1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st),
34 //===----------------------------------------------------------------------===//
35 // TargetInstrInfo callbacks
36 //===----------------------------------------------------------------------===//
38 static unsigned getNumOperandsNoGlue(SDNode *Node) {
39 unsigned N = Node->getNumOperands();
40 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
45 static SDValue findChainOperand(SDNode *Load) {
46 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
47 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
51 /// \brief Returns true if both nodes have the same value for the given
52 /// operand \p Op, or if both nodes do not have this operand.
53 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
54 unsigned Opc0 = N0->getMachineOpcode();
55 unsigned Opc1 = N1->getMachineOpcode();
57 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
58 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
60 if (Op0Idx == -1 && Op1Idx == -1)
64 if ((Op0Idx == -1 && Op1Idx != -1) ||
65 (Op1Idx == -1 && Op0Idx != -1))
68 // getNamedOperandIdx returns the index for the MachineInstr's operands,
69 // which includes the result as the first operand. We are indexing into the
70 // MachineSDNode's operands, so we need to skip the result operand to get
75 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
78 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
80 int64_t &Offset1) const {
81 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
84 unsigned Opc0 = Load0->getMachineOpcode();
85 unsigned Opc1 = Load1->getMachineOpcode();
87 // Make sure both are actually loads.
88 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
91 if (isDS(Opc0) && isDS(Opc1)) {
93 // FIXME: Handle this case:
94 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
98 if (Load0->getOperand(1) != Load1->getOperand(1))
102 if (findChainOperand(Load0) != findChainOperand(Load1))
105 // Skip read2 / write2 variants for simplicity.
106 // TODO: We should report true if the used offsets are adjacent (excluded
108 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
109 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
112 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
113 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
117 if (isSMRD(Opc0) && isSMRD(Opc1)) {
118 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
121 if (Load0->getOperand(0) != Load1->getOperand(0))
125 if (findChainOperand(Load0) != findChainOperand(Load1))
128 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
129 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
133 // MUBUF and MTBUF can access the same addresses.
134 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
136 // MUBUF and MTBUF have vaddr at different indices.
137 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
138 findChainOperand(Load0) != findChainOperand(Load1) ||
139 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
140 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
143 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
144 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
146 if (OffIdx0 == -1 || OffIdx1 == -1)
149 // getNamedOperandIdx returns the index for MachineInstrs. Since they
150 // inlcude the output in the operand list, but SDNodes don't, we need to
151 // subtract the index by one.
155 SDValue Off0 = Load0->getOperand(OffIdx0);
156 SDValue Off1 = Load1->getOperand(OffIdx1);
158 // The offset might be a FrameIndexSDNode.
159 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
162 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
163 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
170 static bool isStride64(unsigned Opc) {
172 case AMDGPU::DS_READ2ST64_B32:
173 case AMDGPU::DS_READ2ST64_B64:
174 case AMDGPU::DS_WRITE2ST64_B32:
175 case AMDGPU::DS_WRITE2ST64_B64:
182 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
183 unsigned &BaseReg, unsigned &Offset,
184 const TargetRegisterInfo *TRI) const {
185 unsigned Opc = LdSt->getOpcode();
187 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
188 AMDGPU::OpName::offset);
190 // Normal, single offset LDS instruction.
191 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
192 AMDGPU::OpName::addr);
194 BaseReg = AddrReg->getReg();
195 Offset = OffsetImm->getImm();
199 // The 2 offset instructions use offset0 and offset1 instead. We can treat
200 // these as a load with a single offset if the 2 offsets are consecutive. We
201 // will use this for some partially aligned loads.
202 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
203 AMDGPU::OpName::offset0);
204 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
205 AMDGPU::OpName::offset1);
207 uint8_t Offset0 = Offset0Imm->getImm();
208 uint8_t Offset1 = Offset1Imm->getImm();
209 assert(Offset1 > Offset0);
211 if (Offset1 - Offset0 == 1) {
212 // Each of these offsets is in element sized units, so we need to convert
213 // to bytes of the individual reads.
217 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
219 assert(LdSt->mayStore());
220 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
221 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
227 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
228 AMDGPU::OpName::addr);
229 BaseReg = AddrReg->getReg();
230 Offset = EltSize * Offset0;
237 if (isMUBUF(Opc) || isMTBUF(Opc)) {
238 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
241 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
242 AMDGPU::OpName::vaddr);
246 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
247 AMDGPU::OpName::offset);
248 BaseReg = AddrReg->getReg();
249 Offset = OffsetImm->getImm();
254 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
255 AMDGPU::OpName::offset);
259 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
260 AMDGPU::OpName::sbase);
261 BaseReg = SBaseReg->getReg();
262 Offset = OffsetImm->getImm();
269 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
270 MachineInstr *SecondLdSt,
271 unsigned NumLoads) const {
272 unsigned Opc0 = FirstLdSt->getOpcode();
273 unsigned Opc1 = SecondLdSt->getOpcode();
275 // TODO: This needs finer tuning
279 if (isDS(Opc0) && isDS(Opc1))
282 if (isSMRD(Opc0) && isSMRD(Opc1))
285 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
292 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
293 MachineBasicBlock::iterator MI, DebugLoc DL,
294 unsigned DestReg, unsigned SrcReg,
295 bool KillSrc) const {
297 // If we are trying to copy to or from SCC, there is a bug somewhere else in
298 // the backend. While it may be theoretically possible to do this, it should
299 // never be necessary.
300 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
302 static const int16_t Sub0_15[] = {
303 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
304 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
305 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
306 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
309 static const int16_t Sub0_7[] = {
310 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
311 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
314 static const int16_t Sub0_3[] = {
315 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
318 static const int16_t Sub0_2[] = {
319 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
322 static const int16_t Sub0_1[] = {
323 AMDGPU::sub0, AMDGPU::sub1, 0
327 const int16_t *SubIndices;
329 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
330 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
331 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
332 .addReg(SrcReg, getKillRegState(KillSrc));
335 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
336 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
337 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
338 .addReg(SrcReg, getKillRegState(KillSrc));
341 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
342 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
343 Opcode = AMDGPU::S_MOV_B32;
346 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
347 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
348 Opcode = AMDGPU::S_MOV_B32;
351 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
352 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
353 Opcode = AMDGPU::S_MOV_B32;
354 SubIndices = Sub0_15;
356 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
357 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
358 AMDGPU::SReg_32RegClass.contains(SrcReg));
359 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
360 .addReg(SrcReg, getKillRegState(KillSrc));
363 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
364 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
365 AMDGPU::SReg_64RegClass.contains(SrcReg));
366 Opcode = AMDGPU::V_MOV_B32_e32;
369 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
370 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
371 Opcode = AMDGPU::V_MOV_B32_e32;
374 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
375 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
376 AMDGPU::SReg_128RegClass.contains(SrcReg));
377 Opcode = AMDGPU::V_MOV_B32_e32;
380 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
381 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
382 AMDGPU::SReg_256RegClass.contains(SrcReg));
383 Opcode = AMDGPU::V_MOV_B32_e32;
386 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
387 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
388 AMDGPU::SReg_512RegClass.contains(SrcReg));
389 Opcode = AMDGPU::V_MOV_B32_e32;
390 SubIndices = Sub0_15;
393 llvm_unreachable("Can't copy register!");
396 while (unsigned SubIdx = *SubIndices++) {
397 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
398 get(Opcode), RI.getSubReg(DestReg, SubIdx));
400 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
403 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
407 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
410 // Try to map original to commuted opcode
411 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
414 // Try to map commuted to original opcode
415 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
421 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
423 if (DstRC->getSize() == 4) {
424 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
425 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
426 return AMDGPU::S_MOV_B64;
427 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
428 return AMDGPU::V_MOV_B64_PSEUDO;
433 static bool shouldTryToSpillVGPRs(MachineFunction *MF) {
435 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
436 const TargetMachine &TM = MF->getTarget();
438 // FIXME: Even though it can cause problems, we need to enable
439 // spilling at -O0, since the fast register allocator always
440 // spills registers that are live at the end of blocks.
441 return MFI->getShaderType() == ShaderType::COMPUTE &&
442 TM.getOptLevel() == CodeGenOpt::None;
446 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
447 MachineBasicBlock::iterator MI,
448 unsigned SrcReg, bool isKill,
450 const TargetRegisterClass *RC,
451 const TargetRegisterInfo *TRI) const {
452 MachineFunction *MF = MBB.getParent();
453 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
454 DebugLoc DL = MBB.findDebugLoc(MI);
457 if (RI.isSGPRClass(RC)) {
458 // We are only allowed to create one new instruction when spilling
459 // registers, so we need to use pseudo instruction for spilling
461 switch (RC->getSize() * 8) {
462 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
463 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
464 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
465 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
466 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
468 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
469 switch(RC->getSize() * 8) {
470 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
471 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
472 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
473 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
474 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
475 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
480 FrameInfo->setObjectAlignment(FrameIndex, 4);
481 BuildMI(MBB, MI, DL, get(Opcode))
483 .addFrameIndex(FrameIndex);
485 LLVMContext &Ctx = MF->getFunction()->getContext();
486 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
488 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
493 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
494 MachineBasicBlock::iterator MI,
495 unsigned DestReg, int FrameIndex,
496 const TargetRegisterClass *RC,
497 const TargetRegisterInfo *TRI) const {
498 MachineFunction *MF = MBB.getParent();
499 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
500 DebugLoc DL = MBB.findDebugLoc(MI);
503 if (RI.isSGPRClass(RC)){
504 switch(RC->getSize() * 8) {
505 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
506 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
507 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
508 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
509 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
511 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
512 switch(RC->getSize() * 8) {
513 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
514 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
515 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
516 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
517 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
518 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
523 FrameInfo->setObjectAlignment(FrameIndex, 4);
524 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
525 .addFrameIndex(FrameIndex);
527 LLVMContext &Ctx = MF->getFunction()->getContext();
528 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
529 " restore register");
530 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
531 .addReg(AMDGPU::VGPR0);
535 /// \param @Offset Offset in bytes of the FrameIndex being spilled
536 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
537 MachineBasicBlock::iterator MI,
538 RegScavenger *RS, unsigned TmpReg,
539 unsigned FrameOffset,
540 unsigned Size) const {
541 MachineFunction *MF = MBB.getParent();
542 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
543 const AMDGPUSubtarget &ST = MF->getTarget().getSubtarget<AMDGPUSubtarget>();
544 const SIRegisterInfo *TRI =
545 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
546 DebugLoc DL = MBB.findDebugLoc(MI);
547 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
548 unsigned WavefrontSize = ST.getWavefrontSize();
550 unsigned TIDReg = MFI->getTIDReg();
551 if (!MFI->hasCalculatedTID()) {
552 MachineBasicBlock &Entry = MBB.getParent()->front();
553 MachineBasicBlock::iterator Insert = Entry.front();
554 DebugLoc DL = Insert->getDebugLoc();
556 TIDReg = RI.findUnusedVGPR(MF->getRegInfo());
557 if (TIDReg == AMDGPU::NoRegister)
561 if (MFI->getShaderType() == ShaderType::COMPUTE &&
562 WorkGroupSize > WavefrontSize) {
564 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
565 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
566 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
567 unsigned InputPtrReg =
568 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
569 static const unsigned TIDIGRegs[3] = {
570 TIDIGXReg, TIDIGYReg, TIDIGZReg
572 for (unsigned Reg : TIDIGRegs) {
573 if (!Entry.isLiveIn(Reg))
574 Entry.addLiveIn(Reg);
577 RS->enterBasicBlock(&Entry);
578 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
579 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
580 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
582 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
583 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
585 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
587 // NGROUPS.X * NGROUPS.Y
588 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
591 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
592 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
595 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
596 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
600 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
601 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
606 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
611 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e32),
617 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
621 MFI->setTIDReg(TIDReg);
624 // Add FrameIndex to LDS offset
625 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
626 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
633 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
642 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
647 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
648 MachineBasicBlock &MBB = *MI->getParent();
649 DebugLoc DL = MBB.findDebugLoc(MI);
650 switch (MI->getOpcode()) {
651 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
653 case AMDGPU::SI_CONSTDATA_PTR: {
654 unsigned Reg = MI->getOperand(0).getReg();
655 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
656 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
658 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
660 // Add 32-bit offset from this instruction to the start of the constant data.
661 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
663 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
664 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
665 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
668 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
669 .addReg(AMDGPU::SCC, RegState::Implicit);
670 MI->eraseFromParent();
673 case AMDGPU::SGPR_USE:
674 // This is just a placeholder for register allocation.
675 MI->eraseFromParent();
678 case AMDGPU::V_MOV_B64_PSEUDO: {
679 unsigned Dst = MI->getOperand(0).getReg();
680 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
681 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
683 const MachineOperand &SrcOp = MI->getOperand(1);
684 // FIXME: Will this work for 64-bit floating point immediates?
685 assert(!SrcOp.isFPImm());
687 APInt Imm(64, SrcOp.getImm());
688 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
689 .addImm(Imm.getLoBits(32).getZExtValue())
690 .addReg(Dst, RegState::Implicit);
691 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
692 .addImm(Imm.getHiBits(32).getZExtValue())
693 .addReg(Dst, RegState::Implicit);
695 assert(SrcOp.isReg());
696 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
697 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
698 .addReg(Dst, RegState::Implicit);
699 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
700 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
701 .addReg(Dst, RegState::Implicit);
703 MI->eraseFromParent();
710 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
712 if (MI->getNumOperands() < 3)
715 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
716 AMDGPU::OpName::src0);
717 assert(Src0Idx != -1 && "Should always have src0 operand");
719 MachineOperand &Src0 = MI->getOperand(Src0Idx);
723 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
724 AMDGPU::OpName::src1);
728 MachineOperand &Src1 = MI->getOperand(Src1Idx);
730 // Make sure it's legal to commute operands for VOP2.
731 if (isVOP2(MI->getOpcode()) &&
732 (!isOperandLegal(MI, Src0Idx, &Src1) ||
733 !isOperandLegal(MI, Src1Idx, &Src0)))
737 // Allow commuting instructions with Imm or FPImm operands.
738 if (NewMI || (!Src1.isImm() && !Src1.isFPImm()) ||
739 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
743 // Be sure to copy the source modifiers to the right place.
744 if (MachineOperand *Src0Mods
745 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
746 MachineOperand *Src1Mods
747 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
749 int Src0ModsVal = Src0Mods->getImm();
750 if (!Src1Mods && Src0ModsVal != 0)
753 // XXX - This assert might be a lie. It might be useful to have a neg
754 // modifier with 0.0.
755 int Src1ModsVal = Src1Mods->getImm();
756 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
758 Src1Mods->setImm(Src0ModsVal);
759 Src0Mods->setImm(Src1ModsVal);
762 unsigned Reg = Src0.getReg();
763 unsigned SubReg = Src0.getSubReg();
765 Src0.ChangeToImmediate(Src1.getImm());
766 else if (Src1.isFPImm())
767 Src0.ChangeToFPImmediate(Src1.getFPImm());
769 llvm_unreachable("Should only have immediates");
771 Src1.ChangeToRegister(Reg, false);
772 Src1.setSubReg(SubReg);
774 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
778 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
783 // This needs to be implemented because the source modifiers may be inserted
784 // between the true commutable operands, and the base
785 // TargetInstrInfo::commuteInstruction uses it.
786 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
788 unsigned &SrcOpIdx2) const {
789 const MCInstrDesc &MCID = MI->getDesc();
790 if (!MCID.isCommutable())
793 unsigned Opc = MI->getOpcode();
794 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
798 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
800 if (!MI->getOperand(Src0Idx).isReg())
803 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
807 if (!MI->getOperand(Src1Idx).isReg())
810 // If any source modifiers are set, the generic instruction commuting won't
811 // understand how to copy the source modifiers.
812 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
813 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
821 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
822 MachineBasicBlock::iterator I,
824 unsigned SrcReg) const {
825 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
826 DstReg) .addReg(SrcReg);
829 bool SIInstrInfo::isMov(unsigned Opcode) const {
831 default: return false;
832 case AMDGPU::S_MOV_B32:
833 case AMDGPU::S_MOV_B64:
834 case AMDGPU::V_MOV_B32_e32:
835 case AMDGPU::V_MOV_B32_e64:
841 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
842 return RC != &AMDGPU::EXECRegRegClass;
846 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
847 AliasAnalysis *AA) const {
848 switch(MI->getOpcode()) {
849 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
850 case AMDGPU::S_MOV_B32:
851 case AMDGPU::S_MOV_B64:
852 case AMDGPU::V_MOV_B32_e32:
853 return MI->getOperand(1).isImm();
857 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
858 int WidthB, int OffsetB) {
859 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
860 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
861 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
862 return LowOffset + LowWidth <= HighOffset;
865 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
866 MachineInstr *MIb) const {
867 unsigned BaseReg0, Offset0;
868 unsigned BaseReg1, Offset1;
870 if (getLdStBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
871 getLdStBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
872 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
873 "read2 / write2 not expected here yet");
874 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
875 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
876 if (BaseReg0 == BaseReg1 &&
877 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
885 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
887 AliasAnalysis *AA) const {
888 unsigned Opc0 = MIa->getOpcode();
889 unsigned Opc1 = MIb->getOpcode();
891 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
892 "MIa must load from or modify a memory location");
893 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
894 "MIb must load from or modify a memory location");
896 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
899 // XXX - Can we relax this between address spaces?
900 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
903 // TODO: Should we check the address space from the MachineMemOperand? That
904 // would allow us to distinguish objects we know don't alias based on the
905 // underlying addres space, even if it was lowered to a different one,
906 // e.g. private accesses lowered to use MUBUF instructions on a scratch
910 return checkInstOffsetsDoNotOverlap(MIa, MIb);
912 return !isFLAT(Opc1);
915 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
916 if (isMUBUF(Opc1) || isMTBUF(Opc1))
917 return checkInstOffsetsDoNotOverlap(MIa, MIb);
919 return !isFLAT(Opc1) && !isSMRD(Opc1);
924 return checkInstOffsetsDoNotOverlap(MIa, MIb);
926 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
931 return checkInstOffsetsDoNotOverlap(MIa, MIb);
939 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
940 int64_t SVal = Imm.getSExtValue();
941 if (SVal >= -16 && SVal <= 64)
944 if (Imm.getBitWidth() == 64) {
945 uint64_t Val = Imm.getZExtValue();
946 return (DoubleToBits(0.0) == Val) ||
947 (DoubleToBits(1.0) == Val) ||
948 (DoubleToBits(-1.0) == Val) ||
949 (DoubleToBits(0.5) == Val) ||
950 (DoubleToBits(-0.5) == Val) ||
951 (DoubleToBits(2.0) == Val) ||
952 (DoubleToBits(-2.0) == Val) ||
953 (DoubleToBits(4.0) == Val) ||
954 (DoubleToBits(-4.0) == Val);
957 // The actual type of the operand does not seem to matter as long
958 // as the bits match one of the inline immediate values. For example:
960 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
961 // so it is a legal inline immediate.
963 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
964 // floating-point, so it is a legal inline immediate.
965 uint32_t Val = Imm.getZExtValue();
967 return (FloatToBits(0.0f) == Val) ||
968 (FloatToBits(1.0f) == Val) ||
969 (FloatToBits(-1.0f) == Val) ||
970 (FloatToBits(0.5f) == Val) ||
971 (FloatToBits(-0.5f) == Val) ||
972 (FloatToBits(2.0f) == Val) ||
973 (FloatToBits(-2.0f) == Val) ||
974 (FloatToBits(4.0f) == Val) ||
975 (FloatToBits(-4.0f) == Val);
978 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
980 return isInlineConstant(APInt(32, MO.getImm(), true));
983 APFloat FpImm = MO.getFPImm()->getValueAPF();
984 return isInlineConstant(FpImm.bitcastToAPInt());
990 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
991 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
994 static bool compareMachineOp(const MachineOperand &Op0,
995 const MachineOperand &Op1) {
996 if (Op0.getType() != Op1.getType())
999 switch (Op0.getType()) {
1000 case MachineOperand::MO_Register:
1001 return Op0.getReg() == Op1.getReg();
1002 case MachineOperand::MO_Immediate:
1003 return Op0.getImm() == Op1.getImm();
1004 case MachineOperand::MO_FPImmediate:
1005 return Op0.getFPImm() == Op1.getFPImm();
1007 llvm_unreachable("Didn't expect to be comparing these operand types");
1011 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1012 const MachineOperand &MO) const {
1013 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1015 assert(MO.isImm() || MO.isFPImm() || MO.isTargetIndex() || MO.isFI());
1017 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1020 if (OpInfo.RegClass < 0)
1023 if (isLiteralConstant(MO))
1024 return RI.regClassCanUseLiteralConstant(OpInfo.RegClass);
1026 return RI.regClassCanUseInlineConstant(OpInfo.RegClass);
1029 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) const {
1031 case AMDGPUAS::GLOBAL_ADDRESS: {
1032 // MUBUF instructions a 12-bit offset in bytes.
1033 return isUInt<12>(OffsetSize);
1035 case AMDGPUAS::CONSTANT_ADDRESS: {
1036 // SMRD instructions have an 8-bit offset in dwords on SI and
1037 // a 20-bit offset in bytes on VI.
1038 if (RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1039 return isUInt<20>(OffsetSize);
1041 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1043 case AMDGPUAS::LOCAL_ADDRESS:
1044 case AMDGPUAS::REGION_ADDRESS: {
1045 // The single offset versions have a 16-bit offset in bytes.
1046 return isUInt<16>(OffsetSize);
1048 case AMDGPUAS::PRIVATE_ADDRESS:
1049 // Indirect register addressing does not use any offsets.
1055 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1056 return AMDGPU::getVOPe32(Opcode) != -1;
1059 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1060 // The src0_modifier operand is present on all instructions
1061 // that have modifiers.
1063 return AMDGPU::getNamedOperandIdx(Opcode,
1064 AMDGPU::OpName::src0_modifiers) != -1;
1067 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1068 unsigned OpName) const {
1069 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1070 return Mods && Mods->getImm();
1073 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1074 const MachineOperand &MO) const {
1075 // Literal constants use the constant bus.
1076 if (isLiteralConstant(MO))
1079 if (!MO.isReg() || !MO.isUse())
1082 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1083 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1085 // FLAT_SCR is just an SGPR pair.
1086 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1089 // EXEC register uses the constant bus.
1090 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1093 // SGPRs use the constant bus
1094 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1095 (!MO.isImplicit() &&
1096 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1097 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1104 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1105 StringRef &ErrInfo) const {
1106 uint16_t Opcode = MI->getOpcode();
1107 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1108 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1109 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1110 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1112 // Make sure the number of operands is correct.
1113 const MCInstrDesc &Desc = get(Opcode);
1114 if (!Desc.isVariadic() &&
1115 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1116 ErrInfo = "Instruction has wrong number of operands.";
1120 // Make sure the register classes are correct
1121 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1122 switch (Desc.OpInfo[i].OperandType) {
1123 case MCOI::OPERAND_REGISTER: {
1124 if ((MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm()) &&
1125 !isImmOperandLegal(MI, i, MI->getOperand(i))) {
1126 ErrInfo = "Illegal immediate value for operand.";
1131 case MCOI::OPERAND_IMMEDIATE:
1132 // Check if this operand is an immediate.
1133 // FrameIndex operands will be replaced by immediates, so they are
1135 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
1136 !MI->getOperand(i).isFI()) {
1137 ErrInfo = "Expected immediate, but got non-immediate";
1145 if (!MI->getOperand(i).isReg())
1148 int RegClass = Desc.OpInfo[i].RegClass;
1149 if (RegClass != -1) {
1150 unsigned Reg = MI->getOperand(i).getReg();
1151 if (TargetRegisterInfo::isVirtualRegister(Reg))
1154 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1155 if (!RC->contains(Reg)) {
1156 ErrInfo = "Operand has incorrect register class.";
1164 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1165 // Only look at the true operands. Only a real operand can use the constant
1166 // bus, and we don't want to check pseudo-operands like the source modifier
1168 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1170 unsigned ConstantBusCount = 0;
1171 unsigned SGPRUsed = AMDGPU::NoRegister;
1172 for (int OpIdx : OpIndices) {
1176 const MachineOperand &MO = MI->getOperand(OpIdx);
1177 if (usesConstantBus(MRI, MO)) {
1179 if (MO.getReg() != SGPRUsed)
1181 SGPRUsed = MO.getReg();
1187 if (ConstantBusCount > 1) {
1188 ErrInfo = "VOP* instruction uses the constant bus more than once";
1193 // Verify SRC1 for VOP2 and VOPC
1194 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
1195 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1196 if (Src1.isImm() || Src1.isFPImm()) {
1197 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
1203 if (isVOP3(Opcode)) {
1204 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
1205 ErrInfo = "VOP3 src0 cannot be a literal constant.";
1208 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
1209 ErrInfo = "VOP3 src1 cannot be a literal constant.";
1212 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
1213 ErrInfo = "VOP3 src2 cannot be a literal constant.";
1218 // Verify misc. restrictions on specific instructions.
1219 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1220 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1221 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1222 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1223 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1224 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1225 if (!compareMachineOp(Src0, Src1) &&
1226 !compareMachineOp(Src0, Src2)) {
1227 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1236 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1237 switch (MI.getOpcode()) {
1238 default: return AMDGPU::INSTRUCTION_LIST_END;
1239 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1240 case AMDGPU::COPY: return AMDGPU::COPY;
1241 case AMDGPU::PHI: return AMDGPU::PHI;
1242 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1243 case AMDGPU::S_MOV_B32:
1244 return MI.getOperand(1).isReg() ?
1245 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1246 case AMDGPU::S_ADD_I32:
1247 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1248 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1249 case AMDGPU::S_SUB_I32:
1250 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1251 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1252 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1253 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1254 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1255 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1256 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1257 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1258 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1259 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1260 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1261 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1262 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1263 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1264 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1265 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1266 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1267 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1268 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1269 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1270 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1271 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1272 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1273 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1274 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1275 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1276 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1277 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1278 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1279 case AMDGPU::S_LOAD_DWORD_IMM:
1280 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1281 case AMDGPU::S_LOAD_DWORDX2_IMM:
1282 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1283 case AMDGPU::S_LOAD_DWORDX4_IMM:
1284 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1285 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
1286 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1287 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1291 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1292 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1295 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1296 unsigned OpNo) const {
1297 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1298 const MCInstrDesc &Desc = get(MI.getOpcode());
1299 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1300 Desc.OpInfo[OpNo].RegClass == -1) {
1301 unsigned Reg = MI.getOperand(OpNo).getReg();
1303 if (TargetRegisterInfo::isVirtualRegister(Reg))
1304 return MRI.getRegClass(Reg);
1305 return RI.getRegClass(Reg);
1308 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1309 return RI.getRegClass(RCID);
1312 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1313 switch (MI.getOpcode()) {
1315 case AMDGPU::REG_SEQUENCE:
1317 case AMDGPU::INSERT_SUBREG:
1318 return RI.hasVGPRs(getOpRegClass(MI, 0));
1320 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1324 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1325 MachineBasicBlock::iterator I = MI;
1326 MachineBasicBlock *MBB = MI->getParent();
1327 MachineOperand &MO = MI->getOperand(OpIdx);
1328 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1329 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1330 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1331 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1333 Opcode = AMDGPU::COPY;
1334 else if (RI.isSGPRClass(RC))
1335 Opcode = AMDGPU::S_MOV_B32;
1338 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1339 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1340 VRC = &AMDGPU::VReg_64RegClass;
1342 VRC = &AMDGPU::VReg_32RegClass;
1344 unsigned Reg = MRI.createVirtualRegister(VRC);
1345 DebugLoc DL = MBB->findDebugLoc(I);
1346 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1348 MO.ChangeToRegister(Reg, false);
1351 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1352 MachineRegisterInfo &MRI,
1353 MachineOperand &SuperReg,
1354 const TargetRegisterClass *SuperRC,
1356 const TargetRegisterClass *SubRC)
1358 assert(SuperReg.isReg());
1360 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1361 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1363 // Just in case the super register is itself a sub-register, copy it to a new
1364 // value so we don't need to worry about merging its subreg index with the
1365 // SubIdx passed to this function. The register coalescer should be able to
1366 // eliminate this extra copy.
1367 MachineBasicBlock *MBB = MI->getParent();
1368 DebugLoc DL = MI->getDebugLoc();
1370 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1371 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1373 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1374 .addReg(NewSuperReg, 0, SubIdx);
1379 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1380 MachineBasicBlock::iterator MII,
1381 MachineRegisterInfo &MRI,
1383 const TargetRegisterClass *SuperRC,
1385 const TargetRegisterClass *SubRC) const {
1387 // XXX - Is there a better way to do this?
1388 if (SubIdx == AMDGPU::sub0)
1389 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1390 if (SubIdx == AMDGPU::sub1)
1391 return MachineOperand::CreateImm(Op.getImm() >> 32);
1393 llvm_unreachable("Unhandled register index for immediate");
1396 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1398 return MachineOperand::CreateReg(SubReg, false);
1401 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1402 MachineBasicBlock::iterator MI,
1403 MachineRegisterInfo &MRI,
1404 const TargetRegisterClass *RC,
1405 const MachineOperand &Op) const {
1406 MachineBasicBlock *MBB = MI->getParent();
1407 DebugLoc DL = MI->getDebugLoc();
1408 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1409 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1410 unsigned Dst = MRI.createVirtualRegister(RC);
1412 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1414 .addImm(Op.getImm() & 0xFFFFFFFF);
1415 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1417 .addImm(Op.getImm() >> 32);
1419 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1421 .addImm(AMDGPU::sub0)
1423 .addImm(AMDGPU::sub1);
1425 Worklist.push_back(Lo);
1426 Worklist.push_back(Hi);
1431 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1432 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1433 assert(Inst->getNumExplicitOperands() == 3);
1434 MachineOperand Op1 = Inst->getOperand(1);
1435 Inst->RemoveOperand(1);
1436 Inst->addOperand(Op1);
1439 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1440 const MachineOperand *MO) const {
1441 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1442 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1443 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1444 const TargetRegisterClass *DefinedRC =
1445 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1447 MO = &MI->getOperand(OpIdx);
1449 if (isVALU(InstDesc.Opcode) && usesConstantBus(MRI, *MO)) {
1451 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1452 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1455 if (usesConstantBus(MRI, MI->getOperand(i)) &&
1456 MI->getOperand(i).isReg() && MI->getOperand(i).getReg() != SGPRUsed) {
1464 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1466 // In order to be legal, the common sub-class must be equal to the
1467 // class of the current operand. For example:
1469 // v_mov_b32 s0 ; Operand defined as vsrc_32
1470 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1472 // s_sendmsg 0, s0 ; Operand defined as m0reg
1473 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1474 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1478 // Handle non-register types that are treated like immediates.
1479 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1482 // This operand expects an immediate.
1486 return isImmOperandLegal(MI, OpIdx, *MO);
1489 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1490 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1492 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1493 AMDGPU::OpName::src0);
1494 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1495 AMDGPU::OpName::src1);
1496 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1497 AMDGPU::OpName::src2);
1500 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1502 if (!isOperandLegal(MI, Src0Idx))
1503 legalizeOpWithMove(MI, Src0Idx);
1506 if (isOperandLegal(MI, Src1Idx))
1509 // Usually src0 of VOP2 instructions allow more types of inputs
1510 // than src1, so try to commute the instruction to decrease our
1511 // chances of having to insert a MOV instruction to legalize src1.
1512 if (MI->isCommutable()) {
1513 if (commuteInstruction(MI))
1514 // If we are successful in commuting, then we know MI is legal, so
1519 legalizeOpWithMove(MI, Src1Idx);
1523 // XXX - Do any VOP3 instructions read VCC?
1525 if (isVOP3(MI->getOpcode())) {
1526 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1528 // Find the one SGPR operand we are allowed to use.
1529 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1531 for (unsigned i = 0; i < 3; ++i) {
1532 int Idx = VOP3Idx[i];
1535 MachineOperand &MO = MI->getOperand(Idx);
1538 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1539 continue; // VGPRs are legal
1541 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1543 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1544 SGPRReg = MO.getReg();
1545 // We can use one SGPR in each VOP3 instruction.
1548 } else if (!isLiteralConstant(MO)) {
1549 // If it is not a register and not a literal constant, then it must be
1550 // an inline constant which is always legal.
1553 // If we make it this far, then the operand is not legal and we must
1555 legalizeOpWithMove(MI, Idx);
1559 // Legalize REG_SEQUENCE and PHI
1560 // The register class of the operands much be the same type as the register
1561 // class of the output.
1562 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1563 MI->getOpcode() == AMDGPU::PHI) {
1564 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1565 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1566 if (!MI->getOperand(i).isReg() ||
1567 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1569 const TargetRegisterClass *OpRC =
1570 MRI.getRegClass(MI->getOperand(i).getReg());
1571 if (RI.hasVGPRs(OpRC)) {
1578 // If any of the operands are VGPR registers, then they all most be
1579 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1581 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1584 VRC = RI.getEquivalentVGPRClass(SRC);
1591 // Update all the operands so they have the same type.
1592 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1593 if (!MI->getOperand(i).isReg() ||
1594 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1596 unsigned DstReg = MRI.createVirtualRegister(RC);
1597 MachineBasicBlock *InsertBB;
1598 MachineBasicBlock::iterator Insert;
1599 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1600 InsertBB = MI->getParent();
1603 // MI is a PHI instruction.
1604 InsertBB = MI->getOperand(i + 1).getMBB();
1605 Insert = InsertBB->getFirstTerminator();
1607 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1608 get(AMDGPU::COPY), DstReg)
1609 .addOperand(MI->getOperand(i));
1610 MI->getOperand(i).setReg(DstReg);
1614 // Legalize INSERT_SUBREG
1615 // src0 must have the same register class as dst
1616 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1617 unsigned Dst = MI->getOperand(0).getReg();
1618 unsigned Src0 = MI->getOperand(1).getReg();
1619 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1620 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1621 if (DstRC != Src0RC) {
1622 MachineBasicBlock &MBB = *MI->getParent();
1623 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1624 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1626 MI->getOperand(1).setReg(NewSrc0);
1631 // Legalize MUBUF* instructions
1632 // FIXME: If we start using the non-addr64 instructions for compute, we
1633 // may need to legalize them here.
1635 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1636 if (SRsrcIdx != -1) {
1637 // We have an MUBUF instruction
1638 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1639 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1640 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1641 RI.getRegClass(SRsrcRC))) {
1642 // The operands are legal.
1643 // FIXME: We may need to legalize operands besided srsrc.
1647 MachineBasicBlock &MBB = *MI->getParent();
1648 // Extract the the ptr from the resource descriptor.
1650 // SRsrcPtrLo = srsrc:sub0
1651 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1652 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1654 // SRsrcPtrHi = srsrc:sub1
1655 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1656 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1658 // Create an empty resource descriptor
1659 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1660 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1661 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1662 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1663 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1666 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1670 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1671 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1673 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1675 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1676 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1678 .addImm(RsrcDataFormat >> 32);
1680 // NewSRsrc = {Zero64, SRsrcFormat}
1681 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1684 .addImm(AMDGPU::sub0_sub1)
1685 .addReg(SRsrcFormatLo)
1686 .addImm(AMDGPU::sub2)
1687 .addReg(SRsrcFormatHi)
1688 .addImm(AMDGPU::sub3);
1690 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1691 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1692 unsigned NewVAddrLo;
1693 unsigned NewVAddrHi;
1695 // This is already an ADDR64 instruction so we need to add the pointer
1696 // extracted from the resource descriptor to the current value of VAddr.
1697 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1698 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1700 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1701 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1704 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1705 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1707 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1708 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1711 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1712 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1713 .addReg(AMDGPU::VCC, RegState::Implicit);
1716 // This instructions is the _OFFSET variant, so we need to convert it to
1718 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1719 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1720 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1721 assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
1722 "with non-zero soffset is not implemented");
1725 // Create the new instruction.
1726 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1727 MachineInstr *Addr64 =
1728 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1731 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1732 // This will be replaced later
1733 // with the new value of vaddr.
1734 .addOperand(*Offset);
1736 MI->removeFromParent();
1739 NewVAddrLo = SRsrcPtrLo;
1740 NewVAddrHi = SRsrcPtrHi;
1741 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1742 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1745 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1746 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1749 .addImm(AMDGPU::sub0)
1751 .addImm(AMDGPU::sub1);
1754 // Update the instruction to use NewVaddr
1755 VAddr->setReg(NewVAddr);
1756 // Update the instruction to use NewSRsrc
1757 SRsrc->setReg(NewSRsrc);
1761 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1762 const TargetRegisterClass *HalfRC,
1763 unsigned HalfImmOp, unsigned HalfSGPROp,
1764 MachineInstr *&Lo, MachineInstr *&Hi) const {
1766 DebugLoc DL = MI->getDebugLoc();
1767 MachineBasicBlock *MBB = MI->getParent();
1768 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1769 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1770 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1771 unsigned HalfSize = HalfRC->getSize();
1772 const MachineOperand *OffOp =
1773 getNamedOperand(*MI, AMDGPU::OpName::offset);
1774 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1776 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1779 bool isVI = RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
1780 unsigned OffScale = isVI ? 1 : 4;
1781 // Handle the _IMM variant
1782 unsigned LoOffset = OffOp->getImm() * OffScale;
1783 unsigned HiOffset = LoOffset + HalfSize;
1784 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1786 .addImm(LoOffset / OffScale);
1788 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1789 unsigned OffsetSGPR =
1790 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1791 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1792 .addImm(HiOffset); // The offset in register is in bytes.
1793 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1795 .addReg(OffsetSGPR);
1797 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1799 .addImm(HiOffset / OffScale);
1802 // Handle the _SGPR variant
1803 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1804 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1807 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1808 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1811 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1813 .addReg(OffsetSGPR);
1816 unsigned SubLo, SubHi;
1819 SubLo = AMDGPU::sub0;
1820 SubHi = AMDGPU::sub1;
1823 SubLo = AMDGPU::sub0_sub1;
1824 SubHi = AMDGPU::sub2_sub3;
1827 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1828 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1831 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1832 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1835 llvm_unreachable("Unhandled HalfSize");
1838 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1839 .addOperand(MI->getOperand(0))
1846 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1847 MachineBasicBlock *MBB = MI->getParent();
1848 switch (MI->getOpcode()) {
1849 case AMDGPU::S_LOAD_DWORD_IMM:
1850 case AMDGPU::S_LOAD_DWORD_SGPR:
1851 case AMDGPU::S_LOAD_DWORDX2_IMM:
1852 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1853 case AMDGPU::S_LOAD_DWORDX4_IMM:
1854 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1855 unsigned NewOpcode = getVALUOp(*MI);
1859 if (MI->getOperand(2).isReg()) {
1860 RegOffset = MI->getOperand(2).getReg();
1863 assert(MI->getOperand(2).isImm());
1864 // SMRD instructions take a dword offsets on SI and byte offset on VI
1865 // and MUBUF instructions always take a byte offset.
1866 ImmOffset = MI->getOperand(2).getImm();
1867 if (RI.ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1869 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1871 if (isUInt<12>(ImmOffset)) {
1872 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1876 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1883 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1884 unsigned DWord0 = RegOffset;
1885 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1886 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1887 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1888 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1890 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1892 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1893 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1894 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1895 .addImm(RsrcDataFormat >> 32);
1896 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1898 .addImm(AMDGPU::sub0)
1900 .addImm(AMDGPU::sub1)
1902 .addImm(AMDGPU::sub2)
1904 .addImm(AMDGPU::sub3);
1905 MI->setDesc(get(NewOpcode));
1906 if (MI->getOperand(2).isReg()) {
1907 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1909 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1911 MI->getOperand(1).setReg(SRsrc);
1912 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1914 const TargetRegisterClass *NewDstRC =
1915 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1917 unsigned DstReg = MI->getOperand(0).getReg();
1918 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1919 MRI.replaceRegWith(DstReg, NewDstReg);
1922 case AMDGPU::S_LOAD_DWORDX8_IMM:
1923 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1924 MachineInstr *Lo, *Hi;
1925 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1926 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1927 MI->eraseFromParent();
1928 moveSMRDToVALU(Lo, MRI);
1929 moveSMRDToVALU(Hi, MRI);
1933 case AMDGPU::S_LOAD_DWORDX16_IMM:
1934 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1935 MachineInstr *Lo, *Hi;
1936 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1937 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1938 MI->eraseFromParent();
1939 moveSMRDToVALU(Lo, MRI);
1940 moveSMRDToVALU(Hi, MRI);
1946 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1947 SmallVector<MachineInstr *, 128> Worklist;
1948 Worklist.push_back(&TopInst);
1950 while (!Worklist.empty()) {
1951 MachineInstr *Inst = Worklist.pop_back_val();
1952 MachineBasicBlock *MBB = Inst->getParent();
1953 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1955 unsigned Opcode = Inst->getOpcode();
1956 unsigned NewOpcode = getVALUOp(*Inst);
1958 // Handle some special cases
1961 if (isSMRD(Inst->getOpcode())) {
1962 moveSMRDToVALU(Inst, MRI);
1965 case AMDGPU::S_MOV_B64: {
1966 DebugLoc DL = Inst->getDebugLoc();
1968 // If the source operand is a register we can replace this with a
1970 if (Inst->getOperand(1).isReg()) {
1971 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1972 .addOperand(Inst->getOperand(0))
1973 .addOperand(Inst->getOperand(1));
1974 Worklist.push_back(Copy);
1976 // Otherwise, we need to split this into two movs, because there is
1977 // no 64-bit VALU move instruction.
1978 unsigned Reg = Inst->getOperand(0).getReg();
1979 unsigned Dst = split64BitImm(Worklist,
1982 MRI.getRegClass(Reg),
1983 Inst->getOperand(1));
1984 MRI.replaceRegWith(Reg, Dst);
1986 Inst->eraseFromParent();
1989 case AMDGPU::S_AND_B64:
1990 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1991 Inst->eraseFromParent();
1994 case AMDGPU::S_OR_B64:
1995 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1996 Inst->eraseFromParent();
1999 case AMDGPU::S_XOR_B64:
2000 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
2001 Inst->eraseFromParent();
2004 case AMDGPU::S_NOT_B64:
2005 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
2006 Inst->eraseFromParent();
2009 case AMDGPU::S_BCNT1_I32_B64:
2010 splitScalar64BitBCNT(Worklist, Inst);
2011 Inst->eraseFromParent();
2014 case AMDGPU::S_BFE_I64: {
2015 splitScalar64BitBFE(Worklist, Inst);
2016 Inst->eraseFromParent();
2020 case AMDGPU::S_LSHL_B32:
2021 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2022 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2026 case AMDGPU::S_ASHR_I32:
2027 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2028 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2032 case AMDGPU::S_LSHR_B32:
2033 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2034 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2039 case AMDGPU::S_BFE_U64:
2040 case AMDGPU::S_BFM_B64:
2041 llvm_unreachable("Moving this op to VALU not implemented");
2044 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2045 // We cannot move this instruction to the VALU, so we should try to
2046 // legalize its operands instead.
2047 legalizeOperands(Inst);
2051 // Use the new VALU Opcode.
2052 const MCInstrDesc &NewDesc = get(NewOpcode);
2053 Inst->setDesc(NewDesc);
2055 // Remove any references to SCC. Vector instructions can't read from it, and
2056 // We're just about to add the implicit use / defs of VCC, and we don't want
2058 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2059 MachineOperand &Op = Inst->getOperand(i);
2060 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2061 Inst->RemoveOperand(i);
2064 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2065 // We are converting these to a BFE, so we need to add the missing
2066 // operands for the size and offset.
2067 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2068 Inst->addOperand(MachineOperand::CreateImm(0));
2069 Inst->addOperand(MachineOperand::CreateImm(Size));
2071 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2072 // The VALU version adds the second operand to the result, so insert an
2074 Inst->addOperand(MachineOperand::CreateImm(0));
2077 addDescImplicitUseDef(NewDesc, Inst);
2079 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2080 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2081 // If we need to move this to VGPRs, we need to unpack the second operand
2082 // back into the 2 separate ones for bit offset and width.
2083 assert(OffsetWidthOp.isImm() &&
2084 "Scalar BFE is only implemented for constant width and offset");
2085 uint32_t Imm = OffsetWidthOp.getImm();
2087 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2088 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2089 Inst->RemoveOperand(2); // Remove old immediate.
2090 Inst->addOperand(MachineOperand::CreateImm(Offset));
2091 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2094 // Update the destination register class.
2096 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2099 // For target instructions, getOpRegClass just returns the virtual
2100 // register class associated with the operand, so we need to find an
2101 // equivalent VGPR register class in order to move the instruction to the
2105 case AMDGPU::REG_SEQUENCE:
2106 case AMDGPU::INSERT_SUBREG:
2107 if (RI.hasVGPRs(NewDstRC))
2109 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2117 unsigned DstReg = Inst->getOperand(0).getReg();
2118 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2119 MRI.replaceRegWith(DstReg, NewDstReg);
2121 // Legalize the operands
2122 legalizeOperands(Inst);
2124 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
2125 E = MRI.use_end(); I != E; ++I) {
2126 MachineInstr &UseMI = *I->getParent();
2127 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2128 Worklist.push_back(&UseMI);
2134 //===----------------------------------------------------------------------===//
2135 // Indirect addressing callbacks
2136 //===----------------------------------------------------------------------===//
2138 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2139 unsigned Channel) const {
2140 assert(Channel == 0);
2144 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2145 return &AMDGPU::VReg_32RegClass;
2148 void SIInstrInfo::splitScalar64BitUnaryOp(
2149 SmallVectorImpl<MachineInstr *> &Worklist,
2151 unsigned Opcode) const {
2152 MachineBasicBlock &MBB = *Inst->getParent();
2153 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2155 MachineOperand &Dest = Inst->getOperand(0);
2156 MachineOperand &Src0 = Inst->getOperand(1);
2157 DebugLoc DL = Inst->getDebugLoc();
2159 MachineBasicBlock::iterator MII = Inst;
2161 const MCInstrDesc &InstDesc = get(Opcode);
2162 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2163 MRI.getRegClass(Src0.getReg()) :
2164 &AMDGPU::SGPR_32RegClass;
2166 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2168 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2169 AMDGPU::sub0, Src0SubRC);
2171 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2172 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2174 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2175 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2176 .addOperand(SrcReg0Sub0);
2178 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2179 AMDGPU::sub1, Src0SubRC);
2181 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2182 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2183 .addOperand(SrcReg0Sub1);
2185 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2186 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2188 .addImm(AMDGPU::sub0)
2190 .addImm(AMDGPU::sub1);
2192 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2194 // Try to legalize the operands in case we need to swap the order to keep it
2196 Worklist.push_back(LoHalf);
2197 Worklist.push_back(HiHalf);
2200 void SIInstrInfo::splitScalar64BitBinaryOp(
2201 SmallVectorImpl<MachineInstr *> &Worklist,
2203 unsigned Opcode) const {
2204 MachineBasicBlock &MBB = *Inst->getParent();
2205 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2207 MachineOperand &Dest = Inst->getOperand(0);
2208 MachineOperand &Src0 = Inst->getOperand(1);
2209 MachineOperand &Src1 = Inst->getOperand(2);
2210 DebugLoc DL = Inst->getDebugLoc();
2212 MachineBasicBlock::iterator MII = Inst;
2214 const MCInstrDesc &InstDesc = get(Opcode);
2215 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2216 MRI.getRegClass(Src0.getReg()) :
2217 &AMDGPU::SGPR_32RegClass;
2219 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2220 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2221 MRI.getRegClass(Src1.getReg()) :
2222 &AMDGPU::SGPR_32RegClass;
2224 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2226 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2227 AMDGPU::sub0, Src0SubRC);
2228 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2229 AMDGPU::sub0, Src1SubRC);
2231 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2232 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2234 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2235 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2236 .addOperand(SrcReg0Sub0)
2237 .addOperand(SrcReg1Sub0);
2239 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2240 AMDGPU::sub1, Src0SubRC);
2241 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2242 AMDGPU::sub1, Src1SubRC);
2244 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2245 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2246 .addOperand(SrcReg0Sub1)
2247 .addOperand(SrcReg1Sub1);
2249 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2250 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2252 .addImm(AMDGPU::sub0)
2254 .addImm(AMDGPU::sub1);
2256 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2258 // Try to legalize the operands in case we need to swap the order to keep it
2260 Worklist.push_back(LoHalf);
2261 Worklist.push_back(HiHalf);
2264 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2265 MachineInstr *Inst) const {
2266 MachineBasicBlock &MBB = *Inst->getParent();
2267 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2269 MachineBasicBlock::iterator MII = Inst;
2270 DebugLoc DL = Inst->getDebugLoc();
2272 MachineOperand &Dest = Inst->getOperand(0);
2273 MachineOperand &Src = Inst->getOperand(1);
2275 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
2276 const TargetRegisterClass *SrcRC = Src.isReg() ?
2277 MRI.getRegClass(Src.getReg()) :
2278 &AMDGPU::SGPR_32RegClass;
2280 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2281 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2283 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2285 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2286 AMDGPU::sub0, SrcSubRC);
2287 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2288 AMDGPU::sub1, SrcSubRC);
2290 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2291 .addOperand(SrcRegSub0)
2294 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2295 .addOperand(SrcRegSub1)
2298 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2300 Worklist.push_back(First);
2301 Worklist.push_back(Second);
2304 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2305 MachineInstr *Inst) const {
2306 MachineBasicBlock &MBB = *Inst->getParent();
2307 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2308 MachineBasicBlock::iterator MII = Inst;
2309 DebugLoc DL = Inst->getDebugLoc();
2311 MachineOperand &Dest = Inst->getOperand(0);
2312 uint32_t Imm = Inst->getOperand(2).getImm();
2313 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2314 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2318 // Only sext_inreg cases handled.
2319 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2324 if (BitWidth < 32) {
2325 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2326 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2327 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2329 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2330 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2334 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2338 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2340 .addImm(AMDGPU::sub0)
2342 .addImm(AMDGPU::sub1);
2344 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2348 MachineOperand &Src = Inst->getOperand(1);
2349 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2350 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2352 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2354 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2356 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2357 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2358 .addImm(AMDGPU::sub0)
2360 .addImm(AMDGPU::sub1);
2362 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2365 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2366 MachineInstr *Inst) const {
2367 // Add the implict and explicit register definitions.
2368 if (NewDesc.ImplicitUses) {
2369 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2370 unsigned Reg = NewDesc.ImplicitUses[i];
2371 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2375 if (NewDesc.ImplicitDefs) {
2376 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2377 unsigned Reg = NewDesc.ImplicitDefs[i];
2378 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2383 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2384 int OpIndices[3]) const {
2385 const MCInstrDesc &Desc = get(MI->getOpcode());
2387 // Find the one SGPR operand we are allowed to use.
2388 unsigned SGPRReg = AMDGPU::NoRegister;
2390 // First we need to consider the instruction's operand requirements before
2391 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2392 // of VCC, but we are still bound by the constant bus requirement to only use
2395 // If the operand's class is an SGPR, we can never move it.
2397 for (const MachineOperand &MO : MI->implicit_operands()) {
2398 // We only care about reads.
2402 if (MO.getReg() == AMDGPU::VCC)
2405 if (MO.getReg() == AMDGPU::FLAT_SCR)
2406 return AMDGPU::FLAT_SCR;
2409 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2410 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2412 for (unsigned i = 0; i < 3; ++i) {
2413 int Idx = OpIndices[i];
2417 const MachineOperand &MO = MI->getOperand(Idx);
2418 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2419 SGPRReg = MO.getReg();
2421 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2422 UsedSGPRs[i] = MO.getReg();
2425 if (SGPRReg != AMDGPU::NoRegister)
2428 // We don't have a required SGPR operand, so we have a bit more freedom in
2429 // selecting operands to move.
2431 // Try to select the most used SGPR. If an SGPR is equal to one of the
2432 // others, we choose that.
2435 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2436 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2438 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2439 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2440 SGPRReg = UsedSGPRs[0];
2443 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2444 if (UsedSGPRs[1] == UsedSGPRs[2])
2445 SGPRReg = UsedSGPRs[1];
2451 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2452 MachineBasicBlock *MBB,
2453 MachineBasicBlock::iterator I,
2455 unsigned Address, unsigned OffsetReg) const {
2456 const DebugLoc &DL = MBB->findDebugLoc(I);
2457 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
2458 getIndirectIndexBegin(*MBB->getParent()));
2460 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2461 .addReg(IndirectBaseReg, RegState::Define)
2462 .addOperand(I->getOperand(0))
2463 .addReg(IndirectBaseReg)
2469 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2470 MachineBasicBlock *MBB,
2471 MachineBasicBlock::iterator I,
2473 unsigned Address, unsigned OffsetReg) const {
2474 const DebugLoc &DL = MBB->findDebugLoc(I);
2475 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
2476 getIndirectIndexBegin(*MBB->getParent()));
2478 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2479 .addOperand(I->getOperand(0))
2480 .addOperand(I->getOperand(1))
2481 .addReg(IndirectBaseReg)
2487 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2488 const MachineFunction &MF) const {
2489 int End = getIndirectIndexEnd(MF);
2490 int Begin = getIndirectIndexBegin(MF);
2496 for (int Index = Begin; Index <= End; ++Index)
2497 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
2499 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2500 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2502 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2503 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2505 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2506 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2508 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2509 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2511 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2512 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2515 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2516 unsigned OperandName) const {
2517 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2521 return &MI.getOperand(Idx);
2524 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2525 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2526 if (ST.isAmdHsaOS())
2527 RsrcDataFormat |= (1ULL << 56);
2529 return RsrcDataFormat;