1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/MC/MCInstrDesc.h"
25 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
26 : AMDGPUInstrInfo(tm),
30 const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
35 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator MI, DebugLoc DL,
37 unsigned DestReg, unsigned SrcReg,
39 // If we are trying to copy to or from SCC, there is a bug somewhere else in
40 // the backend. While it may be theoretically possible to do this, it should
41 // never be necessary.
42 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
44 if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
45 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
46 AMDGPU::SReg_64RegClass.contains(SrcReg));
47 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub0))
48 .addReg(RI.getSubReg(SrcReg, AMDGPU::sub0), getKillRegState(KillSrc))
49 .addReg(DestReg, RegState::Define | RegState::Implicit);
50 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub1))
51 .addReg(RI.getSubReg(SrcReg, AMDGPU::sub1), getKillRegState(KillSrc));
52 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
53 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
54 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
55 .addReg(SrcReg, getKillRegState(KillSrc));
56 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
57 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
58 AMDGPU::SReg_32RegClass.contains(SrcReg));
59 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
60 .addReg(SrcReg, getKillRegState(KillSrc));
62 assert(AMDGPU::SReg_32RegClass.contains(DestReg));
63 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
64 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
65 .addReg(SrcReg, getKillRegState(KillSrc));
69 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
71 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
72 MachineInstrBuilder MIB(*MF, MI);
73 MIB.addReg(DstReg, RegState::Define);
80 bool SIInstrInfo::isMov(unsigned Opcode) const {
82 default: return false;
83 case AMDGPU::S_MOV_B32:
84 case AMDGPU::S_MOV_B64:
85 case AMDGPU::V_MOV_B32_e32:
86 case AMDGPU::V_MOV_B32_e64:
87 case AMDGPU::V_MOV_IMM_F32:
88 case AMDGPU::V_MOV_IMM_I32:
89 case AMDGPU::S_MOV_IMM_I32:
95 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
96 return RC != &AMDGPU::EXECRegRegClass;
99 //===----------------------------------------------------------------------===//
100 // Indirect addressing callbacks
101 //===----------------------------------------------------------------------===//
103 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
104 unsigned Channel) const {
105 assert(Channel == 0);
110 int SIInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
111 llvm_unreachable("Unimplemented");
114 int SIInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
115 llvm_unreachable("Unimplemented");
118 const TargetRegisterClass *SIInstrInfo::getIndirectAddrStoreRegClass(
119 unsigned SourceReg) const {
120 llvm_unreachable("Unimplemented");
123 const TargetRegisterClass *SIInstrInfo::getIndirectAddrLoadRegClass() const {
124 llvm_unreachable("Unimplemented");
127 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
128 MachineBasicBlock *MBB,
129 MachineBasicBlock::iterator I,
131 unsigned Address, unsigned OffsetReg) const {
132 llvm_unreachable("Unimplemented");
135 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
136 MachineBasicBlock *MBB,
137 MachineBasicBlock::iterator I,
139 unsigned Address, unsigned OffsetReg) const {
140 llvm_unreachable("Unimplemented");
143 const TargetRegisterClass *SIInstrInfo::getSuperIndirectRegClass() const {
144 llvm_unreachable("Unimplemented");