1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/MC/MCInstrDesc.h"
26 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
27 : AMDGPUInstrInfo(tm),
30 //===----------------------------------------------------------------------===//
31 // TargetInstrInfo callbacks
32 //===----------------------------------------------------------------------===//
35 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator MI, DebugLoc DL,
37 unsigned DestReg, unsigned SrcReg,
40 // If we are trying to copy to or from SCC, there is a bug somewhere else in
41 // the backend. While it may be theoretically possible to do this, it should
42 // never be necessary.
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
45 static const int16_t Sub0_15[] = {
46 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
47 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
48 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
49 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
52 static const int16_t Sub0_7[] = {
53 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
54 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
57 static const int16_t Sub0_3[] = {
58 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
61 static const int16_t Sub0_2[] = {
62 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
65 static const int16_t Sub0_1[] = {
66 AMDGPU::sub0, AMDGPU::sub1, 0
70 const int16_t *SubIndices;
72 if (AMDGPU::M0 == DestReg) {
73 // Check if M0 isn't already set to this value
74 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
75 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
77 if (!I->definesRegister(AMDGPU::M0))
80 unsigned Opc = I->getOpcode();
81 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
84 if (!I->readsRegister(SrcReg))
87 // The copy isn't necessary
92 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
93 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
94 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
95 .addReg(SrcReg, getKillRegState(KillSrc));
98 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
99 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
100 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
101 .addReg(SrcReg, getKillRegState(KillSrc));
104 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
105 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
106 Opcode = AMDGPU::S_MOV_B32;
109 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
110 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
111 Opcode = AMDGPU::S_MOV_B32;
114 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
115 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
116 Opcode = AMDGPU::S_MOV_B32;
117 SubIndices = Sub0_15;
119 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
120 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
121 AMDGPU::SReg_32RegClass.contains(SrcReg));
122 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
123 .addReg(SrcReg, getKillRegState(KillSrc));
126 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
127 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
128 AMDGPU::SReg_64RegClass.contains(SrcReg));
129 Opcode = AMDGPU::V_MOV_B32_e32;
132 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
133 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
134 Opcode = AMDGPU::V_MOV_B32_e32;
137 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
138 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
139 AMDGPU::SReg_128RegClass.contains(SrcReg));
140 Opcode = AMDGPU::V_MOV_B32_e32;
143 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
144 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
145 AMDGPU::SReg_256RegClass.contains(SrcReg));
146 Opcode = AMDGPU::V_MOV_B32_e32;
149 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
150 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
151 AMDGPU::SReg_512RegClass.contains(SrcReg));
152 Opcode = AMDGPU::V_MOV_B32_e32;
153 SubIndices = Sub0_15;
156 llvm_unreachable("Can't copy register!");
159 while (unsigned SubIdx = *SubIndices++) {
160 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
161 get(Opcode), RI.getSubReg(DestReg, SubIdx));
163 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
166 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
170 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
173 // Try to map original to commuted opcode
174 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
177 // Try to map commuted to original opcode
178 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
184 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator MI,
186 unsigned SrcReg, bool isKill,
188 const TargetRegisterClass *RC,
189 const TargetRegisterInfo *TRI) const {
190 SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
191 DebugLoc DL = MBB.findDebugLoc(MI);
192 unsigned KillFlag = isKill ? RegState::Kill : 0;
193 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
195 if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
196 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MBB.getParent());
198 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), MFI->SpillTracker.LaneVGPR)
199 .addReg(SrcReg, KillFlag)
201 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR, Lane);
202 } else if (RI.isSGPRClass(RC)) {
203 // We are only allowed to create one new instruction when spilling
204 // registers, so we need to use pseudo instruction for vector
207 // Reserve a spot in the spill tracker for each sub-register of
208 // the vector register.
209 unsigned NumSubRegs = RC->getSize() / 4;
210 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MBB.getParent(),
212 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
216 switch (RC->getSize() * 8) {
217 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
218 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
219 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
220 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
221 default: llvm_unreachable("Cannot spill register class");
224 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
228 llvm_unreachable("VGPR spilling not supported");
232 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
233 MachineBasicBlock::iterator MI,
234 unsigned DestReg, int FrameIndex,
235 const TargetRegisterClass *RC,
236 const TargetRegisterInfo *TRI) const {
237 SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
238 DebugLoc DL = MBB.findDebugLoc(MI);
239 if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) {
240 SIMachineFunctionInfo::SpilledReg Spill =
241 MFI->SpillTracker.getSpilledReg(FrameIndex);
243 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), DestReg)
247 } else if (RI.isSGPRClass(RC)){
249 switch(RC->getSize() * 8) {
250 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
251 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
252 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
253 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
254 default: llvm_unreachable("Cannot spill register class");
257 SIMachineFunctionInfo::SpilledReg Spill =
258 MFI->SpillTracker.getSpilledReg(FrameIndex);
260 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
265 llvm_unreachable("VGPR spilling not supported");
269 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
272 case AMDGPU::SI_SPILL_S512_SAVE:
273 case AMDGPU::SI_SPILL_S512_RESTORE:
275 case AMDGPU::SI_SPILL_S256_SAVE:
276 case AMDGPU::SI_SPILL_S256_RESTORE:
278 case AMDGPU::SI_SPILL_S128_SAVE:
279 case AMDGPU::SI_SPILL_S128_RESTORE:
281 case AMDGPU::SI_SPILL_S64_SAVE:
282 case AMDGPU::SI_SPILL_S64_RESTORE:
284 default: llvm_unreachable("Invalid spill opcode");
288 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
297 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
302 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
303 SIMachineFunctionInfo *MFI =
304 MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
305 MachineBasicBlock &MBB = *MI->getParent();
306 DebugLoc DL = MBB.findDebugLoc(MI);
307 switch (MI->getOpcode()) {
308 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
310 // SGPR register spill
311 case AMDGPU::SI_SPILL_S512_SAVE:
312 case AMDGPU::SI_SPILL_S256_SAVE:
313 case AMDGPU::SI_SPILL_S128_SAVE:
314 case AMDGPU::SI_SPILL_S64_SAVE: {
315 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
316 unsigned FrameIndex = MI->getOperand(2).getImm();
318 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
319 SIMachineFunctionInfo::SpilledReg Spill;
320 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
321 &AMDGPU::SGPR_32RegClass, i);
322 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
324 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
325 MI->getOperand(0).getReg())
327 .addImm(Spill.Lane + i);
329 MI->eraseFromParent();
333 // SGPR register restore
334 case AMDGPU::SI_SPILL_S512_RESTORE:
335 case AMDGPU::SI_SPILL_S256_RESTORE:
336 case AMDGPU::SI_SPILL_S128_RESTORE:
337 case AMDGPU::SI_SPILL_S64_RESTORE: {
338 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
340 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
341 SIMachineFunctionInfo::SpilledReg Spill;
342 unsigned FrameIndex = MI->getOperand(2).getImm();
343 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
344 &AMDGPU::SGPR_32RegClass, i);
345 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
347 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
348 .addReg(MI->getOperand(1).getReg())
349 .addImm(Spill.Lane + i);
351 MI->eraseFromParent();
358 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
361 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
362 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
365 // Cannot commute VOP2 if src0 is SGPR.
366 if (isVOP2(MI->getOpcode()) && MI->getOperand(1).isReg() &&
367 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
370 if (!MI->getOperand(2).isReg()) {
371 // XXX: Commute instructions with FPImm operands
372 if (NewMI || MI->getOperand(2).isFPImm() ||
373 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
377 // XXX: Commute VOP3 instructions with abs and neg set.
378 if (isVOP3(MI->getOpcode()) &&
379 (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
380 AMDGPU::OpName::abs)).getImm() ||
381 MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
382 AMDGPU::OpName::neg)).getImm()))
385 unsigned Reg = MI->getOperand(1).getReg();
386 unsigned SubReg = MI->getOperand(1).getSubReg();
387 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
388 MI->getOperand(2).ChangeToRegister(Reg, false);
389 MI->getOperand(2).setSubReg(SubReg);
391 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
395 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
400 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
401 MachineBasicBlock::iterator I,
403 unsigned SrcReg) const {
404 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
405 DstReg) .addReg(SrcReg);
408 bool SIInstrInfo::isMov(unsigned Opcode) const {
410 default: return false;
411 case AMDGPU::S_MOV_B32:
412 case AMDGPU::S_MOV_B64:
413 case AMDGPU::V_MOV_B32_e32:
414 case AMDGPU::V_MOV_B32_e64:
420 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
421 return RC != &AMDGPU::EXECRegRegClass;
425 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
426 AliasAnalysis *AA) const {
427 switch(MI->getOpcode()) {
428 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
429 case AMDGPU::S_MOV_B32:
430 case AMDGPU::S_MOV_B64:
431 case AMDGPU::V_MOV_B32_e32:
432 return MI->getOperand(1).isImm();
438 // Helper function generated by tablegen. We are wrapping this with
439 // an SIInstrInfo function that reutrns bool rather than int.
440 int isDS(uint16_t Opcode);
444 bool SIInstrInfo::isDS(uint16_t Opcode) const {
445 return ::AMDGPU::isDS(Opcode) != -1;
448 int SIInstrInfo::isMIMG(uint16_t Opcode) const {
449 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
452 int SIInstrInfo::isSMRD(uint16_t Opcode) const {
453 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
456 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
457 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
460 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
461 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
464 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
465 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
468 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
469 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
472 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
473 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
476 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
477 int32_t Val = Imm.getSExtValue();
478 if (Val >= -16 && Val <= 64)
481 // The actual type of the operand does not seem to matter as long
482 // as the bits match one of the inline immediate values. For example:
484 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
485 // so it is a legal inline immediate.
487 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
488 // floating-point, so it is a legal inline immediate.
490 return (APInt::floatToBits(0.0f) == Imm) ||
491 (APInt::floatToBits(1.0f) == Imm) ||
492 (APInt::floatToBits(-1.0f) == Imm) ||
493 (APInt::floatToBits(0.5f) == Imm) ||
494 (APInt::floatToBits(-0.5f) == Imm) ||
495 (APInt::floatToBits(2.0f) == Imm) ||
496 (APInt::floatToBits(-2.0f) == Imm) ||
497 (APInt::floatToBits(4.0f) == Imm) ||
498 (APInt::floatToBits(-4.0f) == Imm);
501 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
503 return isInlineConstant(APInt(32, MO.getImm(), true));
506 APFloat FpImm = MO.getFPImm()->getValueAPF();
507 return isInlineConstant(FpImm.bitcastToAPInt());
513 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
514 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
517 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
518 StringRef &ErrInfo) const {
519 uint16_t Opcode = MI->getOpcode();
520 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
521 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
522 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
524 // Make sure the number of operands is correct.
525 const MCInstrDesc &Desc = get(Opcode);
526 if (!Desc.isVariadic() &&
527 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
528 ErrInfo = "Instruction has wrong number of operands.";
532 // Make sure the register classes are correct
533 for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
534 switch (Desc.OpInfo[i].OperandType) {
535 case MCOI::OPERAND_REGISTER:
537 case MCOI::OPERAND_IMMEDIATE:
538 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) {
539 ErrInfo = "Expected immediate, but got non-immediate";
547 if (!MI->getOperand(i).isReg())
550 int RegClass = Desc.OpInfo[i].RegClass;
551 if (RegClass != -1) {
552 unsigned Reg = MI->getOperand(i).getReg();
553 if (TargetRegisterInfo::isVirtualRegister(Reg))
556 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
557 if (!RC->contains(Reg)) {
558 ErrInfo = "Operand has incorrect register class.";
566 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
567 unsigned ConstantBusCount = 0;
568 unsigned SGPRUsed = AMDGPU::NoRegister;
569 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
570 const MachineOperand &MO = MI->getOperand(i);
571 if (MO.isReg() && MO.isUse() &&
572 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
574 // EXEC register uses the constant bus.
575 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
578 // SGPRs use the constant bus
579 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
581 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
582 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
583 if (SGPRUsed != MO.getReg()) {
585 SGPRUsed = MO.getReg();
589 // Literal constants use the constant bus.
590 if (isLiteralConstant(MO))
593 if (ConstantBusCount > 1) {
594 ErrInfo = "VOP* instruction uses the constant bus more than once";
599 // Verify SRC1 for VOP2 and VOPC
600 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
601 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
602 if (Src1.isImm() || Src1.isFPImm()) {
603 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
609 if (isVOP3(Opcode)) {
610 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
611 ErrInfo = "VOP3 src0 cannot be a literal constant.";
614 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
615 ErrInfo = "VOP3 src1 cannot be a literal constant.";
618 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
619 ErrInfo = "VOP3 src2 cannot be a literal constant.";
626 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
627 switch (MI.getOpcode()) {
628 default: return AMDGPU::INSTRUCTION_LIST_END;
629 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
630 case AMDGPU::COPY: return AMDGPU::COPY;
631 case AMDGPU::PHI: return AMDGPU::PHI;
632 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
633 case AMDGPU::S_MOV_B32:
634 return MI.getOperand(1).isReg() ?
635 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
636 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
637 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
638 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
639 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
640 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
641 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
642 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
643 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
644 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
645 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
646 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
647 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
648 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
649 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
650 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
651 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
652 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
653 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
654 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
655 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
656 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
657 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
658 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
659 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
660 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
661 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
662 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
663 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
664 case AMDGPU::S_LOAD_DWORD_IMM:
665 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
666 case AMDGPU::S_LOAD_DWORDX2_IMM:
667 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
668 case AMDGPU::S_LOAD_DWORDX4_IMM:
669 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
673 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
674 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
677 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
678 unsigned OpNo) const {
679 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
680 const MCInstrDesc &Desc = get(MI.getOpcode());
681 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
682 Desc.OpInfo[OpNo].RegClass == -1)
683 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
685 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
686 return RI.getRegClass(RCID);
689 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
690 switch (MI.getOpcode()) {
692 case AMDGPU::REG_SEQUENCE:
694 return RI.hasVGPRs(getOpRegClass(MI, 0));
696 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
700 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
701 MachineBasicBlock::iterator I = MI;
702 MachineOperand &MO = MI->getOperand(OpIdx);
703 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
704 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
705 const TargetRegisterClass *RC = RI.getRegClass(RCID);
706 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
708 Opcode = AMDGPU::COPY;
709 } else if (RI.isSGPRClass(RC)) {
710 Opcode = AMDGPU::S_MOV_B32;
713 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
714 unsigned Reg = MRI.createVirtualRegister(VRC);
715 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
717 MO.ChangeToRegister(Reg, false);
720 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
721 MachineRegisterInfo &MRI,
722 MachineOperand &SuperReg,
723 const TargetRegisterClass *SuperRC,
725 const TargetRegisterClass *SubRC)
727 assert(SuperReg.isReg());
729 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
730 unsigned SubReg = MRI.createVirtualRegister(SubRC);
732 // Just in case the super register is itself a sub-register, copy it to a new
733 // value so we don't need to wory about merging its subreg index with the
734 // SubIdx passed to this function. The register coalescer should be able to
735 // eliminate this extra copy.
736 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
738 .addOperand(SuperReg);
740 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
742 .addReg(NewSuperReg, 0, SubIdx);
746 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
747 MachineBasicBlock::iterator MII,
748 MachineRegisterInfo &MRI,
750 const TargetRegisterClass *SuperRC,
752 const TargetRegisterClass *SubRC) const {
754 // XXX - Is there a better way to do this?
755 if (SubIdx == AMDGPU::sub0)
756 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
757 if (SubIdx == AMDGPU::sub1)
758 return MachineOperand::CreateImm(Op.getImm() >> 32);
760 llvm_unreachable("Unhandled register index for immediate");
763 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
765 return MachineOperand::CreateReg(SubReg, false);
768 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
769 MachineBasicBlock::iterator MI,
770 MachineRegisterInfo &MRI,
771 const TargetRegisterClass *RC,
772 const MachineOperand &Op) const {
773 MachineBasicBlock *MBB = MI->getParent();
774 DebugLoc DL = MI->getDebugLoc();
775 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
776 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
777 unsigned Dst = MRI.createVirtualRegister(RC);
779 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
781 .addImm(Op.getImm() & 0xFFFFFFFF);
782 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
784 .addImm(Op.getImm() >> 32);
786 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
788 .addImm(AMDGPU::sub0)
790 .addImm(AMDGPU::sub1);
792 Worklist.push_back(Lo);
793 Worklist.push_back(Hi);
798 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
799 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
800 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
801 AMDGPU::OpName::src0);
802 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
803 AMDGPU::OpName::src1);
804 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
805 AMDGPU::OpName::src2);
808 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
809 MachineOperand &Src0 = MI->getOperand(Src0Idx);
810 MachineOperand &Src1 = MI->getOperand(Src1Idx);
812 // If the instruction implicitly reads VCC, we can't have any SGPR operands,
814 bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI);
815 if (ReadsVCC && Src0.isReg() &&
816 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {
817 legalizeOpWithMove(MI, Src0Idx);
821 if (ReadsVCC && Src1.isReg() &&
822 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
823 legalizeOpWithMove(MI, Src1Idx);
827 // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
828 // be the first operand, and there can only be one.
829 if (Src1.isImm() || Src1.isFPImm() ||
830 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
831 if (MI->isCommutable()) {
832 if (commuteInstruction(MI))
835 legalizeOpWithMove(MI, Src1Idx);
839 // XXX - Do any VOP3 instructions read VCC?
841 if (isVOP3(MI->getOpcode())) {
842 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
843 unsigned SGPRReg = AMDGPU::NoRegister;
844 for (unsigned i = 0; i < 3; ++i) {
845 int Idx = VOP3Idx[i];
848 MachineOperand &MO = MI->getOperand(Idx);
851 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
852 continue; // VGPRs are legal
854 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
856 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
857 SGPRReg = MO.getReg();
858 // We can use one SGPR in each VOP3 instruction.
861 } else if (!isLiteralConstant(MO)) {
862 // If it is not a register and not a literal constant, then it must be
863 // an inline constant which is always legal.
866 // If we make it this far, then the operand is not legal and we must
868 legalizeOpWithMove(MI, Idx);
872 // Legalize REG_SEQUENCE and PHI
873 // The register class of the operands much be the same type as the register
874 // class of the output.
875 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
876 MI->getOpcode() == AMDGPU::PHI) {
877 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
878 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
879 if (!MI->getOperand(i).isReg() ||
880 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
882 const TargetRegisterClass *OpRC =
883 MRI.getRegClass(MI->getOperand(i).getReg());
884 if (RI.hasVGPRs(OpRC)) {
891 // If any of the operands are VGPR registers, then they all most be
892 // otherwise we will create illegal VGPR->SGPR copies when legalizing
894 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
897 VRC = RI.getEquivalentVGPRClass(SRC);
904 // Update all the operands so they have the same type.
905 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
906 if (!MI->getOperand(i).isReg() ||
907 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
909 unsigned DstReg = MRI.createVirtualRegister(RC);
910 MachineBasicBlock *InsertBB;
911 MachineBasicBlock::iterator Insert;
912 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
913 InsertBB = MI->getParent();
916 // MI is a PHI instruction.
917 InsertBB = MI->getOperand(i + 1).getMBB();
918 Insert = InsertBB->getFirstTerminator();
920 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
921 get(AMDGPU::COPY), DstReg)
922 .addOperand(MI->getOperand(i));
923 MI->getOperand(i).setReg(DstReg);
927 // Legalize MUBUF* instructions
928 // FIXME: If we start using the non-addr64 instructions for compute, we
929 // may need to legalize them here.
931 int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
932 AMDGPU::OpName::srsrc);
933 int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
934 AMDGPU::OpName::vaddr);
935 if (SRsrcIdx != -1 && VAddrIdx != -1) {
936 const TargetRegisterClass *VAddrRC =
937 RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
939 if(VAddrRC->getSize() == 8 &&
940 MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
941 // We have a MUBUF instruction that uses a 64-bit vaddr register and
942 // srsrc has the incorrect register class. In order to fix this, we
943 // need to extract the pointer from the resource descriptor (srsrc),
944 // add it to the value of vadd, then store the result in the vaddr
945 // operand. Then, we need to set the pointer field of the resource
946 // descriptor to zero.
948 MachineBasicBlock &MBB = *MI->getParent();
949 MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
950 MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
951 unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
952 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
953 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
954 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
955 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
956 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
957 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
958 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
960 // SRsrcPtrLo = srsrc:sub0
961 SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
962 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
964 // SRsrcPtrHi = srsrc:sub1
965 SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
966 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
968 // VAddrLo = vaddr:sub0
969 VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
970 &AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
972 // VAddrHi = vaddr:sub1
973 VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
974 &AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
976 // NewVaddrLo = SRsrcPtrLo + VAddrLo
977 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
981 .addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
983 // NewVaddrHi = SRsrcPtrHi + VAddrHi
984 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
988 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
989 .addReg(AMDGPU::VCC, RegState::Implicit);
991 // NewVaddr = {NewVaddrHi, NewVaddrLo}
992 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
995 .addImm(AMDGPU::sub0)
997 .addImm(AMDGPU::sub1);
1000 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1004 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1005 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1007 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1009 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1010 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1012 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1014 // NewSRsrc = {Zero64, SRsrcFormat}
1015 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1018 .addImm(AMDGPU::sub0_sub1)
1019 .addReg(SRsrcFormatLo)
1020 .addImm(AMDGPU::sub2)
1021 .addReg(SRsrcFormatHi)
1022 .addImm(AMDGPU::sub3);
1024 // Update the instruction to use NewVaddr
1025 MI->getOperand(VAddrIdx).setReg(NewVAddr);
1026 // Update the instruction to use NewSRsrc
1027 MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
1032 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1033 MachineBasicBlock *MBB = MI->getParent();
1034 switch (MI->getOpcode()) {
1035 case AMDGPU::S_LOAD_DWORD_IMM:
1036 case AMDGPU::S_LOAD_DWORD_SGPR:
1037 case AMDGPU::S_LOAD_DWORDX2_IMM:
1038 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1039 case AMDGPU::S_LOAD_DWORDX4_IMM:
1040 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1041 unsigned NewOpcode = getVALUOp(*MI);
1045 if (MI->getOperand(2).isReg()) {
1046 RegOffset = MI->getOperand(2).getReg();
1049 assert(MI->getOperand(2).isImm());
1050 // SMRD instructions take a dword offsets and MUBUF instructions
1051 // take a byte offset.
1052 ImmOffset = MI->getOperand(2).getImm() << 2;
1053 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1054 if (isUInt<12>(ImmOffset)) {
1055 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1059 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1066 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1067 unsigned DWord0 = RegOffset;
1068 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1069 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1070 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1072 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1074 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1075 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1076 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1077 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1078 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1080 .addImm(AMDGPU::sub0)
1082 .addImm(AMDGPU::sub1)
1084 .addImm(AMDGPU::sub2)
1086 .addImm(AMDGPU::sub3);
1087 MI->setDesc(get(NewOpcode));
1088 if (MI->getOperand(2).isReg()) {
1089 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1091 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1093 MI->getOperand(1).setReg(SRsrc);
1094 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1098 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1099 SmallVector<MachineInstr *, 128> Worklist;
1100 Worklist.push_back(&TopInst);
1102 while (!Worklist.empty()) {
1103 MachineInstr *Inst = Worklist.pop_back_val();
1104 MachineBasicBlock *MBB = Inst->getParent();
1105 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1107 unsigned Opcode = Inst->getOpcode();
1108 unsigned NewOpcode = getVALUOp(*Inst);
1110 // Handle some special cases
1113 if (isSMRD(Inst->getOpcode())) {
1114 moveSMRDToVALU(Inst, MRI);
1117 case AMDGPU::S_MOV_B64: {
1118 DebugLoc DL = Inst->getDebugLoc();
1120 // If the source operand is a register we can replace this with a
1122 if (Inst->getOperand(1).isReg()) {
1123 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1124 .addOperand(Inst->getOperand(0))
1125 .addOperand(Inst->getOperand(1));
1126 Worklist.push_back(Copy);
1128 // Otherwise, we need to split this into two movs, because there is
1129 // no 64-bit VALU move instruction.
1130 unsigned Reg = Inst->getOperand(0).getReg();
1131 unsigned Dst = split64BitImm(Worklist,
1134 MRI.getRegClass(Reg),
1135 Inst->getOperand(1));
1136 MRI.replaceRegWith(Reg, Dst);
1138 Inst->eraseFromParent();
1141 case AMDGPU::S_AND_B64:
1142 splitScalar64BitOp(Worklist, Inst, AMDGPU::S_AND_B32);
1143 Inst->eraseFromParent();
1146 case AMDGPU::S_OR_B64:
1147 splitScalar64BitOp(Worklist, Inst, AMDGPU::S_OR_B32);
1148 Inst->eraseFromParent();
1151 case AMDGPU::S_XOR_B64:
1152 splitScalar64BitOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1153 Inst->eraseFromParent();
1156 case AMDGPU::S_NOT_B64:
1157 splitScalar64BitOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1158 Inst->eraseFromParent();
1161 case AMDGPU::S_BFE_U64:
1162 case AMDGPU::S_BFE_I64:
1163 case AMDGPU::S_BFM_B64:
1164 llvm_unreachable("Moving this op to VALU not implemented");
1167 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1168 // We cannot move this instruction to the VALU, so we should try to
1169 // legalize its operands instead.
1170 legalizeOperands(Inst);
1174 // Use the new VALU Opcode.
1175 const MCInstrDesc &NewDesc = get(NewOpcode);
1176 Inst->setDesc(NewDesc);
1178 // Remove any references to SCC. Vector instructions can't read from it, and
1179 // We're just about to add the implicit use / defs of VCC, and we don't want
1181 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1182 MachineOperand &Op = Inst->getOperand(i);
1183 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1184 Inst->RemoveOperand(i);
1187 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1188 // We are converting these to a BFE, so we need to add the missing
1189 // operands for the size and offset.
1190 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1191 Inst->addOperand(Inst->getOperand(1));
1192 Inst->getOperand(1).ChangeToImmediate(0);
1193 Inst->addOperand(MachineOperand::CreateImm(0));
1194 Inst->addOperand(MachineOperand::CreateImm(0));
1195 Inst->addOperand(MachineOperand::CreateImm(0));
1196 Inst->addOperand(MachineOperand::CreateImm(Size));
1198 // XXX - Other pointless operands. There are 4, but it seems you only need
1199 // 3 to not hit an assertion later in MCInstLower.
1200 Inst->addOperand(MachineOperand::CreateImm(0));
1201 Inst->addOperand(MachineOperand::CreateImm(0));
1204 addDescImplicitUseDef(NewDesc, Inst);
1206 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1207 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1208 // If we need to move this to VGPRs, we need to unpack the second operand
1209 // back into the 2 separate ones for bit offset and width.
1210 assert(OffsetWidthOp.isImm() &&
1211 "Scalar BFE is only implemented for constant width and offset");
1212 uint32_t Imm = OffsetWidthOp.getImm();
1214 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1215 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1217 Inst->RemoveOperand(2); // Remove old immediate.
1218 Inst->addOperand(Inst->getOperand(1));
1219 Inst->getOperand(1).ChangeToImmediate(0);
1220 Inst->addOperand(MachineOperand::CreateImm(Offset));
1221 Inst->addOperand(MachineOperand::CreateImm(0));
1222 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1223 Inst->addOperand(MachineOperand::CreateImm(0));
1224 Inst->addOperand(MachineOperand::CreateImm(0));
1225 Inst->addOperand(MachineOperand::CreateImm(0));
1228 // Update the destination register class.
1230 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1233 // For target instructions, getOpRegClass just returns the virtual
1234 // register class associated with the operand, so we need to find an
1235 // equivalent VGPR register class in order to move the instruction to the
1239 case AMDGPU::REG_SEQUENCE:
1240 case AMDGPU::INSERT_SUBREG:
1241 if (RI.hasVGPRs(NewDstRC))
1243 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1251 unsigned DstReg = Inst->getOperand(0).getReg();
1252 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1253 MRI.replaceRegWith(DstReg, NewDstReg);
1255 // Legalize the operands
1256 legalizeOperands(Inst);
1258 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1259 E = MRI.use_end(); I != E; ++I) {
1260 MachineInstr &UseMI = *I->getParent();
1261 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1262 Worklist.push_back(&UseMI);
1268 //===----------------------------------------------------------------------===//
1269 // Indirect addressing callbacks
1270 //===----------------------------------------------------------------------===//
1272 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1273 unsigned Channel) const {
1274 assert(Channel == 0);
1278 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1279 return &AMDGPU::VReg_32RegClass;
1282 void SIInstrInfo::splitScalar64BitOp(SmallVectorImpl<MachineInstr *> &Worklist,
1284 unsigned Opcode) const {
1285 MachineBasicBlock &MBB = *Inst->getParent();
1286 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1288 MachineOperand &Dest = Inst->getOperand(0);
1289 MachineOperand &Src0 = Inst->getOperand(1);
1290 MachineOperand &Src1 = Inst->getOperand(2);
1291 DebugLoc DL = Inst->getDebugLoc();
1293 MachineBasicBlock::iterator MII = Inst;
1295 const MCInstrDesc &InstDesc = get(Opcode);
1296 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1297 MRI.getRegClass(Src0.getReg()) :
1298 &AMDGPU::SGPR_32RegClass;
1300 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1301 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1302 MRI.getRegClass(Src1.getReg()) :
1303 &AMDGPU::SGPR_32RegClass;
1305 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1307 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1308 AMDGPU::sub0, Src0SubRC);
1309 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1310 AMDGPU::sub0, Src1SubRC);
1312 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1313 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1315 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1316 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1317 .addOperand(SrcReg0Sub0)
1318 .addOperand(SrcReg1Sub0);
1320 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1321 AMDGPU::sub1, Src0SubRC);
1322 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1323 AMDGPU::sub1, Src1SubRC);
1325 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1326 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1327 .addOperand(SrcReg0Sub1)
1328 .addOperand(SrcReg1Sub1);
1330 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1331 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1333 .addImm(AMDGPU::sub0)
1335 .addImm(AMDGPU::sub1);
1337 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1339 // Try to legalize the operands in case we need to swap the order to keep it
1341 Worklist.push_back(LoHalf);
1342 Worklist.push_back(HiHalf);
1345 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1346 MachineInstr *Inst) const {
1347 // Add the implict and explicit register definitions.
1348 if (NewDesc.ImplicitUses) {
1349 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
1350 unsigned Reg = NewDesc.ImplicitUses[i];
1351 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
1355 if (NewDesc.ImplicitDefs) {
1356 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1357 unsigned Reg = NewDesc.ImplicitDefs[i];
1358 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
1363 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1364 MachineBasicBlock *MBB,
1365 MachineBasicBlock::iterator I,
1367 unsigned Address, unsigned OffsetReg) const {
1368 const DebugLoc &DL = MBB->findDebugLoc(I);
1369 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1370 getIndirectIndexBegin(*MBB->getParent()));
1372 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1373 .addReg(IndirectBaseReg, RegState::Define)
1374 .addOperand(I->getOperand(0))
1375 .addReg(IndirectBaseReg)
1381 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1382 MachineBasicBlock *MBB,
1383 MachineBasicBlock::iterator I,
1385 unsigned Address, unsigned OffsetReg) const {
1386 const DebugLoc &DL = MBB->findDebugLoc(I);
1387 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1388 getIndirectIndexBegin(*MBB->getParent()));
1390 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1391 .addOperand(I->getOperand(0))
1392 .addOperand(I->getOperand(1))
1393 .addReg(IndirectBaseReg)
1399 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1400 const MachineFunction &MF) const {
1401 int End = getIndirectIndexEnd(MF);
1402 int Begin = getIndirectIndexBegin(MF);
1408 for (int Index = Begin; Index <= End; ++Index)
1409 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1411 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1412 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1414 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1415 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1417 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1418 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1420 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1421 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1423 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1424 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));