1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
29 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
30 : AMDGPUInstrInfo(st),
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
79 int64_t &Offset1) const {
80 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
83 unsigned Opc0 = Load0->getMachineOpcode();
84 unsigned Opc1 = Load1->getMachineOpcode();
86 // Make sure both are actually loads.
87 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
90 if (isDS(Opc0) && isDS(Opc1)) {
92 // FIXME: Handle this case:
93 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
97 if (Load0->getOperand(1) != Load1->getOperand(1))
101 if (findChainOperand(Load0) != findChainOperand(Load1))
104 // Skip read2 / write2 variants for simplicity.
105 // TODO: We should report true if the used offsets are adjacent (excluded
107 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
108 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
111 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
112 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
116 if (isSMRD(Opc0) && isSMRD(Opc1)) {
117 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
120 if (Load0->getOperand(0) != Load1->getOperand(0))
124 if (findChainOperand(Load0) != findChainOperand(Load1))
127 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
128 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
132 // MUBUF and MTBUF can access the same addresses.
133 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
135 // MUBUF and MTBUF have vaddr at different indices.
136 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
137 findChainOperand(Load0) != findChainOperand(Load1) ||
138 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
139 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
142 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
143 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
145 if (OffIdx0 == -1 || OffIdx1 == -1)
148 // getNamedOperandIdx returns the index for MachineInstrs. Since they
149 // inlcude the output in the operand list, but SDNodes don't, we need to
150 // subtract the index by one.
154 SDValue Off0 = Load0->getOperand(OffIdx0);
155 SDValue Off1 = Load1->getOperand(OffIdx1);
157 // The offset might be a FrameIndexSDNode.
158 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
161 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
162 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
169 static bool isStride64(unsigned Opc) {
171 case AMDGPU::DS_READ2ST64_B32:
172 case AMDGPU::DS_READ2ST64_B64:
173 case AMDGPU::DS_WRITE2ST64_B32:
174 case AMDGPU::DS_WRITE2ST64_B64:
181 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
182 unsigned &BaseReg, unsigned &Offset,
183 const TargetRegisterInfo *TRI) const {
184 unsigned Opc = LdSt->getOpcode();
186 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
187 AMDGPU::OpName::offset);
189 // Normal, single offset LDS instruction.
190 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
191 AMDGPU::OpName::addr);
193 BaseReg = AddrReg->getReg();
194 Offset = OffsetImm->getImm();
198 // The 2 offset instructions use offset0 and offset1 instead. We can treat
199 // these as a load with a single offset if the 2 offsets are consecutive. We
200 // will use this for some partially aligned loads.
201 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
202 AMDGPU::OpName::offset0);
203 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
204 AMDGPU::OpName::offset1);
206 uint8_t Offset0 = Offset0Imm->getImm();
207 uint8_t Offset1 = Offset1Imm->getImm();
208 assert(Offset1 > Offset0);
210 if (Offset1 - Offset0 == 1) {
211 // Each of these offsets is in element sized units, so we need to convert
212 // to bytes of the individual reads.
216 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
218 assert(LdSt->mayStore());
219 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
220 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
226 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
227 AMDGPU::OpName::addr);
228 BaseReg = AddrReg->getReg();
229 Offset = EltSize * Offset0;
236 if (isMUBUF(Opc) || isMTBUF(Opc)) {
237 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
240 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
241 AMDGPU::OpName::vaddr);
245 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
246 AMDGPU::OpName::offset);
247 BaseReg = AddrReg->getReg();
248 Offset = OffsetImm->getImm();
253 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
254 AMDGPU::OpName::offset);
258 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
259 AMDGPU::OpName::sbase);
260 BaseReg = SBaseReg->getReg();
261 Offset = OffsetImm->getImm();
268 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
269 MachineInstr *SecondLdSt,
270 unsigned NumLoads) const {
271 unsigned Opc0 = FirstLdSt->getOpcode();
272 unsigned Opc1 = SecondLdSt->getOpcode();
274 // TODO: This needs finer tuning
278 if (isDS(Opc0) && isDS(Opc1))
281 if (isSMRD(Opc0) && isSMRD(Opc1))
284 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
291 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator MI, DebugLoc DL,
293 unsigned DestReg, unsigned SrcReg,
294 bool KillSrc) const {
296 // If we are trying to copy to or from SCC, there is a bug somewhere else in
297 // the backend. While it may be theoretically possible to do this, it should
298 // never be necessary.
299 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
301 static const int16_t Sub0_15[] = {
302 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
303 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
304 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
305 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
308 static const int16_t Sub0_7[] = {
309 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
310 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
313 static const int16_t Sub0_3[] = {
314 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
317 static const int16_t Sub0_2[] = {
318 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
321 static const int16_t Sub0_1[] = {
322 AMDGPU::sub0, AMDGPU::sub1, 0
326 const int16_t *SubIndices;
328 if (AMDGPU::M0 == DestReg) {
329 // Check if M0 isn't already set to this value
330 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
331 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
333 if (!I->definesRegister(AMDGPU::M0))
336 unsigned Opc = I->getOpcode();
337 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
340 if (!I->readsRegister(SrcReg))
343 // The copy isn't necessary
348 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
349 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
350 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
351 .addReg(SrcReg, getKillRegState(KillSrc));
354 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
355 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
356 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
357 .addReg(SrcReg, getKillRegState(KillSrc));
360 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
361 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
362 Opcode = AMDGPU::S_MOV_B32;
365 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
366 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
367 Opcode = AMDGPU::S_MOV_B32;
370 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
371 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
372 Opcode = AMDGPU::S_MOV_B32;
373 SubIndices = Sub0_15;
375 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
376 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
377 AMDGPU::SReg_32RegClass.contains(SrcReg));
378 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
379 .addReg(SrcReg, getKillRegState(KillSrc));
382 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
383 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
384 AMDGPU::SReg_64RegClass.contains(SrcReg));
385 Opcode = AMDGPU::V_MOV_B32_e32;
388 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
389 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
390 Opcode = AMDGPU::V_MOV_B32_e32;
393 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
394 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
395 AMDGPU::SReg_128RegClass.contains(SrcReg));
396 Opcode = AMDGPU::V_MOV_B32_e32;
399 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
400 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
401 AMDGPU::SReg_256RegClass.contains(SrcReg));
402 Opcode = AMDGPU::V_MOV_B32_e32;
405 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
406 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
407 AMDGPU::SReg_512RegClass.contains(SrcReg));
408 Opcode = AMDGPU::V_MOV_B32_e32;
409 SubIndices = Sub0_15;
412 llvm_unreachable("Can't copy register!");
415 while (unsigned SubIdx = *SubIndices++) {
416 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
417 get(Opcode), RI.getSubReg(DestReg, SubIdx));
419 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
422 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
426 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
429 // Try to map original to commuted opcode
430 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
433 // Try to map commuted to original opcode
434 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
440 static bool shouldTryToSpillVGPRs(MachineFunction *MF) {
442 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
443 const TargetMachine &TM = MF->getTarget();
445 // FIXME: Even though it can cause problems, we need to enable
446 // spilling at -O0, since the fast register allocator always
447 // spills registers that are live at the end of blocks.
448 return MFI->getShaderType() == ShaderType::COMPUTE &&
449 TM.getOptLevel() == CodeGenOpt::None;
453 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
454 MachineBasicBlock::iterator MI,
455 unsigned SrcReg, bool isKill,
457 const TargetRegisterClass *RC,
458 const TargetRegisterInfo *TRI) const {
459 MachineFunction *MF = MBB.getParent();
460 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
461 DebugLoc DL = MBB.findDebugLoc(MI);
464 if (RI.isSGPRClass(RC)) {
465 // We are only allowed to create one new instruction when spilling
466 // registers, so we need to use pseudo instruction for spilling
468 switch (RC->getSize() * 8) {
469 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
470 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
471 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
472 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
473 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
475 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
476 switch(RC->getSize() * 8) {
477 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
478 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
479 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
480 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
481 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
482 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
487 FrameInfo->setObjectAlignment(FrameIndex, 4);
488 BuildMI(MBB, MI, DL, get(Opcode))
490 .addFrameIndex(FrameIndex);
492 LLVMContext &Ctx = MF->getFunction()->getContext();
493 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
495 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
500 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
501 MachineBasicBlock::iterator MI,
502 unsigned DestReg, int FrameIndex,
503 const TargetRegisterClass *RC,
504 const TargetRegisterInfo *TRI) const {
505 MachineFunction *MF = MBB.getParent();
506 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
507 DebugLoc DL = MBB.findDebugLoc(MI);
510 if (RI.isSGPRClass(RC)){
511 switch(RC->getSize() * 8) {
512 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
513 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
514 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
515 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
516 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
518 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
519 switch(RC->getSize() * 8) {
520 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
521 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
522 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
523 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
524 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
525 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
530 FrameInfo->setObjectAlignment(FrameIndex, 4);
531 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
532 .addFrameIndex(FrameIndex);
534 LLVMContext &Ctx = MF->getFunction()->getContext();
535 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
536 " restore register");
537 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
538 .addReg(AMDGPU::VGPR0);
542 /// \param @Offset Offset in bytes of the FrameIndex being spilled
543 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
544 MachineBasicBlock::iterator MI,
545 RegScavenger *RS, unsigned TmpReg,
546 unsigned FrameOffset,
547 unsigned Size) const {
548 MachineFunction *MF = MBB.getParent();
549 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
550 const AMDGPUSubtarget &ST = MF->getTarget().getSubtarget<AMDGPUSubtarget>();
551 const SIRegisterInfo *TRI =
552 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
553 DebugLoc DL = MBB.findDebugLoc(MI);
554 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
555 unsigned WavefrontSize = ST.getWavefrontSize();
557 unsigned TIDReg = MFI->getTIDReg();
558 if (!MFI->hasCalculatedTID()) {
559 MachineBasicBlock &Entry = MBB.getParent()->front();
560 MachineBasicBlock::iterator Insert = Entry.front();
561 DebugLoc DL = Insert->getDebugLoc();
563 TIDReg = RI.findUnusedVGPR(MF->getRegInfo());
564 if (TIDReg == AMDGPU::NoRegister)
568 if (MFI->getShaderType() == ShaderType::COMPUTE &&
569 WorkGroupSize > WavefrontSize) {
571 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
572 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
573 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
574 unsigned InputPtrReg =
575 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
576 static const unsigned TIDIGRegs[3] = {
577 TIDIGXReg, TIDIGYReg, TIDIGZReg
579 for (unsigned Reg : TIDIGRegs) {
580 if (!Entry.isLiveIn(Reg))
581 Entry.addLiveIn(Reg);
584 RS->enterBasicBlock(&Entry);
585 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
586 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
587 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
589 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
590 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
592 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
594 // NGROUPS.X * NGROUPS.Y
595 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
598 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
599 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
602 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
603 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
607 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
608 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
613 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
618 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e32),
624 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
628 MFI->setTIDReg(TIDReg);
631 // Add FrameIndex to LDS offset
632 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
633 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
640 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
649 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
654 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
655 MachineBasicBlock &MBB = *MI->getParent();
656 DebugLoc DL = MBB.findDebugLoc(MI);
657 switch (MI->getOpcode()) {
658 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
660 case AMDGPU::SI_CONSTDATA_PTR: {
661 unsigned Reg = MI->getOperand(0).getReg();
662 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
663 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
665 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
667 // Add 32-bit offset from this instruction to the start of the constant data.
668 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
670 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
671 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
672 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
675 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
676 .addReg(AMDGPU::SCC, RegState::Implicit);
677 MI->eraseFromParent();
680 case AMDGPU::SGPR_USE:
681 // This is just a placeholder for register allocation.
682 MI->eraseFromParent();
688 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
690 if (MI->getNumOperands() < 3)
693 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
694 AMDGPU::OpName::src0);
695 assert(Src0Idx != -1 && "Should always have src0 operand");
697 if (!MI->getOperand(Src0Idx).isReg())
700 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
701 AMDGPU::OpName::src1);
703 // Make sure it s legal to commute operands for VOP2.
704 if ((Src1Idx != -1) && isVOP2(MI->getOpcode()) &&
705 (!isOperandLegal(MI, Src0Idx, &MI->getOperand(Src1Idx)) ||
706 !isOperandLegal(MI, Src1Idx, &MI->getOperand(Src0Idx))))
709 if (Src1Idx != -1 && !MI->getOperand(Src1Idx).isReg()) {
710 // XXX: Commute instructions with FPImm operands
711 if (NewMI || !MI->getOperand(Src1Idx).isImm() ||
712 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
716 // XXX: Commute VOP3 instructions with abs and neg set .
717 const MachineOperand *Src0Mods = getNamedOperand(*MI,
718 AMDGPU::OpName::src0_modifiers);
719 const MachineOperand *Src1Mods = getNamedOperand(*MI,
720 AMDGPU::OpName::src1_modifiers);
721 const MachineOperand *Src2Mods = getNamedOperand(*MI,
722 AMDGPU::OpName::src2_modifiers);
724 if ((Src0Mods && Src0Mods->getImm()) ||
725 (Src1Mods && Src1Mods->getImm()) ||
726 (Src2Mods && Src2Mods->getImm()))
729 unsigned Reg = MI->getOperand(Src0Idx).getReg();
730 unsigned SubReg = MI->getOperand(Src0Idx).getSubReg();
731 MI->getOperand(Src0Idx).ChangeToImmediate(MI->getOperand(Src1Idx).getImm());
732 MI->getOperand(Src1Idx).ChangeToRegister(Reg, false);
733 MI->getOperand(Src1Idx).setSubReg(SubReg);
735 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
739 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
744 // This needs to be implemented because the source modifiers may be inserted
745 // between the true commutable operands, and the base
746 // TargetInstrInfo::commuteInstruction uses it.
747 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
749 unsigned &SrcOpIdx2) const {
750 const MCInstrDesc &MCID = MI->getDesc();
751 if (!MCID.isCommutable())
754 unsigned Opc = MI->getOpcode();
755 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
759 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
761 if (!MI->getOperand(Src0Idx).isReg())
764 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
768 if (!MI->getOperand(Src1Idx).isReg())
776 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
777 MachineBasicBlock::iterator I,
779 unsigned SrcReg) const {
780 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
781 DstReg) .addReg(SrcReg);
784 bool SIInstrInfo::isMov(unsigned Opcode) const {
786 default: return false;
787 case AMDGPU::S_MOV_B32:
788 case AMDGPU::S_MOV_B64:
789 case AMDGPU::V_MOV_B32_e32:
790 case AMDGPU::V_MOV_B32_e64:
796 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
797 return RC != &AMDGPU::EXECRegRegClass;
801 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
802 AliasAnalysis *AA) const {
803 switch(MI->getOpcode()) {
804 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
805 case AMDGPU::S_MOV_B32:
806 case AMDGPU::S_MOV_B64:
807 case AMDGPU::V_MOV_B32_e32:
808 return MI->getOperand(1).isImm();
814 // Helper function generated by tablegen. We are wrapping this with
815 // an SIInstrInfo function that returns bool rather than int.
816 int isDS(uint16_t Opcode);
820 bool SIInstrInfo::isDS(uint16_t Opcode) const {
821 return ::AMDGPU::isDS(Opcode) != -1;
824 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
825 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
828 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
829 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
832 bool SIInstrInfo::isMUBUF(uint16_t Opcode) const {
833 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
836 bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
837 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
840 bool SIInstrInfo::isFLAT(uint16_t Opcode) const {
841 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
844 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
845 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
848 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
849 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
852 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
853 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
856 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
857 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
860 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
861 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
864 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
865 int32_t Val = Imm.getSExtValue();
866 if (Val >= -16 && Val <= 64)
869 // The actual type of the operand does not seem to matter as long
870 // as the bits match one of the inline immediate values. For example:
872 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
873 // so it is a legal inline immediate.
875 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
876 // floating-point, so it is a legal inline immediate.
878 return (APInt::floatToBits(0.0f) == Imm) ||
879 (APInt::floatToBits(1.0f) == Imm) ||
880 (APInt::floatToBits(-1.0f) == Imm) ||
881 (APInt::floatToBits(0.5f) == Imm) ||
882 (APInt::floatToBits(-0.5f) == Imm) ||
883 (APInt::floatToBits(2.0f) == Imm) ||
884 (APInt::floatToBits(-2.0f) == Imm) ||
885 (APInt::floatToBits(4.0f) == Imm) ||
886 (APInt::floatToBits(-4.0f) == Imm);
889 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
891 return isInlineConstant(APInt(32, MO.getImm(), true));
894 APFloat FpImm = MO.getFPImm()->getValueAPF();
895 return isInlineConstant(FpImm.bitcastToAPInt());
901 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
902 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
905 static bool compareMachineOp(const MachineOperand &Op0,
906 const MachineOperand &Op1) {
907 if (Op0.getType() != Op1.getType())
910 switch (Op0.getType()) {
911 case MachineOperand::MO_Register:
912 return Op0.getReg() == Op1.getReg();
913 case MachineOperand::MO_Immediate:
914 return Op0.getImm() == Op1.getImm();
915 case MachineOperand::MO_FPImmediate:
916 return Op0.getFPImm() == Op1.getFPImm();
918 llvm_unreachable("Didn't expect to be comparing these operand types");
922 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
923 const MachineOperand &MO) const {
924 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
926 assert(MO.isImm() || MO.isFPImm() || MO.isTargetIndex() || MO.isFI());
928 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
931 if (OpInfo.RegClass < 0)
934 if (isLiteralConstant(MO))
935 return RI.regClassCanUseLiteralConstant(OpInfo.RegClass);
937 return RI.regClassCanUseInlineConstant(OpInfo.RegClass);
940 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) {
942 case AMDGPUAS::GLOBAL_ADDRESS: {
943 // MUBUF instructions a 12-bit offset in bytes.
944 return isUInt<12>(OffsetSize);
946 case AMDGPUAS::CONSTANT_ADDRESS: {
947 // SMRD instructions have an 8-bit offset in dwords.
948 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
950 case AMDGPUAS::LOCAL_ADDRESS:
951 case AMDGPUAS::REGION_ADDRESS: {
952 // The single offset versions have a 16-bit offset in bytes.
953 return isUInt<16>(OffsetSize);
955 case AMDGPUAS::PRIVATE_ADDRESS:
956 // Indirect register addressing does not use any offsets.
962 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
963 return AMDGPU::getVOPe32(Opcode) != -1;
966 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
967 // The src0_modifier operand is present on all instructions
968 // that have modifiers.
970 return AMDGPU::getNamedOperandIdx(Opcode,
971 AMDGPU::OpName::src0_modifiers) != -1;
974 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
975 const MachineOperand &MO) const {
976 // Literal constants use the constant bus.
977 if (isLiteralConstant(MO))
980 if (!MO.isReg() || !MO.isUse())
983 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
984 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
986 // FLAT_SCR is just an SGPR pair.
987 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
990 // EXEC register uses the constant bus.
991 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
994 // SGPRs use the constant bus
995 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
997 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
998 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1005 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1006 StringRef &ErrInfo) const {
1007 uint16_t Opcode = MI->getOpcode();
1008 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1009 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1010 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1011 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1013 // Make sure the number of operands is correct.
1014 const MCInstrDesc &Desc = get(Opcode);
1015 if (!Desc.isVariadic() &&
1016 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1017 ErrInfo = "Instruction has wrong number of operands.";
1021 // Make sure the register classes are correct
1022 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1023 switch (Desc.OpInfo[i].OperandType) {
1024 case MCOI::OPERAND_REGISTER: {
1025 if ((MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm()) &&
1026 !isImmOperandLegal(MI, i, MI->getOperand(i))) {
1027 ErrInfo = "Illegal immediate value for operand.";
1032 case MCOI::OPERAND_IMMEDIATE:
1033 // Check if this operand is an immediate.
1034 // FrameIndex operands will be replaced by immediates, so they are
1036 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
1037 !MI->getOperand(i).isFI()) {
1038 ErrInfo = "Expected immediate, but got non-immediate";
1046 if (!MI->getOperand(i).isReg())
1049 int RegClass = Desc.OpInfo[i].RegClass;
1050 if (RegClass != -1) {
1051 unsigned Reg = MI->getOperand(i).getReg();
1052 if (TargetRegisterInfo::isVirtualRegister(Reg))
1055 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1056 if (!RC->contains(Reg)) {
1057 ErrInfo = "Operand has incorrect register class.";
1065 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1066 unsigned ConstantBusCount = 0;
1067 unsigned SGPRUsed = AMDGPU::NoRegister;
1068 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
1069 const MachineOperand &MO = MI->getOperand(i);
1070 if (usesConstantBus(MRI, MO)) {
1072 if (MO.getReg() != SGPRUsed)
1074 SGPRUsed = MO.getReg();
1080 if (ConstantBusCount > 1) {
1081 ErrInfo = "VOP* instruction uses the constant bus more than once";
1086 // Verify SRC1 for VOP2 and VOPC
1087 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
1088 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1089 if (Src1.isImm() || Src1.isFPImm()) {
1090 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
1096 if (isVOP3(Opcode)) {
1097 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
1098 ErrInfo = "VOP3 src0 cannot be a literal constant.";
1101 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
1102 ErrInfo = "VOP3 src1 cannot be a literal constant.";
1105 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
1106 ErrInfo = "VOP3 src2 cannot be a literal constant.";
1111 // Verify misc. restrictions on specific instructions.
1112 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1113 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1114 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1115 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1116 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1117 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1118 if (!compareMachineOp(Src0, Src1) &&
1119 !compareMachineOp(Src0, Src2)) {
1120 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1129 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1130 switch (MI.getOpcode()) {
1131 default: return AMDGPU::INSTRUCTION_LIST_END;
1132 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1133 case AMDGPU::COPY: return AMDGPU::COPY;
1134 case AMDGPU::PHI: return AMDGPU::PHI;
1135 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1136 case AMDGPU::S_MOV_B32:
1137 return MI.getOperand(1).isReg() ?
1138 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1139 case AMDGPU::S_ADD_I32:
1140 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1141 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1142 case AMDGPU::S_SUB_I32:
1143 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1144 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1145 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1146 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1147 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1148 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1149 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1150 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1151 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1152 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1153 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1154 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1155 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1156 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1157 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1158 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1159 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1160 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1161 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1162 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1163 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1164 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1165 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1166 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1167 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1168 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1169 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1170 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1171 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1172 case AMDGPU::S_LOAD_DWORD_IMM:
1173 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1174 case AMDGPU::S_LOAD_DWORDX2_IMM:
1175 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1176 case AMDGPU::S_LOAD_DWORDX4_IMM:
1177 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1178 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
1179 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1180 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1184 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1185 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1188 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1189 unsigned OpNo) const {
1190 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1191 const MCInstrDesc &Desc = get(MI.getOpcode());
1192 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1193 Desc.OpInfo[OpNo].RegClass == -1)
1194 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
1196 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1197 return RI.getRegClass(RCID);
1200 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1201 switch (MI.getOpcode()) {
1203 case AMDGPU::REG_SEQUENCE:
1205 case AMDGPU::INSERT_SUBREG:
1206 return RI.hasVGPRs(getOpRegClass(MI, 0));
1208 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1212 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1213 MachineBasicBlock::iterator I = MI;
1214 MachineOperand &MO = MI->getOperand(OpIdx);
1215 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1216 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1217 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1218 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1220 Opcode = AMDGPU::COPY;
1221 } else if (RI.isSGPRClass(RC)) {
1222 Opcode = AMDGPU::S_MOV_B32;
1225 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1226 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) {
1227 VRC = &AMDGPU::VReg_64RegClass;
1229 VRC = &AMDGPU::VReg_32RegClass;
1231 unsigned Reg = MRI.createVirtualRegister(VRC);
1232 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
1233 Reg).addOperand(MO);
1234 MO.ChangeToRegister(Reg, false);
1237 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1238 MachineRegisterInfo &MRI,
1239 MachineOperand &SuperReg,
1240 const TargetRegisterClass *SuperRC,
1242 const TargetRegisterClass *SubRC)
1244 assert(SuperReg.isReg());
1246 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1247 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1249 // Just in case the super register is itself a sub-register, copy it to a new
1250 // value so we don't need to worry about merging its subreg index with the
1251 // SubIdx passed to this function. The register coalescer should be able to
1252 // eliminate this extra copy.
1253 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1255 .addOperand(SuperReg);
1257 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1259 .addReg(NewSuperReg, 0, SubIdx);
1263 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1264 MachineBasicBlock::iterator MII,
1265 MachineRegisterInfo &MRI,
1267 const TargetRegisterClass *SuperRC,
1269 const TargetRegisterClass *SubRC) const {
1271 // XXX - Is there a better way to do this?
1272 if (SubIdx == AMDGPU::sub0)
1273 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1274 if (SubIdx == AMDGPU::sub1)
1275 return MachineOperand::CreateImm(Op.getImm() >> 32);
1277 llvm_unreachable("Unhandled register index for immediate");
1280 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1282 return MachineOperand::CreateReg(SubReg, false);
1285 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1286 MachineBasicBlock::iterator MI,
1287 MachineRegisterInfo &MRI,
1288 const TargetRegisterClass *RC,
1289 const MachineOperand &Op) const {
1290 MachineBasicBlock *MBB = MI->getParent();
1291 DebugLoc DL = MI->getDebugLoc();
1292 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1293 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1294 unsigned Dst = MRI.createVirtualRegister(RC);
1296 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1298 .addImm(Op.getImm() & 0xFFFFFFFF);
1299 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1301 .addImm(Op.getImm() >> 32);
1303 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1305 .addImm(AMDGPU::sub0)
1307 .addImm(AMDGPU::sub1);
1309 Worklist.push_back(Lo);
1310 Worklist.push_back(Hi);
1315 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1316 const MachineOperand *MO) const {
1317 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1318 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1319 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1320 const TargetRegisterClass *DefinedRC =
1321 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1323 MO = &MI->getOperand(OpIdx);
1325 if (usesConstantBus(MRI, *MO)) {
1327 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1328 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1331 if (usesConstantBus(MRI, MI->getOperand(i)) &&
1332 MI->getOperand(i).isReg() && MI->getOperand(i).getReg() != SGPRUsed) {
1340 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1341 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass));
1345 // Handle non-register types that are treated like immediates.
1346 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1349 // This operand expects an immediate.
1353 return isImmOperandLegal(MI, OpIdx, *MO);
1356 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1357 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1359 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1360 AMDGPU::OpName::src0);
1361 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1362 AMDGPU::OpName::src1);
1363 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1364 AMDGPU::OpName::src2);
1367 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1369 if (!isOperandLegal(MI, Src0Idx))
1370 legalizeOpWithMove(MI, Src0Idx);
1373 if (isOperandLegal(MI, Src1Idx))
1376 // Usually src0 of VOP2 instructions allow more types of inputs
1377 // than src1, so try to commute the instruction to decrease our
1378 // chances of having to insert a MOV instruction to legalize src1.
1379 if (MI->isCommutable()) {
1380 if (commuteInstruction(MI))
1381 // If we are successful in commuting, then we know MI is legal, so
1386 legalizeOpWithMove(MI, Src1Idx);
1390 // XXX - Do any VOP3 instructions read VCC?
1392 if (isVOP3(MI->getOpcode())) {
1393 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1395 // Find the one SGPR operand we are allowed to use.
1396 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1398 for (unsigned i = 0; i < 3; ++i) {
1399 int Idx = VOP3Idx[i];
1402 MachineOperand &MO = MI->getOperand(Idx);
1405 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1406 continue; // VGPRs are legal
1408 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1410 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1411 SGPRReg = MO.getReg();
1412 // We can use one SGPR in each VOP3 instruction.
1415 } else if (!isLiteralConstant(MO)) {
1416 // If it is not a register and not a literal constant, then it must be
1417 // an inline constant which is always legal.
1420 // If we make it this far, then the operand is not legal and we must
1422 legalizeOpWithMove(MI, Idx);
1426 // Legalize REG_SEQUENCE and PHI
1427 // The register class of the operands much be the same type as the register
1428 // class of the output.
1429 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1430 MI->getOpcode() == AMDGPU::PHI) {
1431 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1432 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1433 if (!MI->getOperand(i).isReg() ||
1434 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1436 const TargetRegisterClass *OpRC =
1437 MRI.getRegClass(MI->getOperand(i).getReg());
1438 if (RI.hasVGPRs(OpRC)) {
1445 // If any of the operands are VGPR registers, then they all most be
1446 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1448 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1451 VRC = RI.getEquivalentVGPRClass(SRC);
1458 // Update all the operands so they have the same type.
1459 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1460 if (!MI->getOperand(i).isReg() ||
1461 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1463 unsigned DstReg = MRI.createVirtualRegister(RC);
1464 MachineBasicBlock *InsertBB;
1465 MachineBasicBlock::iterator Insert;
1466 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1467 InsertBB = MI->getParent();
1470 // MI is a PHI instruction.
1471 InsertBB = MI->getOperand(i + 1).getMBB();
1472 Insert = InsertBB->getFirstTerminator();
1474 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1475 get(AMDGPU::COPY), DstReg)
1476 .addOperand(MI->getOperand(i));
1477 MI->getOperand(i).setReg(DstReg);
1481 // Legalize INSERT_SUBREG
1482 // src0 must have the same register class as dst
1483 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1484 unsigned Dst = MI->getOperand(0).getReg();
1485 unsigned Src0 = MI->getOperand(1).getReg();
1486 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1487 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1488 if (DstRC != Src0RC) {
1489 MachineBasicBlock &MBB = *MI->getParent();
1490 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1491 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1493 MI->getOperand(1).setReg(NewSrc0);
1498 // Legalize MUBUF* instructions
1499 // FIXME: If we start using the non-addr64 instructions for compute, we
1500 // may need to legalize them here.
1502 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1503 if (SRsrcIdx != -1) {
1504 // We have an MUBUF instruction
1505 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1506 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1507 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1508 RI.getRegClass(SRsrcRC))) {
1509 // The operands are legal.
1510 // FIXME: We may need to legalize operands besided srsrc.
1514 MachineBasicBlock &MBB = *MI->getParent();
1515 // Extract the the ptr from the resource descriptor.
1517 // SRsrcPtrLo = srsrc:sub0
1518 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1519 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1521 // SRsrcPtrHi = srsrc:sub1
1522 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1523 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1525 // Create an empty resource descriptor
1526 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1527 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1528 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1529 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1532 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1536 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1537 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1539 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1541 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1542 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1544 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1546 // NewSRsrc = {Zero64, SRsrcFormat}
1547 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1550 .addImm(AMDGPU::sub0_sub1)
1551 .addReg(SRsrcFormatLo)
1552 .addImm(AMDGPU::sub2)
1553 .addReg(SRsrcFormatHi)
1554 .addImm(AMDGPU::sub3);
1556 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1557 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1558 unsigned NewVAddrLo;
1559 unsigned NewVAddrHi;
1561 // This is already an ADDR64 instruction so we need to add the pointer
1562 // extracted from the resource descriptor to the current value of VAddr.
1563 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1564 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1566 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1567 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1570 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1571 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1573 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1574 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1577 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1578 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1579 .addReg(AMDGPU::VCC, RegState::Implicit);
1582 // This instructions is the _OFFSET variant, so we need to convert it to
1584 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1585 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1586 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1587 assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
1588 "with non-zero soffset is not implemented");
1591 // Create the new instruction.
1592 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1593 MachineInstr *Addr64 =
1594 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1597 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1598 // This will be replaced later
1599 // with the new value of vaddr.
1600 .addOperand(*Offset);
1602 MI->removeFromParent();
1605 NewVAddrLo = SRsrcPtrLo;
1606 NewVAddrHi = SRsrcPtrHi;
1607 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1608 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1611 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1612 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1615 .addImm(AMDGPU::sub0)
1617 .addImm(AMDGPU::sub1);
1620 // Update the instruction to use NewVaddr
1621 VAddr->setReg(NewVAddr);
1622 // Update the instruction to use NewSRsrc
1623 SRsrc->setReg(NewSRsrc);
1627 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1628 const TargetRegisterClass *HalfRC,
1629 unsigned HalfImmOp, unsigned HalfSGPROp,
1630 MachineInstr *&Lo, MachineInstr *&Hi) const {
1632 DebugLoc DL = MI->getDebugLoc();
1633 MachineBasicBlock *MBB = MI->getParent();
1634 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1635 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1636 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1637 unsigned HalfSize = HalfRC->getSize();
1638 const MachineOperand *OffOp =
1639 getNamedOperand(*MI, AMDGPU::OpName::offset);
1640 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1643 // Handle the _IMM variant
1644 unsigned LoOffset = OffOp->getImm();
1645 unsigned HiOffset = LoOffset + (HalfSize / 4);
1646 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1650 if (!isUInt<8>(HiOffset)) {
1651 unsigned OffsetSGPR =
1652 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1653 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1654 .addImm(HiOffset << 2); // The immediate offset is in dwords,
1655 // but offset in register is in bytes.
1656 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1658 .addReg(OffsetSGPR);
1660 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1665 // Handle the _SGPR variant
1666 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1667 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1670 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1671 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1674 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1676 .addReg(OffsetSGPR);
1679 unsigned SubLo, SubHi;
1682 SubLo = AMDGPU::sub0;
1683 SubHi = AMDGPU::sub1;
1686 SubLo = AMDGPU::sub0_sub1;
1687 SubHi = AMDGPU::sub2_sub3;
1690 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1691 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1694 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1695 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1698 llvm_unreachable("Unhandled HalfSize");
1701 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1702 .addOperand(MI->getOperand(0))
1709 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1710 MachineBasicBlock *MBB = MI->getParent();
1711 switch (MI->getOpcode()) {
1712 case AMDGPU::S_LOAD_DWORD_IMM:
1713 case AMDGPU::S_LOAD_DWORD_SGPR:
1714 case AMDGPU::S_LOAD_DWORDX2_IMM:
1715 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1716 case AMDGPU::S_LOAD_DWORDX4_IMM:
1717 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1718 unsigned NewOpcode = getVALUOp(*MI);
1722 if (MI->getOperand(2).isReg()) {
1723 RegOffset = MI->getOperand(2).getReg();
1726 assert(MI->getOperand(2).isImm());
1727 // SMRD instructions take a dword offsets and MUBUF instructions
1728 // take a byte offset.
1729 ImmOffset = MI->getOperand(2).getImm() << 2;
1730 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1731 if (isUInt<12>(ImmOffset)) {
1732 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1736 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1743 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1744 unsigned DWord0 = RegOffset;
1745 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1746 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1747 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1749 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1751 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1752 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1753 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1754 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1755 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1757 .addImm(AMDGPU::sub0)
1759 .addImm(AMDGPU::sub1)
1761 .addImm(AMDGPU::sub2)
1763 .addImm(AMDGPU::sub3);
1764 MI->setDesc(get(NewOpcode));
1765 if (MI->getOperand(2).isReg()) {
1766 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1768 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1770 MI->getOperand(1).setReg(SRsrc);
1771 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1773 const TargetRegisterClass *NewDstRC =
1774 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1776 unsigned DstReg = MI->getOperand(0).getReg();
1777 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1778 MRI.replaceRegWith(DstReg, NewDstReg);
1781 case AMDGPU::S_LOAD_DWORDX8_IMM:
1782 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1783 MachineInstr *Lo, *Hi;
1784 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1785 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1786 MI->eraseFromParent();
1787 moveSMRDToVALU(Lo, MRI);
1788 moveSMRDToVALU(Hi, MRI);
1792 case AMDGPU::S_LOAD_DWORDX16_IMM:
1793 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1794 MachineInstr *Lo, *Hi;
1795 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1796 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1797 MI->eraseFromParent();
1798 moveSMRDToVALU(Lo, MRI);
1799 moveSMRDToVALU(Hi, MRI);
1805 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1806 SmallVector<MachineInstr *, 128> Worklist;
1807 Worklist.push_back(&TopInst);
1809 while (!Worklist.empty()) {
1810 MachineInstr *Inst = Worklist.pop_back_val();
1811 MachineBasicBlock *MBB = Inst->getParent();
1812 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1814 unsigned Opcode = Inst->getOpcode();
1815 unsigned NewOpcode = getVALUOp(*Inst);
1817 // Handle some special cases
1820 if (isSMRD(Inst->getOpcode())) {
1821 moveSMRDToVALU(Inst, MRI);
1824 case AMDGPU::S_MOV_B64: {
1825 DebugLoc DL = Inst->getDebugLoc();
1827 // If the source operand is a register we can replace this with a
1829 if (Inst->getOperand(1).isReg()) {
1830 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1831 .addOperand(Inst->getOperand(0))
1832 .addOperand(Inst->getOperand(1));
1833 Worklist.push_back(Copy);
1835 // Otherwise, we need to split this into two movs, because there is
1836 // no 64-bit VALU move instruction.
1837 unsigned Reg = Inst->getOperand(0).getReg();
1838 unsigned Dst = split64BitImm(Worklist,
1841 MRI.getRegClass(Reg),
1842 Inst->getOperand(1));
1843 MRI.replaceRegWith(Reg, Dst);
1845 Inst->eraseFromParent();
1848 case AMDGPU::S_AND_B64:
1849 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1850 Inst->eraseFromParent();
1853 case AMDGPU::S_OR_B64:
1854 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1855 Inst->eraseFromParent();
1858 case AMDGPU::S_XOR_B64:
1859 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1860 Inst->eraseFromParent();
1863 case AMDGPU::S_NOT_B64:
1864 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1865 Inst->eraseFromParent();
1868 case AMDGPU::S_BCNT1_I32_B64:
1869 splitScalar64BitBCNT(Worklist, Inst);
1870 Inst->eraseFromParent();
1873 case AMDGPU::S_BFE_U64:
1874 case AMDGPU::S_BFE_I64:
1875 case AMDGPU::S_BFM_B64:
1876 llvm_unreachable("Moving this op to VALU not implemented");
1879 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1880 // We cannot move this instruction to the VALU, so we should try to
1881 // legalize its operands instead.
1882 legalizeOperands(Inst);
1886 // Use the new VALU Opcode.
1887 const MCInstrDesc &NewDesc = get(NewOpcode);
1888 Inst->setDesc(NewDesc);
1890 // Remove any references to SCC. Vector instructions can't read from it, and
1891 // We're just about to add the implicit use / defs of VCC, and we don't want
1893 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1894 MachineOperand &Op = Inst->getOperand(i);
1895 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1896 Inst->RemoveOperand(i);
1899 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1900 // We are converting these to a BFE, so we need to add the missing
1901 // operands for the size and offset.
1902 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1903 Inst->addOperand(MachineOperand::CreateImm(0));
1904 Inst->addOperand(MachineOperand::CreateImm(Size));
1906 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1907 // The VALU version adds the second operand to the result, so insert an
1909 Inst->addOperand(MachineOperand::CreateImm(0));
1912 addDescImplicitUseDef(NewDesc, Inst);
1914 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1915 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1916 // If we need to move this to VGPRs, we need to unpack the second operand
1917 // back into the 2 separate ones for bit offset and width.
1918 assert(OffsetWidthOp.isImm() &&
1919 "Scalar BFE is only implemented for constant width and offset");
1920 uint32_t Imm = OffsetWidthOp.getImm();
1922 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1923 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1924 Inst->RemoveOperand(2); // Remove old immediate.
1925 Inst->addOperand(MachineOperand::CreateImm(Offset));
1926 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1929 // Update the destination register class.
1931 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1934 // For target instructions, getOpRegClass just returns the virtual
1935 // register class associated with the operand, so we need to find an
1936 // equivalent VGPR register class in order to move the instruction to the
1940 case AMDGPU::REG_SEQUENCE:
1941 case AMDGPU::INSERT_SUBREG:
1942 if (RI.hasVGPRs(NewDstRC))
1944 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1952 unsigned DstReg = Inst->getOperand(0).getReg();
1953 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1954 MRI.replaceRegWith(DstReg, NewDstReg);
1956 // Legalize the operands
1957 legalizeOperands(Inst);
1959 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1960 E = MRI.use_end(); I != E; ++I) {
1961 MachineInstr &UseMI = *I->getParent();
1962 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1963 Worklist.push_back(&UseMI);
1969 //===----------------------------------------------------------------------===//
1970 // Indirect addressing callbacks
1971 //===----------------------------------------------------------------------===//
1973 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1974 unsigned Channel) const {
1975 assert(Channel == 0);
1979 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1980 return &AMDGPU::VReg_32RegClass;
1983 void SIInstrInfo::splitScalar64BitUnaryOp(
1984 SmallVectorImpl<MachineInstr *> &Worklist,
1986 unsigned Opcode) const {
1987 MachineBasicBlock &MBB = *Inst->getParent();
1988 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1990 MachineOperand &Dest = Inst->getOperand(0);
1991 MachineOperand &Src0 = Inst->getOperand(1);
1992 DebugLoc DL = Inst->getDebugLoc();
1994 MachineBasicBlock::iterator MII = Inst;
1996 const MCInstrDesc &InstDesc = get(Opcode);
1997 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1998 MRI.getRegClass(Src0.getReg()) :
1999 &AMDGPU::SGPR_32RegClass;
2001 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2003 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2004 AMDGPU::sub0, Src0SubRC);
2006 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2007 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2009 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2010 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2011 .addOperand(SrcReg0Sub0);
2013 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2014 AMDGPU::sub1, Src0SubRC);
2016 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2017 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2018 .addOperand(SrcReg0Sub1);
2020 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2021 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2023 .addImm(AMDGPU::sub0)
2025 .addImm(AMDGPU::sub1);
2027 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2029 // Try to legalize the operands in case we need to swap the order to keep it
2031 Worklist.push_back(LoHalf);
2032 Worklist.push_back(HiHalf);
2035 void SIInstrInfo::splitScalar64BitBinaryOp(
2036 SmallVectorImpl<MachineInstr *> &Worklist,
2038 unsigned Opcode) const {
2039 MachineBasicBlock &MBB = *Inst->getParent();
2040 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2042 MachineOperand &Dest = Inst->getOperand(0);
2043 MachineOperand &Src0 = Inst->getOperand(1);
2044 MachineOperand &Src1 = Inst->getOperand(2);
2045 DebugLoc DL = Inst->getDebugLoc();
2047 MachineBasicBlock::iterator MII = Inst;
2049 const MCInstrDesc &InstDesc = get(Opcode);
2050 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2051 MRI.getRegClass(Src0.getReg()) :
2052 &AMDGPU::SGPR_32RegClass;
2054 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2055 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2056 MRI.getRegClass(Src1.getReg()) :
2057 &AMDGPU::SGPR_32RegClass;
2059 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2061 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2062 AMDGPU::sub0, Src0SubRC);
2063 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2064 AMDGPU::sub0, Src1SubRC);
2066 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2067 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2069 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2070 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2071 .addOperand(SrcReg0Sub0)
2072 .addOperand(SrcReg1Sub0);
2074 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2075 AMDGPU::sub1, Src0SubRC);
2076 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2077 AMDGPU::sub1, Src1SubRC);
2079 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2080 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2081 .addOperand(SrcReg0Sub1)
2082 .addOperand(SrcReg1Sub1);
2084 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2085 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2087 .addImm(AMDGPU::sub0)
2089 .addImm(AMDGPU::sub1);
2091 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2093 // Try to legalize the operands in case we need to swap the order to keep it
2095 Worklist.push_back(LoHalf);
2096 Worklist.push_back(HiHalf);
2099 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2100 MachineInstr *Inst) const {
2101 MachineBasicBlock &MBB = *Inst->getParent();
2102 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2104 MachineBasicBlock::iterator MII = Inst;
2105 DebugLoc DL = Inst->getDebugLoc();
2107 MachineOperand &Dest = Inst->getOperand(0);
2108 MachineOperand &Src = Inst->getOperand(1);
2110 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
2111 const TargetRegisterClass *SrcRC = Src.isReg() ?
2112 MRI.getRegClass(Src.getReg()) :
2113 &AMDGPU::SGPR_32RegClass;
2115 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2116 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2118 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2120 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2121 AMDGPU::sub0, SrcSubRC);
2122 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2123 AMDGPU::sub1, SrcSubRC);
2125 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2126 .addOperand(SrcRegSub0)
2129 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2130 .addOperand(SrcRegSub1)
2133 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2135 Worklist.push_back(First);
2136 Worklist.push_back(Second);
2139 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2140 MachineInstr *Inst) const {
2141 // Add the implict and explicit register definitions.
2142 if (NewDesc.ImplicitUses) {
2143 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2144 unsigned Reg = NewDesc.ImplicitUses[i];
2145 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2149 if (NewDesc.ImplicitDefs) {
2150 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2151 unsigned Reg = NewDesc.ImplicitDefs[i];
2152 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2157 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2158 int OpIndices[3]) const {
2159 const MCInstrDesc &Desc = get(MI->getOpcode());
2161 // Find the one SGPR operand we are allowed to use.
2162 unsigned SGPRReg = AMDGPU::NoRegister;
2164 // First we need to consider the instruction's operand requirements before
2165 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2166 // of VCC, but we are still bound by the constant bus requirement to only use
2169 // If the operand's class is an SGPR, we can never move it.
2171 for (const MachineOperand &MO : MI->implicit_operands()) {
2172 // We only care about reads.
2176 if (MO.getReg() == AMDGPU::VCC)
2179 if (MO.getReg() == AMDGPU::FLAT_SCR)
2180 return AMDGPU::FLAT_SCR;
2183 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2184 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2186 for (unsigned i = 0; i < 3; ++i) {
2187 int Idx = OpIndices[i];
2191 const MachineOperand &MO = MI->getOperand(Idx);
2192 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2193 SGPRReg = MO.getReg();
2195 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2196 UsedSGPRs[i] = MO.getReg();
2199 if (SGPRReg != AMDGPU::NoRegister)
2202 // We don't have a required SGPR operand, so we have a bit more freedom in
2203 // selecting operands to move.
2205 // Try to select the most used SGPR. If an SGPR is equal to one of the
2206 // others, we choose that.
2209 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2210 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2212 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2213 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2214 SGPRReg = UsedSGPRs[0];
2217 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2218 if (UsedSGPRs[1] == UsedSGPRs[2])
2219 SGPRReg = UsedSGPRs[1];
2225 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2226 MachineBasicBlock *MBB,
2227 MachineBasicBlock::iterator I,
2229 unsigned Address, unsigned OffsetReg) const {
2230 const DebugLoc &DL = MBB->findDebugLoc(I);
2231 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
2232 getIndirectIndexBegin(*MBB->getParent()));
2234 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2235 .addReg(IndirectBaseReg, RegState::Define)
2236 .addOperand(I->getOperand(0))
2237 .addReg(IndirectBaseReg)
2243 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2244 MachineBasicBlock *MBB,
2245 MachineBasicBlock::iterator I,
2247 unsigned Address, unsigned OffsetReg) const {
2248 const DebugLoc &DL = MBB->findDebugLoc(I);
2249 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
2250 getIndirectIndexBegin(*MBB->getParent()));
2252 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2253 .addOperand(I->getOperand(0))
2254 .addOperand(I->getOperand(1))
2255 .addReg(IndirectBaseReg)
2261 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2262 const MachineFunction &MF) const {
2263 int End = getIndirectIndexEnd(MF);
2264 int Begin = getIndirectIndexBegin(MF);
2270 for (int Index = Begin; Index <= End; ++Index)
2271 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
2273 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2274 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2276 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2277 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2279 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2280 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2282 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2283 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2285 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2286 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2289 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2290 unsigned OperandName) const {
2291 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2295 return &MI.getOperand(Idx);