1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/MC/MCInstrDesc.h"
25 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
26 : AMDGPUInstrInfo(tm),
30 const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
34 //===----------------------------------------------------------------------===//
35 // TargetInstrInfo callbacks
36 //===----------------------------------------------------------------------===//
39 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MI, DebugLoc DL,
41 unsigned DestReg, unsigned SrcReg,
44 // If we are trying to copy to or from SCC, there is a bug somewhere else in
45 // the backend. While it may be theoretically possible to do this, it should
46 // never be necessary.
47 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
49 static const int16_t Sub0_15[] = {
50 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
51 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
52 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
53 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
56 static const int16_t Sub0_7[] = {
57 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
58 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
61 static const int16_t Sub0_3[] = {
62 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
65 static const int16_t Sub0_2[] = {
66 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
69 static const int16_t Sub0_1[] = {
70 AMDGPU::sub0, AMDGPU::sub1, 0
74 const int16_t *SubIndices;
76 if (AMDGPU::M0 == DestReg) {
77 // Check if M0 isn't already set to this value
78 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
79 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
81 if (!I->definesRegister(AMDGPU::M0))
84 unsigned Opc = I->getOpcode();
85 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
88 if (!I->readsRegister(SrcReg))
91 // The copy isn't necessary
96 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
97 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
98 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
99 .addReg(SrcReg, getKillRegState(KillSrc));
102 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
103 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
104 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
105 .addReg(SrcReg, getKillRegState(KillSrc));
108 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
109 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
110 Opcode = AMDGPU::S_MOV_B32;
113 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
114 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
115 Opcode = AMDGPU::S_MOV_B32;
118 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
119 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
120 Opcode = AMDGPU::S_MOV_B32;
121 SubIndices = Sub0_15;
123 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
124 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
125 AMDGPU::SReg_32RegClass.contains(SrcReg));
126 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
127 .addReg(SrcReg, getKillRegState(KillSrc));
130 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
131 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
132 AMDGPU::SReg_64RegClass.contains(SrcReg));
133 Opcode = AMDGPU::V_MOV_B32_e32;
136 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
137 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
138 Opcode = AMDGPU::V_MOV_B32_e32;
141 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
142 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
143 AMDGPU::SReg_128RegClass.contains(SrcReg));
144 Opcode = AMDGPU::V_MOV_B32_e32;
147 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
148 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
149 AMDGPU::SReg_256RegClass.contains(SrcReg));
150 Opcode = AMDGPU::V_MOV_B32_e32;
153 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
154 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
155 AMDGPU::SReg_512RegClass.contains(SrcReg));
156 Opcode = AMDGPU::V_MOV_B32_e32;
157 SubIndices = Sub0_15;
160 llvm_unreachable("Can't copy register!");
163 while (unsigned SubIdx = *SubIndices++) {
164 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
165 get(Opcode), RI.getSubReg(DestReg, SubIdx));
167 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
170 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
174 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
177 // Try to map original to commuted opcode
178 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
181 // Try to map commuted to original opcode
182 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
188 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
191 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
192 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
195 // Cannot commute VOP2 if src0 is SGPR.
196 if (isVOP2(MI->getOpcode()) && MI->getOperand(1).isReg() &&
197 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
200 if (!MI->getOperand(2).isReg()) {
201 // XXX: Commute instructions with FPImm operands
202 if (NewMI || MI->getOperand(2).isFPImm() ||
203 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
207 // XXX: Commute VOP3 instructions with abs and neg set.
208 if (isVOP3(MI->getOpcode()) &&
209 (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
210 AMDGPU::OpName::abs)).getImm() ||
211 MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
212 AMDGPU::OpName::neg)).getImm()))
215 unsigned Reg = MI->getOperand(1).getReg();
216 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
217 MI->getOperand(2).ChangeToRegister(Reg, false);
219 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
223 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
228 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
229 MachineBasicBlock::iterator I,
231 unsigned SrcReg) const {
232 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
233 DstReg) .addReg(SrcReg);
236 bool SIInstrInfo::isMov(unsigned Opcode) const {
238 default: return false;
239 case AMDGPU::S_MOV_B32:
240 case AMDGPU::S_MOV_B64:
241 case AMDGPU::V_MOV_B32_e32:
242 case AMDGPU::V_MOV_B32_e64:
248 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
249 return RC != &AMDGPU::EXECRegRegClass;
252 int SIInstrInfo::isMIMG(uint16_t Opcode) const {
253 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
256 int SIInstrInfo::isSMRD(uint16_t Opcode) const {
257 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
260 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
261 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
264 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
265 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
268 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
269 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
272 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
273 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
276 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
277 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
280 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
282 return MO.getImm() >= -16 && MO.getImm() <= 64;
285 return MO.getFPImm()->isExactlyValue(0.0) ||
286 MO.getFPImm()->isExactlyValue(0.5) ||
287 MO.getFPImm()->isExactlyValue(-0.5) ||
288 MO.getFPImm()->isExactlyValue(1.0) ||
289 MO.getFPImm()->isExactlyValue(-1.0) ||
290 MO.getFPImm()->isExactlyValue(2.0) ||
291 MO.getFPImm()->isExactlyValue(-2.0) ||
292 MO.getFPImm()->isExactlyValue(4.0) ||
293 MO.getFPImm()->isExactlyValue(-4.0);
298 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
299 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
302 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
303 StringRef &ErrInfo) const {
304 uint16_t Opcode = MI->getOpcode();
305 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
306 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
307 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
310 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
311 unsigned ConstantBusCount = 0;
312 unsigned SGPRUsed = AMDGPU::NoRegister;
313 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
314 const MachineOperand &MO = MI->getOperand(i);
315 if (MO.isReg() && MO.isUse() &&
316 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
318 // EXEC register uses the constant bus.
319 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
322 // SGPRs use the constant bus
323 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
325 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
326 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
327 if (SGPRUsed != MO.getReg()) {
329 SGPRUsed = MO.getReg();
333 // Literal constants use the constant bus.
334 if (isLiteralConstant(MO))
337 if (ConstantBusCount > 1) {
338 ErrInfo = "VOP* instruction uses the constant bus more than once";
343 // Verify SRC1 for VOP2 and VOPC
344 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
345 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
346 if (Src1.isImm() || Src1.isFPImm()) {
347 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
353 if (isVOP3(Opcode)) {
354 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
355 ErrInfo = "VOP3 src0 cannot be a literal constant.";
358 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
359 ErrInfo = "VOP3 src1 cannot be a literal constant.";
362 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
363 ErrInfo = "VOP3 src2 cannot be a literal constant.";
370 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
371 switch (MI.getOpcode()) {
372 default: return AMDGPU::INSTRUCTION_LIST_END;
373 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
374 case AMDGPU::COPY: return AMDGPU::COPY;
375 case AMDGPU::PHI: return AMDGPU::PHI;
376 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
377 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
378 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
379 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
380 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
381 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
385 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
386 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
389 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
390 unsigned OpNo) const {
391 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
392 const MCInstrDesc &Desc = get(MI.getOpcode());
393 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
394 Desc.OpInfo[OpNo].RegClass == -1)
395 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
397 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
398 return RI.getRegClass(RCID);
401 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
402 switch (MI.getOpcode()) {
404 case AMDGPU::REG_SEQUENCE:
405 return RI.hasVGPRs(getOpRegClass(MI, 0));
407 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
411 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
412 MachineBasicBlock::iterator I = MI;
413 MachineOperand &MO = MI->getOperand(OpIdx);
414 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
415 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
416 const TargetRegisterClass *RC = RI.getRegClass(RCID);
417 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
419 Opcode = AMDGPU::COPY;
420 } else if (RI.isSGPRClass(RC)) {
421 Opcode = AMDGPU::S_MOV_B32;
424 unsigned Reg = MRI.createVirtualRegister(RI.getRegClass(RCID));
425 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
427 MO.ChangeToRegister(Reg, false);
430 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
431 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
432 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
433 AMDGPU::OpName::src0);
434 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
435 AMDGPU::OpName::src1);
436 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
437 AMDGPU::OpName::src2);
440 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
441 MachineOperand &Src1 = MI->getOperand(Src1Idx);
443 // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
444 // be the first operand, and there can only be one.
445 if (Src1.isImm() || Src1.isFPImm() ||
446 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
447 if (MI->isCommutable()) {
448 if (commuteInstruction(MI))
451 legalizeOpWithMove(MI, Src1Idx);
456 if (isVOP3(MI->getOpcode())) {
457 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
458 unsigned SGPRReg = AMDGPU::NoRegister;
459 for (unsigned i = 0; i < 3; ++i) {
460 int Idx = VOP3Idx[i];
463 MachineOperand &MO = MI->getOperand(Idx);
466 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
467 continue; // VGPRs are legal
469 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
470 SGPRReg = MO.getReg();
471 // We can use one SGPR in each VOP3 instruction.
474 } else if (!isLiteralConstant(MO)) {
475 // If it is not a register and not a literal constant, then it must be
476 // an inline constant which is always legal.
479 // If we make it this far, then the operand is not legal and we must
481 legalizeOpWithMove(MI, Idx);
485 // Legalize REG_SEQUENCE
486 // The register class of the operands much be the same type as the register
487 // class of the output.
488 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
489 const TargetRegisterClass *RC = NULL, *SRC = NULL, *VRC = NULL;
490 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
491 if (!MI->getOperand(i).isReg() ||
492 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
494 const TargetRegisterClass *OpRC =
495 MRI.getRegClass(MI->getOperand(i).getReg());
496 if (RI.hasVGPRs(OpRC)) {
503 // If any of the operands are VGPR registers, then they all most be
504 // otherwise we will create illegal VGPR->SGPR copies when legalizing
506 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
509 VRC = RI.getEquivalentVGPRClass(SRC);
516 // Update all the operands so they have the same type.
517 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
518 if (!MI->getOperand(i).isReg() ||
519 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
521 unsigned DstReg = MRI.createVirtualRegister(RC);
522 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
523 get(AMDGPU::COPY), DstReg)
524 .addOperand(MI->getOperand(i));
525 MI->getOperand(i).setReg(DstReg);
530 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
531 SmallVector<MachineInstr *, 128> Worklist;
532 Worklist.push_back(&TopInst);
534 while (!Worklist.empty()) {
535 MachineInstr *Inst = Worklist.pop_back_val();
536 unsigned NewOpcode = getVALUOp(*Inst);
537 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
540 MachineRegisterInfo &MRI = Inst->getParent()->getParent()->getRegInfo();
542 // Use the new VALU Opcode.
543 const MCInstrDesc &NewDesc = get(NewOpcode);
544 Inst->setDesc(NewDesc);
546 // Add the implict and explicit register definitions.
547 if (NewDesc.ImplicitUses) {
548 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
549 Inst->addOperand(MachineOperand::CreateReg(NewDesc.ImplicitUses[i],
554 if (NewDesc.ImplicitDefs) {
555 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
556 Inst->addOperand(MachineOperand::CreateReg(NewDesc.ImplicitDefs[i],
561 legalizeOperands(Inst);
563 // Update the destination register class.
564 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
566 switch (Inst->getOpcode()) {
567 // For target instructions, getOpRegClass just returns the virtual
568 // register class associated with the operand, so we need to find an
569 // equivalent VGPR register class in order to move the instruction to the
573 case AMDGPU::REG_SEQUENCE:
574 if (RI.hasVGPRs(NewDstRC))
576 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
584 unsigned DstReg = Inst->getOperand(0).getReg();
585 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
586 MRI.replaceRegWith(DstReg, NewDstReg);
588 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
589 E = MRI.use_end(); I != E; ++I) {
590 MachineInstr &UseMI = *I;
591 if (!canReadVGPR(UseMI, I.getOperandNo())) {
592 Worklist.push_back(&UseMI);
598 //===----------------------------------------------------------------------===//
599 // Indirect addressing callbacks
600 //===----------------------------------------------------------------------===//
602 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
603 unsigned Channel) const {
604 assert(Channel == 0);
608 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
609 return &AMDGPU::VReg_32RegClass;
612 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
613 MachineBasicBlock *MBB,
614 MachineBasicBlock::iterator I,
616 unsigned Address, unsigned OffsetReg) const {
617 const DebugLoc &DL = MBB->findDebugLoc(I);
618 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
619 getIndirectIndexBegin(*MBB->getParent()));
621 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
622 .addReg(IndirectBaseReg, RegState::Define)
623 .addOperand(I->getOperand(0))
624 .addReg(IndirectBaseReg)
630 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
631 MachineBasicBlock *MBB,
632 MachineBasicBlock::iterator I,
634 unsigned Address, unsigned OffsetReg) const {
635 const DebugLoc &DL = MBB->findDebugLoc(I);
636 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
637 getIndirectIndexBegin(*MBB->getParent()));
639 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
640 .addOperand(I->getOperand(0))
641 .addOperand(I->getOperand(1))
642 .addReg(IndirectBaseReg)
648 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
649 const MachineFunction &MF) const {
650 int End = getIndirectIndexEnd(MF);
651 int Begin = getIndirectIndexBegin(MF);
657 for (int Index = Begin; Index <= End; ++Index)
658 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
660 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
661 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
663 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
664 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
666 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
667 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
669 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
670 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
672 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
673 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));