1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCInstrDesc.h"
27 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
28 : AMDGPUInstrInfo(st),
31 //===----------------------------------------------------------------------===//
32 // TargetInstrInfo callbacks
33 //===----------------------------------------------------------------------===//
36 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator MI, DebugLoc DL,
38 unsigned DestReg, unsigned SrcReg,
41 // If we are trying to copy to or from SCC, there is a bug somewhere else in
42 // the backend. While it may be theoretically possible to do this, it should
43 // never be necessary.
44 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
46 static const int16_t Sub0_15[] = {
47 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
48 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
49 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
50 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
53 static const int16_t Sub0_7[] = {
54 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
55 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
58 static const int16_t Sub0_3[] = {
59 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
62 static const int16_t Sub0_2[] = {
63 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
66 static const int16_t Sub0_1[] = {
67 AMDGPU::sub0, AMDGPU::sub1, 0
71 const int16_t *SubIndices;
73 if (AMDGPU::M0 == DestReg) {
74 // Check if M0 isn't already set to this value
75 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
76 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
78 if (!I->definesRegister(AMDGPU::M0))
81 unsigned Opc = I->getOpcode();
82 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
85 if (!I->readsRegister(SrcReg))
88 // The copy isn't necessary
93 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
94 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
95 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
96 .addReg(SrcReg, getKillRegState(KillSrc));
99 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
100 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
101 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
102 .addReg(SrcReg, getKillRegState(KillSrc));
105 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
106 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
107 Opcode = AMDGPU::S_MOV_B32;
110 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
111 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
112 Opcode = AMDGPU::S_MOV_B32;
115 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
116 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
117 Opcode = AMDGPU::S_MOV_B32;
118 SubIndices = Sub0_15;
120 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
121 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
122 AMDGPU::SReg_32RegClass.contains(SrcReg));
123 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
124 .addReg(SrcReg, getKillRegState(KillSrc));
127 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
128 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
129 AMDGPU::SReg_64RegClass.contains(SrcReg));
130 Opcode = AMDGPU::V_MOV_B32_e32;
133 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
134 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
135 Opcode = AMDGPU::V_MOV_B32_e32;
138 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
139 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
140 AMDGPU::SReg_128RegClass.contains(SrcReg));
141 Opcode = AMDGPU::V_MOV_B32_e32;
144 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
145 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
146 AMDGPU::SReg_256RegClass.contains(SrcReg));
147 Opcode = AMDGPU::V_MOV_B32_e32;
150 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
151 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
152 AMDGPU::SReg_512RegClass.contains(SrcReg));
153 Opcode = AMDGPU::V_MOV_B32_e32;
154 SubIndices = Sub0_15;
157 llvm_unreachable("Can't copy register!");
160 while (unsigned SubIdx = *SubIndices++) {
161 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
162 get(Opcode), RI.getSubReg(DestReg, SubIdx));
164 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
167 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
171 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
174 // Try to map original to commuted opcode
175 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
178 // Try to map commuted to original opcode
179 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
185 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator MI,
187 unsigned SrcReg, bool isKill,
189 const TargetRegisterClass *RC,
190 const TargetRegisterInfo *TRI) const {
191 MachineFunction *MF = MBB.getParent();
192 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
193 MachineRegisterInfo &MRI = MF->getRegInfo();
194 DebugLoc DL = MBB.findDebugLoc(MI);
195 unsigned KillFlag = isKill ? RegState::Kill : 0;
197 if (RI.hasVGPRs(RC)) {
198 LLVMContext &Ctx = MF->getFunction()->getContext();
199 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
200 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
202 } else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
203 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
204 unsigned TgtReg = MFI->SpillTracker.LaneVGPR;
206 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), TgtReg)
207 .addReg(SrcReg, KillFlag)
209 MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane);
210 } else if (RI.isSGPRClass(RC)) {
211 // We are only allowed to create one new instruction when spilling
212 // registers, so we need to use pseudo instruction for vector
215 // Reserve a spot in the spill tracker for each sub-register of
216 // the vector register.
217 unsigned NumSubRegs = RC->getSize() / 4;
218 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs);
219 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
223 switch (RC->getSize() * 8) {
224 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
225 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
226 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
227 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
228 default: llvm_unreachable("Cannot spill register class");
231 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
235 llvm_unreachable("VGPR spilling not supported");
239 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator MI,
241 unsigned DestReg, int FrameIndex,
242 const TargetRegisterClass *RC,
243 const TargetRegisterInfo *TRI) const {
244 MachineFunction *MF = MBB.getParent();
245 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
246 DebugLoc DL = MBB.findDebugLoc(MI);
248 if (RI.hasVGPRs(RC)) {
249 LLVMContext &Ctx = MF->getFunction()->getContext();
250 Ctx.emitError("SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!");
251 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
253 } else if (RI.isSGPRClass(RC)){
255 switch(RC->getSize() * 8) {
256 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
257 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
258 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
259 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
260 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
261 default: llvm_unreachable("Cannot spill register class");
264 SIMachineFunctionInfo::SpilledReg Spill =
265 MFI->SpillTracker.getSpilledReg(FrameIndex);
267 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
271 llvm_unreachable("VGPR spilling not supported");
275 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
278 case AMDGPU::SI_SPILL_S512_SAVE:
279 case AMDGPU::SI_SPILL_S512_RESTORE:
281 case AMDGPU::SI_SPILL_S256_SAVE:
282 case AMDGPU::SI_SPILL_S256_RESTORE:
284 case AMDGPU::SI_SPILL_S128_SAVE:
285 case AMDGPU::SI_SPILL_S128_RESTORE:
287 case AMDGPU::SI_SPILL_S64_SAVE:
288 case AMDGPU::SI_SPILL_S64_RESTORE:
290 case AMDGPU::SI_SPILL_S32_RESTORE:
292 default: llvm_unreachable("Invalid spill opcode");
296 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
305 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
310 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
311 SIMachineFunctionInfo *MFI =
312 MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
313 MachineBasicBlock &MBB = *MI->getParent();
314 DebugLoc DL = MBB.findDebugLoc(MI);
315 switch (MI->getOpcode()) {
316 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
318 // SGPR register spill
319 case AMDGPU::SI_SPILL_S512_SAVE:
320 case AMDGPU::SI_SPILL_S256_SAVE:
321 case AMDGPU::SI_SPILL_S128_SAVE:
322 case AMDGPU::SI_SPILL_S64_SAVE: {
323 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
324 unsigned FrameIndex = MI->getOperand(2).getImm();
326 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
327 SIMachineFunctionInfo::SpilledReg Spill;
328 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
329 &AMDGPU::SGPR_32RegClass, i);
330 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
332 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
333 MI->getOperand(0).getReg())
335 .addImm(Spill.Lane + i);
337 MI->eraseFromParent();
341 // SGPR register restore
342 case AMDGPU::SI_SPILL_S512_RESTORE:
343 case AMDGPU::SI_SPILL_S256_RESTORE:
344 case AMDGPU::SI_SPILL_S128_RESTORE:
345 case AMDGPU::SI_SPILL_S64_RESTORE:
346 case AMDGPU::SI_SPILL_S32_RESTORE: {
347 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
349 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
350 SIMachineFunctionInfo::SpilledReg Spill;
351 unsigned FrameIndex = MI->getOperand(2).getImm();
352 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
353 &AMDGPU::SGPR_32RegClass, i);
354 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
356 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
357 .addReg(MI->getOperand(1).getReg())
358 .addImm(Spill.Lane + i);
361 MI->eraseFromParent();
364 case AMDGPU::SI_CONSTDATA_PTR: {
365 unsigned Reg = MI->getOperand(0).getReg();
366 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
367 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
369 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
371 // Add 32-bit offset from this instruction to the start of the constant data.
372 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_I32), RegLo)
374 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
375 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
376 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
379 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
380 .addReg(AMDGPU::SCC, RegState::Implicit);
381 MI->eraseFromParent();
388 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
391 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
392 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
395 // Cannot commute VOP2 if src0 is SGPR.
396 if (isVOP2(MI->getOpcode()) && MI->getOperand(1).isReg() &&
397 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
400 if (!MI->getOperand(2).isReg()) {
401 // XXX: Commute instructions with FPImm operands
402 if (NewMI || MI->getOperand(2).isFPImm() ||
403 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
407 // XXX: Commute VOP3 instructions with abs and neg set.
408 if (isVOP3(MI->getOpcode()) &&
409 (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
410 AMDGPU::OpName::abs)).getImm() ||
411 MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
412 AMDGPU::OpName::neg)).getImm()))
415 unsigned Reg = MI->getOperand(1).getReg();
416 unsigned SubReg = MI->getOperand(1).getSubReg();
417 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
418 MI->getOperand(2).ChangeToRegister(Reg, false);
419 MI->getOperand(2).setSubReg(SubReg);
421 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
425 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
430 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
431 MachineBasicBlock::iterator I,
433 unsigned SrcReg) const {
434 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
435 DstReg) .addReg(SrcReg);
438 bool SIInstrInfo::isMov(unsigned Opcode) const {
440 default: return false;
441 case AMDGPU::S_MOV_B32:
442 case AMDGPU::S_MOV_B64:
443 case AMDGPU::V_MOV_B32_e32:
444 case AMDGPU::V_MOV_B32_e64:
450 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
451 return RC != &AMDGPU::EXECRegRegClass;
455 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
456 AliasAnalysis *AA) const {
457 switch(MI->getOpcode()) {
458 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
459 case AMDGPU::S_MOV_B32:
460 case AMDGPU::S_MOV_B64:
461 case AMDGPU::V_MOV_B32_e32:
462 return MI->getOperand(1).isImm();
468 // Helper function generated by tablegen. We are wrapping this with
469 // an SIInstrInfo function that reutrns bool rather than int.
470 int isDS(uint16_t Opcode);
474 bool SIInstrInfo::isDS(uint16_t Opcode) const {
475 return ::AMDGPU::isDS(Opcode) != -1;
478 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
479 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
482 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
483 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
486 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
487 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
490 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
491 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
494 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
495 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
498 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
499 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
502 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
503 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
506 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
507 int32_t Val = Imm.getSExtValue();
508 if (Val >= -16 && Val <= 64)
511 // The actual type of the operand does not seem to matter as long
512 // as the bits match one of the inline immediate values. For example:
514 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
515 // so it is a legal inline immediate.
517 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
518 // floating-point, so it is a legal inline immediate.
520 return (APInt::floatToBits(0.0f) == Imm) ||
521 (APInt::floatToBits(1.0f) == Imm) ||
522 (APInt::floatToBits(-1.0f) == Imm) ||
523 (APInt::floatToBits(0.5f) == Imm) ||
524 (APInt::floatToBits(-0.5f) == Imm) ||
525 (APInt::floatToBits(2.0f) == Imm) ||
526 (APInt::floatToBits(-2.0f) == Imm) ||
527 (APInt::floatToBits(4.0f) == Imm) ||
528 (APInt::floatToBits(-4.0f) == Imm);
531 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
533 return isInlineConstant(APInt(32, MO.getImm(), true));
536 APFloat FpImm = MO.getFPImm()->getValueAPF();
537 return isInlineConstant(FpImm.bitcastToAPInt());
543 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
544 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
547 static bool compareMachineOp(const MachineOperand &Op0,
548 const MachineOperand &Op1) {
549 if (Op0.getType() != Op1.getType())
552 switch (Op0.getType()) {
553 case MachineOperand::MO_Register:
554 return Op0.getReg() == Op1.getReg();
555 case MachineOperand::MO_Immediate:
556 return Op0.getImm() == Op1.getImm();
557 case MachineOperand::MO_FPImmediate:
558 return Op0.getFPImm() == Op1.getFPImm();
560 llvm_unreachable("Didn't expect to be comparing these operand types");
564 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
565 const MachineOperand &MO) const {
566 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
568 assert(MO.isImm() || MO.isFPImm());
570 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
573 if (OpInfo.RegClass < 0)
576 return RI.regClassCanUseImmediate(OpInfo.RegClass);
579 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
580 StringRef &ErrInfo) const {
581 uint16_t Opcode = MI->getOpcode();
582 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
583 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
584 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
586 // Make sure the number of operands is correct.
587 const MCInstrDesc &Desc = get(Opcode);
588 if (!Desc.isVariadic() &&
589 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
590 ErrInfo = "Instruction has wrong number of operands.";
594 // Make sure the register classes are correct
595 for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
596 switch (Desc.OpInfo[i].OperandType) {
597 case MCOI::OPERAND_REGISTER: {
598 int RegClass = Desc.OpInfo[i].RegClass;
599 if (!RI.regClassCanUseImmediate(RegClass) &&
600 (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
601 ErrInfo = "Expected register, but got immediate";
606 case MCOI::OPERAND_IMMEDIATE:
607 // Check if this operand is an immediate.
608 // FrameIndex operands will be replaced by immediates, so they are
610 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
611 !MI->getOperand(i).isFI()) {
612 ErrInfo = "Expected immediate, but got non-immediate";
620 if (!MI->getOperand(i).isReg())
623 int RegClass = Desc.OpInfo[i].RegClass;
624 if (RegClass != -1) {
625 unsigned Reg = MI->getOperand(i).getReg();
626 if (TargetRegisterInfo::isVirtualRegister(Reg))
629 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
630 if (!RC->contains(Reg)) {
631 ErrInfo = "Operand has incorrect register class.";
639 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
640 unsigned ConstantBusCount = 0;
641 unsigned SGPRUsed = AMDGPU::NoRegister;
642 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
643 const MachineOperand &MO = MI->getOperand(i);
644 if (MO.isReg() && MO.isUse() &&
645 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
647 // EXEC register uses the constant bus.
648 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
651 // SGPRs use the constant bus
652 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
654 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
655 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
656 if (SGPRUsed != MO.getReg()) {
658 SGPRUsed = MO.getReg();
662 // Literal constants use the constant bus.
663 if (isLiteralConstant(MO))
666 if (ConstantBusCount > 1) {
667 ErrInfo = "VOP* instruction uses the constant bus more than once";
672 // Verify SRC1 for VOP2 and VOPC
673 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
674 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
675 if (Src1.isImm() || Src1.isFPImm()) {
676 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
682 if (isVOP3(Opcode)) {
683 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
684 ErrInfo = "VOP3 src0 cannot be a literal constant.";
687 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
688 ErrInfo = "VOP3 src1 cannot be a literal constant.";
691 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
692 ErrInfo = "VOP3 src2 cannot be a literal constant.";
697 // Verify misc. restrictions on specific instructions.
698 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
699 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
702 const MachineOperand &Src0 = MI->getOperand(2);
703 const MachineOperand &Src1 = MI->getOperand(3);
704 const MachineOperand &Src2 = MI->getOperand(4);
705 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
706 if (!compareMachineOp(Src0, Src1) &&
707 !compareMachineOp(Src0, Src2)) {
708 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
717 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
718 switch (MI.getOpcode()) {
719 default: return AMDGPU::INSTRUCTION_LIST_END;
720 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
721 case AMDGPU::COPY: return AMDGPU::COPY;
722 case AMDGPU::PHI: return AMDGPU::PHI;
723 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
724 case AMDGPU::S_MOV_B32:
725 return MI.getOperand(1).isReg() ?
726 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
727 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
728 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
729 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
730 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
731 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
732 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
733 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
734 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
735 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
736 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
737 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
738 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
739 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
740 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
741 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
742 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
743 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
744 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
745 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
746 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
747 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
748 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
749 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
750 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
751 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
752 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
753 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
754 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
755 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
756 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
757 case AMDGPU::S_LOAD_DWORD_IMM:
758 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
759 case AMDGPU::S_LOAD_DWORDX2_IMM:
760 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
761 case AMDGPU::S_LOAD_DWORDX4_IMM:
762 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
763 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
764 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
765 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
769 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
770 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
773 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
774 unsigned OpNo) const {
775 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
776 const MCInstrDesc &Desc = get(MI.getOpcode());
777 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
778 Desc.OpInfo[OpNo].RegClass == -1)
779 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
781 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
782 return RI.getRegClass(RCID);
785 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
786 switch (MI.getOpcode()) {
788 case AMDGPU::REG_SEQUENCE:
790 case AMDGPU::INSERT_SUBREG:
791 return RI.hasVGPRs(getOpRegClass(MI, 0));
793 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
797 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
798 MachineBasicBlock::iterator I = MI;
799 MachineOperand &MO = MI->getOperand(OpIdx);
800 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
801 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
802 const TargetRegisterClass *RC = RI.getRegClass(RCID);
803 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
805 Opcode = AMDGPU::COPY;
806 } else if (RI.isSGPRClass(RC)) {
807 Opcode = AMDGPU::S_MOV_B32;
810 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
811 unsigned Reg = MRI.createVirtualRegister(VRC);
812 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
814 MO.ChangeToRegister(Reg, false);
817 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
818 MachineRegisterInfo &MRI,
819 MachineOperand &SuperReg,
820 const TargetRegisterClass *SuperRC,
822 const TargetRegisterClass *SubRC)
824 assert(SuperReg.isReg());
826 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
827 unsigned SubReg = MRI.createVirtualRegister(SubRC);
829 // Just in case the super register is itself a sub-register, copy it to a new
830 // value so we don't need to worry about merging its subreg index with the
831 // SubIdx passed to this function. The register coalescer should be able to
832 // eliminate this extra copy.
833 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
835 .addOperand(SuperReg);
837 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
839 .addReg(NewSuperReg, 0, SubIdx);
843 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
844 MachineBasicBlock::iterator MII,
845 MachineRegisterInfo &MRI,
847 const TargetRegisterClass *SuperRC,
849 const TargetRegisterClass *SubRC) const {
851 // XXX - Is there a better way to do this?
852 if (SubIdx == AMDGPU::sub0)
853 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
854 if (SubIdx == AMDGPU::sub1)
855 return MachineOperand::CreateImm(Op.getImm() >> 32);
857 llvm_unreachable("Unhandled register index for immediate");
860 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
862 return MachineOperand::CreateReg(SubReg, false);
865 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
866 MachineBasicBlock::iterator MI,
867 MachineRegisterInfo &MRI,
868 const TargetRegisterClass *RC,
869 const MachineOperand &Op) const {
870 MachineBasicBlock *MBB = MI->getParent();
871 DebugLoc DL = MI->getDebugLoc();
872 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
873 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
874 unsigned Dst = MRI.createVirtualRegister(RC);
876 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
878 .addImm(Op.getImm() & 0xFFFFFFFF);
879 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
881 .addImm(Op.getImm() >> 32);
883 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
885 .addImm(AMDGPU::sub0)
887 .addImm(AMDGPU::sub1);
889 Worklist.push_back(Lo);
890 Worklist.push_back(Hi);
895 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
896 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
897 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
898 AMDGPU::OpName::src0);
899 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
900 AMDGPU::OpName::src1);
901 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
902 AMDGPU::OpName::src2);
905 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
906 MachineOperand &Src0 = MI->getOperand(Src0Idx);
907 MachineOperand &Src1 = MI->getOperand(Src1Idx);
909 // If the instruction implicitly reads VCC, we can't have any SGPR operands,
911 bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI);
912 if (ReadsVCC && Src0.isReg() &&
913 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {
914 legalizeOpWithMove(MI, Src0Idx);
918 if (ReadsVCC && Src1.isReg() &&
919 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
920 legalizeOpWithMove(MI, Src1Idx);
924 // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
925 // be the first operand, and there can only be one.
926 if (Src1.isImm() || Src1.isFPImm() ||
927 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
928 if (MI->isCommutable()) {
929 if (commuteInstruction(MI))
932 legalizeOpWithMove(MI, Src1Idx);
936 // XXX - Do any VOP3 instructions read VCC?
938 if (isVOP3(MI->getOpcode())) {
939 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
940 unsigned SGPRReg = AMDGPU::NoRegister;
941 for (unsigned i = 0; i < 3; ++i) {
942 int Idx = VOP3Idx[i];
945 MachineOperand &MO = MI->getOperand(Idx);
948 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
949 continue; // VGPRs are legal
951 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
953 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
954 SGPRReg = MO.getReg();
955 // We can use one SGPR in each VOP3 instruction.
958 } else if (!isLiteralConstant(MO)) {
959 // If it is not a register and not a literal constant, then it must be
960 // an inline constant which is always legal.
963 // If we make it this far, then the operand is not legal and we must
965 legalizeOpWithMove(MI, Idx);
969 // Legalize REG_SEQUENCE and PHI
970 // The register class of the operands much be the same type as the register
971 // class of the output.
972 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
973 MI->getOpcode() == AMDGPU::PHI) {
974 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
975 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
976 if (!MI->getOperand(i).isReg() ||
977 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
979 const TargetRegisterClass *OpRC =
980 MRI.getRegClass(MI->getOperand(i).getReg());
981 if (RI.hasVGPRs(OpRC)) {
988 // If any of the operands are VGPR registers, then they all most be
989 // otherwise we will create illegal VGPR->SGPR copies when legalizing
991 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
994 VRC = RI.getEquivalentVGPRClass(SRC);
1001 // Update all the operands so they have the same type.
1002 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1003 if (!MI->getOperand(i).isReg() ||
1004 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1006 unsigned DstReg = MRI.createVirtualRegister(RC);
1007 MachineBasicBlock *InsertBB;
1008 MachineBasicBlock::iterator Insert;
1009 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1010 InsertBB = MI->getParent();
1013 // MI is a PHI instruction.
1014 InsertBB = MI->getOperand(i + 1).getMBB();
1015 Insert = InsertBB->getFirstTerminator();
1017 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1018 get(AMDGPU::COPY), DstReg)
1019 .addOperand(MI->getOperand(i));
1020 MI->getOperand(i).setReg(DstReg);
1024 // Legalize INSERT_SUBREG
1025 // src0 must have the same register class as dst
1026 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1027 unsigned Dst = MI->getOperand(0).getReg();
1028 unsigned Src0 = MI->getOperand(1).getReg();
1029 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1030 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1031 if (DstRC != Src0RC) {
1032 MachineBasicBlock &MBB = *MI->getParent();
1033 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1034 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1036 MI->getOperand(1).setReg(NewSrc0);
1041 // Legalize MUBUF* instructions
1042 // FIXME: If we start using the non-addr64 instructions for compute, we
1043 // may need to legalize them here.
1045 int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1046 AMDGPU::OpName::srsrc);
1047 int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1048 AMDGPU::OpName::vaddr);
1049 if (SRsrcIdx != -1 && VAddrIdx != -1) {
1050 const TargetRegisterClass *VAddrRC =
1051 RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
1053 if(VAddrRC->getSize() == 8 &&
1054 MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
1055 // We have a MUBUF instruction that uses a 64-bit vaddr register and
1056 // srsrc has the incorrect register class. In order to fix this, we
1057 // need to extract the pointer from the resource descriptor (srsrc),
1058 // add it to the value of vadd, then store the result in the vaddr
1059 // operand. Then, we need to set the pointer field of the resource
1060 // descriptor to zero.
1062 MachineBasicBlock &MBB = *MI->getParent();
1063 MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
1064 MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
1065 unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
1066 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1067 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1068 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1069 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1070 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1071 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1072 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1074 // SRsrcPtrLo = srsrc:sub0
1075 SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
1076 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1078 // SRsrcPtrHi = srsrc:sub1
1079 SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
1080 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1082 // VAddrLo = vaddr:sub0
1083 VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
1084 &AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1086 // VAddrHi = vaddr:sub1
1087 VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
1088 &AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1090 // NewVaddrLo = SRsrcPtrLo + VAddrLo
1091 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1095 .addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
1097 // NewVaddrHi = SRsrcPtrHi + VAddrHi
1098 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1102 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1103 .addReg(AMDGPU::VCC, RegState::Implicit);
1105 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1106 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1109 .addImm(AMDGPU::sub0)
1111 .addImm(AMDGPU::sub1);
1114 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1118 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1119 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1121 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1123 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1124 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1126 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1128 // NewSRsrc = {Zero64, SRsrcFormat}
1129 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1132 .addImm(AMDGPU::sub0_sub1)
1133 .addReg(SRsrcFormatLo)
1134 .addImm(AMDGPU::sub2)
1135 .addReg(SRsrcFormatHi)
1136 .addImm(AMDGPU::sub3);
1138 // Update the instruction to use NewVaddr
1139 MI->getOperand(VAddrIdx).setReg(NewVAddr);
1140 // Update the instruction to use NewSRsrc
1141 MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
1146 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1147 MachineBasicBlock *MBB = MI->getParent();
1148 switch (MI->getOpcode()) {
1149 case AMDGPU::S_LOAD_DWORD_IMM:
1150 case AMDGPU::S_LOAD_DWORD_SGPR:
1151 case AMDGPU::S_LOAD_DWORDX2_IMM:
1152 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1153 case AMDGPU::S_LOAD_DWORDX4_IMM:
1154 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1155 unsigned NewOpcode = getVALUOp(*MI);
1159 if (MI->getOperand(2).isReg()) {
1160 RegOffset = MI->getOperand(2).getReg();
1163 assert(MI->getOperand(2).isImm());
1164 // SMRD instructions take a dword offsets and MUBUF instructions
1165 // take a byte offset.
1166 ImmOffset = MI->getOperand(2).getImm() << 2;
1167 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1168 if (isUInt<12>(ImmOffset)) {
1169 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1173 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1180 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1181 unsigned DWord0 = RegOffset;
1182 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1183 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1184 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1186 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1188 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1189 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1190 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1191 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1192 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1194 .addImm(AMDGPU::sub0)
1196 .addImm(AMDGPU::sub1)
1198 .addImm(AMDGPU::sub2)
1200 .addImm(AMDGPU::sub3);
1201 MI->setDesc(get(NewOpcode));
1202 if (MI->getOperand(2).isReg()) {
1203 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1205 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1207 MI->getOperand(1).setReg(SRsrc);
1208 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1212 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1213 SmallVector<MachineInstr *, 128> Worklist;
1214 Worklist.push_back(&TopInst);
1216 while (!Worklist.empty()) {
1217 MachineInstr *Inst = Worklist.pop_back_val();
1218 MachineBasicBlock *MBB = Inst->getParent();
1219 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1221 unsigned Opcode = Inst->getOpcode();
1222 unsigned NewOpcode = getVALUOp(*Inst);
1224 // Handle some special cases
1227 if (isSMRD(Inst->getOpcode())) {
1228 moveSMRDToVALU(Inst, MRI);
1231 case AMDGPU::S_MOV_B64: {
1232 DebugLoc DL = Inst->getDebugLoc();
1234 // If the source operand is a register we can replace this with a
1236 if (Inst->getOperand(1).isReg()) {
1237 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1238 .addOperand(Inst->getOperand(0))
1239 .addOperand(Inst->getOperand(1));
1240 Worklist.push_back(Copy);
1242 // Otherwise, we need to split this into two movs, because there is
1243 // no 64-bit VALU move instruction.
1244 unsigned Reg = Inst->getOperand(0).getReg();
1245 unsigned Dst = split64BitImm(Worklist,
1248 MRI.getRegClass(Reg),
1249 Inst->getOperand(1));
1250 MRI.replaceRegWith(Reg, Dst);
1252 Inst->eraseFromParent();
1255 case AMDGPU::S_AND_B64:
1256 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1257 Inst->eraseFromParent();
1260 case AMDGPU::S_OR_B64:
1261 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1262 Inst->eraseFromParent();
1265 case AMDGPU::S_XOR_B64:
1266 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1267 Inst->eraseFromParent();
1270 case AMDGPU::S_NOT_B64:
1271 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1272 Inst->eraseFromParent();
1275 case AMDGPU::S_BCNT1_I32_B64:
1276 splitScalar64BitBCNT(Worklist, Inst);
1277 Inst->eraseFromParent();
1280 case AMDGPU::S_BFE_U64:
1281 case AMDGPU::S_BFE_I64:
1282 case AMDGPU::S_BFM_B64:
1283 llvm_unreachable("Moving this op to VALU not implemented");
1286 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1287 // We cannot move this instruction to the VALU, so we should try to
1288 // legalize its operands instead.
1289 legalizeOperands(Inst);
1293 // Use the new VALU Opcode.
1294 const MCInstrDesc &NewDesc = get(NewOpcode);
1295 Inst->setDesc(NewDesc);
1297 // Remove any references to SCC. Vector instructions can't read from it, and
1298 // We're just about to add the implicit use / defs of VCC, and we don't want
1300 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1301 MachineOperand &Op = Inst->getOperand(i);
1302 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1303 Inst->RemoveOperand(i);
1306 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1307 // We are converting these to a BFE, so we need to add the missing
1308 // operands for the size and offset.
1309 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1310 Inst->addOperand(Inst->getOperand(1));
1311 Inst->getOperand(1).ChangeToImmediate(0);
1312 Inst->addOperand(MachineOperand::CreateImm(0));
1313 Inst->addOperand(MachineOperand::CreateImm(0));
1314 Inst->addOperand(MachineOperand::CreateImm(0));
1315 Inst->addOperand(MachineOperand::CreateImm(Size));
1317 // XXX - Other pointless operands. There are 4, but it seems you only need
1318 // 3 to not hit an assertion later in MCInstLower.
1319 Inst->addOperand(MachineOperand::CreateImm(0));
1320 Inst->addOperand(MachineOperand::CreateImm(0));
1321 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1322 // The VALU version adds the second operand to the result, so insert an
1324 Inst->addOperand(MachineOperand::CreateImm(0));
1327 addDescImplicitUseDef(NewDesc, Inst);
1329 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1330 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1331 // If we need to move this to VGPRs, we need to unpack the second operand
1332 // back into the 2 separate ones for bit offset and width.
1333 assert(OffsetWidthOp.isImm() &&
1334 "Scalar BFE is only implemented for constant width and offset");
1335 uint32_t Imm = OffsetWidthOp.getImm();
1337 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1338 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1340 Inst->RemoveOperand(2); // Remove old immediate.
1341 Inst->addOperand(Inst->getOperand(1));
1342 Inst->getOperand(1).ChangeToImmediate(0);
1343 Inst->addOperand(MachineOperand::CreateImm(0));
1344 Inst->addOperand(MachineOperand::CreateImm(Offset));
1345 Inst->addOperand(MachineOperand::CreateImm(0));
1346 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1347 Inst->addOperand(MachineOperand::CreateImm(0));
1348 Inst->addOperand(MachineOperand::CreateImm(0));
1351 // Update the destination register class.
1353 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1356 // For target instructions, getOpRegClass just returns the virtual
1357 // register class associated with the operand, so we need to find an
1358 // equivalent VGPR register class in order to move the instruction to the
1362 case AMDGPU::REG_SEQUENCE:
1363 case AMDGPU::INSERT_SUBREG:
1364 if (RI.hasVGPRs(NewDstRC))
1366 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1374 unsigned DstReg = Inst->getOperand(0).getReg();
1375 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1376 MRI.replaceRegWith(DstReg, NewDstReg);
1378 // Legalize the operands
1379 legalizeOperands(Inst);
1381 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1382 E = MRI.use_end(); I != E; ++I) {
1383 MachineInstr &UseMI = *I->getParent();
1384 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1385 Worklist.push_back(&UseMI);
1391 //===----------------------------------------------------------------------===//
1392 // Indirect addressing callbacks
1393 //===----------------------------------------------------------------------===//
1395 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1396 unsigned Channel) const {
1397 assert(Channel == 0);
1401 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1402 return &AMDGPU::VReg_32RegClass;
1405 void SIInstrInfo::splitScalar64BitUnaryOp(
1406 SmallVectorImpl<MachineInstr *> &Worklist,
1408 unsigned Opcode) const {
1409 MachineBasicBlock &MBB = *Inst->getParent();
1410 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1412 MachineOperand &Dest = Inst->getOperand(0);
1413 MachineOperand &Src0 = Inst->getOperand(1);
1414 DebugLoc DL = Inst->getDebugLoc();
1416 MachineBasicBlock::iterator MII = Inst;
1418 const MCInstrDesc &InstDesc = get(Opcode);
1419 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1420 MRI.getRegClass(Src0.getReg()) :
1421 &AMDGPU::SGPR_32RegClass;
1423 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1425 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1426 AMDGPU::sub0, Src0SubRC);
1428 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1429 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1431 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1432 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1433 .addOperand(SrcReg0Sub0);
1435 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1436 AMDGPU::sub1, Src0SubRC);
1438 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1439 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1440 .addOperand(SrcReg0Sub1);
1442 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1443 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1445 .addImm(AMDGPU::sub0)
1447 .addImm(AMDGPU::sub1);
1449 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1451 // Try to legalize the operands in case we need to swap the order to keep it
1453 Worklist.push_back(LoHalf);
1454 Worklist.push_back(HiHalf);
1457 void SIInstrInfo::splitScalar64BitBinaryOp(
1458 SmallVectorImpl<MachineInstr *> &Worklist,
1460 unsigned Opcode) const {
1461 MachineBasicBlock &MBB = *Inst->getParent();
1462 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1464 MachineOperand &Dest = Inst->getOperand(0);
1465 MachineOperand &Src0 = Inst->getOperand(1);
1466 MachineOperand &Src1 = Inst->getOperand(2);
1467 DebugLoc DL = Inst->getDebugLoc();
1469 MachineBasicBlock::iterator MII = Inst;
1471 const MCInstrDesc &InstDesc = get(Opcode);
1472 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1473 MRI.getRegClass(Src0.getReg()) :
1474 &AMDGPU::SGPR_32RegClass;
1476 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1477 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1478 MRI.getRegClass(Src1.getReg()) :
1479 &AMDGPU::SGPR_32RegClass;
1481 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1483 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1484 AMDGPU::sub0, Src0SubRC);
1485 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1486 AMDGPU::sub0, Src1SubRC);
1488 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1489 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1491 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1492 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1493 .addOperand(SrcReg0Sub0)
1494 .addOperand(SrcReg1Sub0);
1496 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1497 AMDGPU::sub1, Src0SubRC);
1498 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1499 AMDGPU::sub1, Src1SubRC);
1501 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1502 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1503 .addOperand(SrcReg0Sub1)
1504 .addOperand(SrcReg1Sub1);
1506 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1507 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1509 .addImm(AMDGPU::sub0)
1511 .addImm(AMDGPU::sub1);
1513 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1515 // Try to legalize the operands in case we need to swap the order to keep it
1517 Worklist.push_back(LoHalf);
1518 Worklist.push_back(HiHalf);
1521 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
1522 MachineInstr *Inst) const {
1523 MachineBasicBlock &MBB = *Inst->getParent();
1524 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1526 MachineBasicBlock::iterator MII = Inst;
1527 DebugLoc DL = Inst->getDebugLoc();
1529 MachineOperand &Dest = Inst->getOperand(0);
1530 MachineOperand &Src = Inst->getOperand(1);
1532 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
1533 const TargetRegisterClass *SrcRC = Src.isReg() ?
1534 MRI.getRegClass(Src.getReg()) :
1535 &AMDGPU::SGPR_32RegClass;
1537 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1538 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1540 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
1542 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1543 AMDGPU::sub0, SrcSubRC);
1544 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1545 AMDGPU::sub1, SrcSubRC);
1547 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
1548 .addOperand(SrcRegSub0)
1551 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
1552 .addOperand(SrcRegSub1)
1555 MRI.replaceRegWith(Dest.getReg(), ResultReg);
1557 Worklist.push_back(First);
1558 Worklist.push_back(Second);
1561 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1562 MachineInstr *Inst) const {
1563 // Add the implict and explicit register definitions.
1564 if (NewDesc.ImplicitUses) {
1565 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
1566 unsigned Reg = NewDesc.ImplicitUses[i];
1567 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
1571 if (NewDesc.ImplicitDefs) {
1572 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1573 unsigned Reg = NewDesc.ImplicitDefs[i];
1574 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
1579 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1580 MachineBasicBlock *MBB,
1581 MachineBasicBlock::iterator I,
1583 unsigned Address, unsigned OffsetReg) const {
1584 const DebugLoc &DL = MBB->findDebugLoc(I);
1585 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1586 getIndirectIndexBegin(*MBB->getParent()));
1588 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1589 .addReg(IndirectBaseReg, RegState::Define)
1590 .addOperand(I->getOperand(0))
1591 .addReg(IndirectBaseReg)
1597 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1598 MachineBasicBlock *MBB,
1599 MachineBasicBlock::iterator I,
1601 unsigned Address, unsigned OffsetReg) const {
1602 const DebugLoc &DL = MBB->findDebugLoc(I);
1603 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1604 getIndirectIndexBegin(*MBB->getParent()));
1606 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1607 .addOperand(I->getOperand(0))
1608 .addOperand(I->getOperand(1))
1609 .addReg(IndirectBaseReg)
1615 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1616 const MachineFunction &MF) const {
1617 int End = getIndirectIndexEnd(MF);
1618 int Begin = getIndirectIndexBegin(MF);
1624 for (int Index = Begin; Index <= End; ++Index)
1625 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1627 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1628 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1630 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1631 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1633 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1634 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1636 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1637 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1639 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1640 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
1643 const MachineOperand *SIInstrInfo::getNamedOperand(const MachineInstr& MI,
1644 unsigned OperandName) const {
1645 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
1649 return &MI.getOperand(Idx);