1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
43 MachineBasicBlock::iterator MI,
44 MachineRegisterInfo &MRI,
45 const TargetRegisterClass *RC,
46 const MachineOperand &Op) const;
48 void swapOperands(MachineBasicBlock::iterator Inst) const;
50 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst, unsigned Opcode) const;
56 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57 MachineInstr *Inst) const;
58 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59 MachineInstr *Inst) const;
61 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
63 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
64 MachineInstr *MIb) const;
66 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
69 explicit SIInstrInfo(const AMDGPUSubtarget &st);
71 const SIRegisterInfo &getRegisterInfo() const override {
75 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
77 int64_t &Offset2) const override;
79 bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
80 unsigned &BaseReg, unsigned &Offset,
81 const TargetRegisterInfo *TRI) const final;
83 bool shouldClusterLoads(MachineInstr *FirstLdSt,
84 MachineInstr *SecondLdSt,
85 unsigned NumLoads) const final;
87 void copyPhysReg(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MI, DebugLoc DL,
89 unsigned DestReg, unsigned SrcReg,
90 bool KillSrc) const override;
92 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MI,
99 void storeRegToStackSlot(MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator MI,
101 unsigned SrcReg, bool isKill, int FrameIndex,
102 const TargetRegisterClass *RC,
103 const TargetRegisterInfo *TRI) const override;
105 void loadRegFromStackSlot(MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator MI,
107 unsigned DestReg, int FrameIndex,
108 const TargetRegisterClass *RC,
109 const TargetRegisterInfo *TRI) const override;
111 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
113 // \brief Returns an opcode that can be used to move a value to a \p DstRC
114 // register. If there is no hardware instruction that can store to \p
115 // DstRC, then AMDGPU::COPY is returned.
116 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
117 unsigned commuteOpcode(unsigned Opcode) const;
119 MachineInstr *commuteInstruction(MachineInstr *MI,
120 bool NewMI = false) const override;
121 bool findCommutedOpIndices(MachineInstr *MI,
123 unsigned &SrcOpIdx2) const override;
125 bool isTriviallyReMaterializable(const MachineInstr *MI,
126 AliasAnalysis *AA = nullptr) const;
128 bool areMemAccessesTriviallyDisjoint(
129 MachineInstr *MIa, MachineInstr *MIb,
130 AliasAnalysis *AA = nullptr) const override;
132 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
133 MachineBasicBlock::iterator I,
134 unsigned DstReg, unsigned SrcReg) const override;
135 bool isMov(unsigned Opcode) const override;
137 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
139 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
140 unsigned Reg, MachineRegisterInfo *MRI) const final;
142 bool isSALU(uint16_t Opcode) const {
143 return get(Opcode).TSFlags & SIInstrFlags::SALU;
146 bool isVALU(uint16_t Opcode) const {
147 return get(Opcode).TSFlags & SIInstrFlags::VALU;
150 bool isSOP1(uint16_t Opcode) const {
151 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
154 bool isSOP2(uint16_t Opcode) const {
155 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
158 bool isSOPC(uint16_t Opcode) const {
159 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
162 bool isSOPK(uint16_t Opcode) const {
163 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
166 bool isSOPP(uint16_t Opcode) const {
167 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
170 bool isVOP1(uint16_t Opcode) const {
171 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
174 bool isVOP2(uint16_t Opcode) const {
175 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
178 bool isVOP3(uint16_t Opcode) const {
179 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
182 bool isVOPC(uint16_t Opcode) const {
183 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
186 bool isMUBUF(uint16_t Opcode) const {
187 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
190 bool isMTBUF(uint16_t Opcode) const {
191 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
194 bool isSMRD(uint16_t Opcode) const {
195 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
198 bool isDS(uint16_t Opcode) const {
199 return get(Opcode).TSFlags & SIInstrFlags::DS;
202 bool isMIMG(uint16_t Opcode) const {
203 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
206 bool isFLAT(uint16_t Opcode) const {
207 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
210 bool isWQM(uint16_t Opcode) const {
211 return get(Opcode).TSFlags & SIInstrFlags::WQM;
214 bool isInlineConstant(const APInt &Imm) const;
215 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
216 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
218 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
219 const MachineOperand &MO) const;
221 /// \brief Return true if the given offset Size in bytes can be folded into
222 /// the immediate offsets of a memory instruction for the given address space.
223 bool canFoldOffset(unsigned OffsetSize, unsigned AS) const;
225 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
226 /// This function will return false if you pass it a 32-bit instruction.
227 bool hasVALU32BitEncoding(unsigned Opcode) const;
229 /// \brief Returns true if this operand uses the constant bus.
230 bool usesConstantBus(const MachineRegisterInfo &MRI,
231 const MachineOperand &MO,
232 unsigned OpSize) const;
234 /// \brief Return true if this instruction has any modifiers.
235 /// e.g. src[012]_mod, omod, clamp.
236 bool hasModifiers(unsigned Opcode) const;
238 bool hasModifiersSet(const MachineInstr &MI,
239 unsigned OpName) const;
241 bool verifyInstruction(const MachineInstr *MI,
242 StringRef &ErrInfo) const override;
244 static unsigned getVALUOp(const MachineInstr &MI);
246 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
248 /// \brief Return the correct register class for \p OpNo. For target-specific
249 /// instructions, this will return the register class that has been defined
250 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
251 /// the register class of its machine operand.
252 /// to infer the correct register class base on the other operands.
253 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
254 unsigned OpNo) const;
256 /// \brief Return the size in bytes of the operand OpNo on the given
257 // instruction opcode.
258 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
259 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
261 if (OpInfo.RegClass == -1) {
262 // If this is an immediate operand, this must be a 32-bit literal.
263 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
267 return RI.getRegClass(OpInfo.RegClass)->getSize();
270 /// \brief This form should usually be preferred since it handles operands
271 /// with unknown register classes.
272 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
273 return getOpRegClass(MI, OpNo)->getSize();
276 /// \returns true if it is legal for the operand at index \p OpNo
278 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
280 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
281 /// a MOV. For example:
282 /// ADD_I32_e32 VGPR0, 15
285 /// ADD_I32_e32 VGPR0, VGPR1
287 /// If the operand being legalized is a register, then a COPY will be used
289 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
291 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
293 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
294 const MachineOperand *MO = nullptr) const;
296 /// \brief Legalize all operands in this instruction. This function may
297 /// create new instruction and insert them before \p MI.
298 void legalizeOperands(MachineInstr *MI) const;
300 /// \brief Split an SMRD instruction into two smaller loads of half the
301 // size storing the results in \p Lo and \p Hi.
302 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
303 unsigned HalfImmOp, unsigned HalfSGPROp,
304 MachineInstr *&Lo, MachineInstr *&Hi) const;
306 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
308 /// \brief Replace this instruction's opcode with the equivalent VALU
309 /// opcode. This function will also move the users of \p MI to the
310 /// VALU if necessary.
311 void moveToVALU(MachineInstr &MI) const;
313 unsigned calculateIndirectAddress(unsigned RegIndex,
314 unsigned Channel) const override;
316 const TargetRegisterClass *getIndirectAddrRegClass() const override;
318 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
319 MachineBasicBlock::iterator I,
322 unsigned OffsetReg) const override;
324 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
325 MachineBasicBlock::iterator I,
328 unsigned OffsetReg) const override;
329 void reserveIndirectRegisters(BitVector &Reserved,
330 const MachineFunction &MF) const;
332 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
333 unsigned SavReg, unsigned IndexReg) const;
335 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
337 /// \brief Returns the operand named \p Op. If \p MI does not have an
338 /// operand named \c Op, this function returns nullptr.
339 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
341 const MachineOperand *getNamedOperand(const MachineInstr &MI,
342 unsigned OpName) const {
343 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
346 uint64_t getDefaultRsrcDataFormat() const;
352 int getVOPe64(uint16_t Opcode);
353 int getVOPe32(uint16_t Opcode);
354 int getCommuteRev(uint16_t Opcode);
355 int getCommuteOrig(uint16_t Opcode);
356 int getAddr64Inst(uint16_t Opcode);
357 int getAtomicRetOp(uint16_t Opcode);
358 int getAtomicNoRetOp(uint16_t Opcode);
360 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
361 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
363 } // End namespace AMDGPU
366 namespace KernelInputOffsets {
368 /// Offsets in bytes from the start of the input buffer
381 } // End namespace KernelInputOffsets
382 } // End namespace SI
384 } // End namespace llvm