1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 MachineInstrBuilder buildIndirectIndexLoop(MachineBasicBlock &MBB,
29 MachineBasicBlock::iterator I,
34 // If you add or remove instructions from this function, you will
37 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
39 const SIRegisterInfo &getRegisterInfo() const;
41 virtual void copyPhysReg(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MI, DebugLoc DL,
43 unsigned DestReg, unsigned SrcReg,
46 void storeRegToStackSlot(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MI,
48 unsigned SrcReg, bool isKill, int FrameIndex,
49 const TargetRegisterClass *RC,
50 const TargetRegisterInfo *TRI) const;
52 void loadRegFromStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MI,
54 unsigned DestReg, int FrameIndex,
55 const TargetRegisterClass *RC,
56 const TargetRegisterInfo *TRI) const;
58 unsigned commuteOpcode(unsigned Opcode) const;
60 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
61 bool NewMI=false) const;
63 virtual unsigned getIEQOpcode() const {
64 llvm_unreachable("Unimplemented");
67 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
68 MachineBasicBlock::iterator I,
69 unsigned DstReg, unsigned SrcReg) const;
70 virtual bool isMov(unsigned Opcode) const;
72 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
73 int isMIMG(uint16_t Opcode) const;
74 int isSMRD(uint16_t Opcode) const;
75 bool isVOP1(uint16_t Opcode) const;
76 bool isVOP2(uint16_t Opcode) const;
77 bool isVOP3(uint16_t Opcode) const;
78 bool isVOPC(uint16_t Opcode) const;
79 bool isInlineConstant(const MachineOperand &MO) const;
80 bool isLiteralConstant(const MachineOperand &MO) const;
82 virtual bool verifyInstruction(const MachineInstr *MI,
83 StringRef &ErrInfo) const;
85 bool isSALUInstr(const MachineInstr &MI) const;
86 static unsigned getVALUOp(const MachineInstr &MI);
87 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
89 /// \brief Return the correct register class for \p OpNo. For target-specific
90 /// instructions, this will return the register class that has been defined
91 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
92 /// the register class of its machine operand.
93 /// to infer the correct register class base on the other operands.
94 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
95 unsigned OpNo) const;\
97 /// \returns true if it is legal for the operand at index \p OpNo
99 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
101 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
102 /// a MOV. For example:
103 /// ADD_I32_e32 VGPR0, 15
106 /// ADD_I32_e32 VGPR0, VGPR1
108 /// If the operand being legalized is a register, then a COPY will be used
110 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
112 /// \brief Legalize all operands in this instruction. This function may
113 /// create new instruction and insert them before \p MI.
114 void legalizeOperands(MachineInstr *MI) const;
116 /// \brief Replace this instruction's opcode with the equivalent VALU
117 /// opcode. This function will also move the users of \p MI to the
118 /// VALU if necessary.
119 void moveToVALU(MachineInstr &MI) const;
121 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
122 unsigned Channel) const;
124 virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
126 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
127 MachineBasicBlock::iterator I,
130 unsigned OffsetReg) const;
132 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
133 MachineBasicBlock::iterator I,
136 unsigned OffsetReg) const;
137 void reserveIndirectRegisters(BitVector &Reserved,
138 const MachineFunction &MF) const;
140 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
141 unsigned SavReg, unsigned IndexReg) const;
146 int getVOPe64(uint16_t Opcode);
147 int getCommuteRev(uint16_t Opcode);
148 int getCommuteOrig(uint16_t Opcode);
150 } // End namespace AMDGPU
152 } // End namespace llvm
154 namespace SIInstrFlags {
156 // First 4 bits are the instruction encoding
163 #endif //SIINSTRINFO_H