1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
29 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
31 const SIRegisterInfo &getRegisterInfo() const;
33 virtual void copyPhysReg(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MI, DebugLoc DL,
35 unsigned DestReg, unsigned SrcReg,
38 unsigned commuteOpcode(unsigned Opcode) const;
40 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
41 bool NewMI=false) const;
43 virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
44 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
45 MachineBasicBlock::iterator I,
46 unsigned DstReg, unsigned SrcReg) const;
47 virtual bool isMov(unsigned Opcode) const;
49 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
50 int isMIMG(uint16_t Opcode) const;
51 int isSMRD(uint16_t Opcode) const;
52 bool isVOP1(uint16_t Opcode) const;
53 bool isVOP2(uint16_t Opcode) const;
54 bool isVOP3(uint16_t Opcode) const;
55 bool isVOPC(uint16_t Opcode) const;
56 bool isInlineConstant(const MachineOperand &MO) const;
57 bool isLiteralConstant(const MachineOperand &MO) const;
59 virtual bool verifyInstruction(const MachineInstr *MI,
60 StringRef &ErrInfo) const;
61 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
63 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
65 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
66 unsigned Channel) const;
68 virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
70 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
71 MachineBasicBlock::iterator I,
74 unsigned OffsetReg) const;
76 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
77 MachineBasicBlock::iterator I,
80 unsigned OffsetReg) const;
85 int getVOPe64(uint16_t Opcode);
86 int getCommuteRev(uint16_t Opcode);
87 int getCommuteOrig(uint16_t Opcode);
89 } // End namespace AMDGPU
91 } // End namespace llvm
93 namespace SIInstrFlags {
95 // First 4 bits are the instruction encoding
102 #endif //SIINSTRINFO_H