lib/Target/R600/SIInstrInfo.h

   1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief Interface definition for SIInstrInfo.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15
  16 #ifndef SIINSTRINFO_H
  17 #define SIINSTRINFO_H
  18
  19 #include "AMDGPUInstrInfo.h"
  20 #include "SIRegisterInfo.h"
  21
  22 namespace llvm {
  23
  24 class SIInstrInfo : public AMDGPUInstrInfo {
  25 private:
  26   const SIRegisterInfo RI;
  27
  28 public:
  29   explicit SIInstrInfo(AMDGPUTargetMachine &tm);
  30
  31   const SIRegisterInfo &getRegisterInfo() const;
  32
  33   virtual void copyPhysReg(MachineBasicBlock &MBB,
  34                            MachineBasicBlock::iterator MI, DebugLoc DL,
  35                            unsigned DestReg, unsigned SrcReg,
  36                            bool KillSrc) const;
  37
  38   unsigned commuteOpcode(unsigned Opcode) const;
  39
  40   virtual MachineInstr *commuteInstruction(MachineInstr *MI,
  41                                            bool NewMI=false) const;
  42
  43   virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
  44   MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
  45                               MachineBasicBlock::iterator I,
  46                               unsigned DstReg, unsigned SrcReg) const;
  47   virtual bool isMov(unsigned Opcode) const;
  48
  49   virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
  50   int isMIMG(uint16_t Opcode) const;
  51   int isSMRD(uint16_t Opcode) const;
  52   bool isVOP1(uint16_t Opcode) const;
  53   bool isVOP2(uint16_t Opcode) const;
  54   bool isVOP3(uint16_t Opcode) const;
  55   bool isVOPC(uint16_t Opcode) const;
  56   bool isInlineConstant(const MachineOperand &MO) const;
  57   bool isLiteralConstant(const MachineOperand &MO) const;
  58
  59   virtual bool verifyInstruction(const MachineInstr *MI,
  60                                  StringRef &ErrInfo) const;
  61   virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
  62
  63   virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
  64
  65   virtual unsigned calculateIndirectAddress(unsigned RegIndex,
  66                                             unsigned Channel) const;
  67
  68   virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
  69
  70   virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
  71                                                  MachineBasicBlock::iterator I,
  72                                                  unsigned ValueReg,
  73                                                  unsigned Address,
  74                                                  unsigned OffsetReg) const;
  75
  76   virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
  77                                                 MachineBasicBlock::iterator I,
  78                                                 unsigned ValueReg,
  79                                                 unsigned Address,
  80                                                 unsigned OffsetReg) const;
  81   };
  82
  83 namespace AMDGPU {
  84
  85   int getVOPe64(uint16_t Opcode);
  86   int getCommuteRev(uint16_t Opcode);
  87   int getCommuteOrig(uint16_t Opcode);
  88
  89 } // End namespace AMDGPU
  90
  91 } // End namespace llvm
  92
  93 namespace SIInstrFlags {
  94   enum Flags {
  95     // First 4 bits are the instruction encoding
  96     VM_CNT = 1 << 0,
  97     EXP_CNT = 1 << 1,
  98     LGKM_CNT = 1 << 2
  99   };
 100 }
 101
 102 #endif //SIINSTRINFO_H