1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35 MachineRegisterInfo &MRI,
36 MachineOperand &SuperReg,
37 const TargetRegisterClass *SuperRC,
39 const TargetRegisterClass *SubRC) const;
41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42 MachineBasicBlock::iterator MI,
43 MachineRegisterInfo &MRI,
44 const TargetRegisterClass *RC,
45 const MachineOperand &Op) const;
47 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst) const;
56 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
58 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
61 explicit SIInstrInfo(const AMDGPUSubtarget &st);
63 const SIRegisterInfo &getRegisterInfo() const override {
67 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
69 int64_t &Offset2) const override;
71 bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
72 unsigned &BaseReg, unsigned &Offset,
73 const TargetRegisterInfo *TRI) const final;
75 bool shouldClusterLoads(MachineInstr *FirstLdSt,
76 MachineInstr *SecondLdSt,
77 unsigned NumLoads) const final;
79 void copyPhysReg(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MI, DebugLoc DL,
81 unsigned DestReg, unsigned SrcReg,
82 bool KillSrc) const override;
84 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MI,
91 void storeRegToStackSlot(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 unsigned SrcReg, bool isKill, int FrameIndex,
94 const TargetRegisterClass *RC,
95 const TargetRegisterInfo *TRI) const override;
97 void loadRegFromStackSlot(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 unsigned DestReg, int FrameIndex,
100 const TargetRegisterClass *RC,
101 const TargetRegisterInfo *TRI) const override;
103 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
105 unsigned commuteOpcode(unsigned Opcode) const;
107 MachineInstr *commuteInstruction(MachineInstr *MI,
108 bool NewMI = false) const override;
109 bool findCommutedOpIndices(MachineInstr *MI,
111 unsigned &SrcOpIdx2) const override;
113 bool isTriviallyReMaterializable(const MachineInstr *MI,
114 AliasAnalysis *AA = nullptr) const;
116 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
117 MachineBasicBlock::iterator I,
118 unsigned DstReg, unsigned SrcReg) const override;
119 bool isMov(unsigned Opcode) const override;
121 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
122 bool isDS(uint16_t Opcode) const;
123 bool isMIMG(uint16_t Opcode) const;
124 bool isSMRD(uint16_t Opcode) const;
125 bool isMUBUF(uint16_t Opcode) const;
126 bool isMTBUF(uint16_t Opcode) const;
127 bool isFLAT(uint16_t Opcode) const;
128 bool isVOP1(uint16_t Opcode) const;
129 bool isVOP2(uint16_t Opcode) const;
130 bool isVOP3(uint16_t Opcode) const;
131 bool isVOPC(uint16_t Opcode) const;
132 bool isInlineConstant(const APInt &Imm) const;
133 bool isInlineConstant(const MachineOperand &MO) const;
134 bool isLiteralConstant(const MachineOperand &MO) const;
136 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
137 const MachineOperand &MO) const;
139 /// \brief Return true if the given offset Size in bytes can be folded into
140 /// the immediate offsets of a memory instruction for the given address space.
141 static bool canFoldOffset(unsigned OffsetSize, unsigned AS) LLVM_READNONE;
143 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
144 /// This function will return false if you pass it a 32-bit instruction.
145 bool hasVALU32BitEncoding(unsigned Opcode) const;
147 /// \brief Returns true if this operand uses the constant bus.
148 bool usesConstantBus(const MachineRegisterInfo &MRI,
149 const MachineOperand &MO) const;
151 /// \brief Return true if this instruction has any modifiers.
152 /// e.g. src[012]_mod, omod, clamp.
153 bool hasModifiers(unsigned Opcode) const;
154 bool verifyInstruction(const MachineInstr *MI,
155 StringRef &ErrInfo) const override;
157 bool isSALUInstr(const MachineInstr &MI) const;
158 static unsigned getVALUOp(const MachineInstr &MI);
160 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
162 /// \brief Return the correct register class for \p OpNo. For target-specific
163 /// instructions, this will return the register class that has been defined
164 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
165 /// the register class of its machine operand.
166 /// to infer the correct register class base on the other operands.
167 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
168 unsigned OpNo) const;\
170 /// \returns true if it is legal for the operand at index \p OpNo
172 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
174 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
175 /// a MOV. For example:
176 /// ADD_I32_e32 VGPR0, 15
179 /// ADD_I32_e32 VGPR0, VGPR1
181 /// If the operand being legalized is a register, then a COPY will be used
183 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
185 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
187 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
188 const MachineOperand *MO = nullptr) const;
190 /// \brief Legalize all operands in this instruction. This function may
191 /// create new instruction and insert them before \p MI.
192 void legalizeOperands(MachineInstr *MI) const;
194 /// \brief Split an SMRD instruction into two smaller loads of half the
195 // size storing the results in \p Lo and \p Hi.
196 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
197 unsigned HalfImmOp, unsigned HalfSGPROp,
198 MachineInstr *&Lo, MachineInstr *&Hi) const;
200 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
202 /// \brief Replace this instruction's opcode with the equivalent VALU
203 /// opcode. This function will also move the users of \p MI to the
204 /// VALU if necessary.
205 void moveToVALU(MachineInstr &MI) const;
207 unsigned calculateIndirectAddress(unsigned RegIndex,
208 unsigned Channel) const override;
210 const TargetRegisterClass *getIndirectAddrRegClass() const override;
212 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
213 MachineBasicBlock::iterator I,
216 unsigned OffsetReg) const override;
218 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
219 MachineBasicBlock::iterator I,
222 unsigned OffsetReg) const override;
223 void reserveIndirectRegisters(BitVector &Reserved,
224 const MachineFunction &MF) const;
226 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
227 unsigned SavReg, unsigned IndexReg) const;
229 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
231 /// \brief Returns the operand named \p Op. If \p MI does not have an
232 /// operand named \c Op, this function returns nullptr.
233 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
238 int getVOPe64(uint16_t Opcode);
239 int getVOPe32(uint16_t Opcode);
240 int getCommuteRev(uint16_t Opcode);
241 int getCommuteOrig(uint16_t Opcode);
242 int getMCOpcode(uint16_t Opcode, unsigned Gen);
243 int getAddr64Inst(uint16_t Opcode);
244 int getAtomicRetOp(uint16_t Opcode);
245 int getAtomicNoRetOp(uint16_t Opcode);
247 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
248 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
250 } // End namespace AMDGPU
253 namespace KernelInputOffsets {
255 /// Offsets in bytes from the start of the input buffer
268 } // End namespace KernelInputOffsets
269 } // End namespace SI
271 } // End namespace llvm
273 namespace SIInstrFlags {
275 // First 4 bits are the instruction encoding
282 namespace SISrcMods {