1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35 MachineRegisterInfo &MRI,
36 MachineOperand &SuperReg,
37 const TargetRegisterClass *SuperRC,
39 const TargetRegisterClass *SubRC) const;
41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42 MachineBasicBlock::iterator MI,
43 MachineRegisterInfo &MRI,
44 const TargetRegisterClass *RC,
45 const MachineOperand &Op) const;
47 void splitScalar64BitOp(SmallVectorImpl<MachineInstr *> & Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
53 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
55 const SIRegisterInfo &getRegisterInfo() const override {
59 void copyPhysReg(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MI, DebugLoc DL,
61 unsigned DestReg, unsigned SrcReg,
62 bool KillSrc) const override;
64 void storeRegToStackSlot(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned SrcReg, bool isKill, int FrameIndex,
67 const TargetRegisterClass *RC,
68 const TargetRegisterInfo *TRI) const override;
70 void loadRegFromStackSlot(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator MI,
72 unsigned DestReg, int FrameIndex,
73 const TargetRegisterClass *RC,
74 const TargetRegisterInfo *TRI) const override;
76 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
78 unsigned commuteOpcode(unsigned Opcode) const;
80 MachineInstr *commuteInstruction(MachineInstr *MI,
81 bool NewMI=false) const override;
83 bool isTriviallyReMaterializable(const MachineInstr *MI,
84 AliasAnalysis *AA = nullptr) const;
86 unsigned getIEQOpcode() const override {
87 llvm_unreachable("Unimplemented");
90 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
91 MachineBasicBlock::iterator I,
92 unsigned DstReg, unsigned SrcReg) const override;
93 bool isMov(unsigned Opcode) const override;
95 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
96 bool isDS(uint16_t Opcode) const;
97 int isMIMG(uint16_t Opcode) const;
98 int isSMRD(uint16_t Opcode) const;
99 bool isVOP1(uint16_t Opcode) const;
100 bool isVOP2(uint16_t Opcode) const;
101 bool isVOP3(uint16_t Opcode) const;
102 bool isVOPC(uint16_t Opcode) const;
103 bool isInlineConstant(const APInt &Imm) const;
104 bool isInlineConstant(const MachineOperand &MO) const;
105 bool isLiteralConstant(const MachineOperand &MO) const;
107 bool verifyInstruction(const MachineInstr *MI,
108 StringRef &ErrInfo) const override;
110 bool isSALUInstr(const MachineInstr &MI) const;
111 static unsigned getVALUOp(const MachineInstr &MI);
113 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
115 /// \brief Return the correct register class for \p OpNo. For target-specific
116 /// instructions, this will return the register class that has been defined
117 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
118 /// the register class of its machine operand.
119 /// to infer the correct register class base on the other operands.
120 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
121 unsigned OpNo) const;\
123 /// \returns true if it is legal for the operand at index \p OpNo
125 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
127 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
128 /// a MOV. For example:
129 /// ADD_I32_e32 VGPR0, 15
132 /// ADD_I32_e32 VGPR0, VGPR1
134 /// If the operand being legalized is a register, then a COPY will be used
136 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
138 /// \brief Legalize all operands in this instruction. This function may
139 /// create new instruction and insert them before \p MI.
140 void legalizeOperands(MachineInstr *MI) const;
142 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
144 /// \brief Replace this instruction's opcode with the equivalent VALU
145 /// opcode. This function will also move the users of \p MI to the
146 /// VALU if necessary.
147 void moveToVALU(MachineInstr &MI) const;
149 unsigned calculateIndirectAddress(unsigned RegIndex,
150 unsigned Channel) const override;
152 const TargetRegisterClass *getIndirectAddrRegClass() const override;
154 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
155 MachineBasicBlock::iterator I,
158 unsigned OffsetReg) const override;
160 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
161 MachineBasicBlock::iterator I,
164 unsigned OffsetReg) const override;
165 void reserveIndirectRegisters(BitVector &Reserved,
166 const MachineFunction &MF) const;
168 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
169 unsigned SavReg, unsigned IndexReg) const;
171 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
176 int getVOPe64(uint16_t Opcode);
177 int getCommuteRev(uint16_t Opcode);
178 int getCommuteOrig(uint16_t Opcode);
179 int getMCOpcode(uint16_t Opcode, unsigned Gen);
181 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
184 } // End namespace AMDGPU
186 } // End namespace llvm
188 namespace SIInstrFlags {
190 // First 4 bits are the instruction encoding
197 #endif //SIINSTRINFO_H