1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
43 MachineBasicBlock::iterator MI,
44 MachineRegisterInfo &MRI,
45 const TargetRegisterClass *RC,
46 const MachineOperand &Op) const;
48 void swapOperands(MachineBasicBlock::iterator Inst) const;
50 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst, unsigned Opcode) const;
56 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57 MachineInstr *Inst) const;
58 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59 MachineInstr *Inst) const;
61 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
63 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
64 MachineInstr *MIb) const;
66 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
69 explicit SIInstrInfo(const AMDGPUSubtarget &st);
71 const SIRegisterInfo &getRegisterInfo() const override {
75 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
76 AliasAnalysis *AA) const override;
78 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
80 int64_t &Offset2) const override;
82 bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
83 unsigned &BaseReg, unsigned &Offset,
84 const TargetRegisterInfo *TRI) const final;
86 bool shouldClusterLoads(MachineInstr *FirstLdSt,
87 MachineInstr *SecondLdSt,
88 unsigned NumLoads) const final;
90 void copyPhysReg(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MI, DebugLoc DL,
92 unsigned DestReg, unsigned SrcReg,
93 bool KillSrc) const override;
95 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MI,
100 unsigned Size) const;
102 void storeRegToStackSlot(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator MI,
104 unsigned SrcReg, bool isKill, int FrameIndex,
105 const TargetRegisterClass *RC,
106 const TargetRegisterInfo *TRI) const override;
108 void loadRegFromStackSlot(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MI,
110 unsigned DestReg, int FrameIndex,
111 const TargetRegisterClass *RC,
112 const TargetRegisterInfo *TRI) const override;
114 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
116 // \brief Returns an opcode that can be used to move a value to a \p DstRC
117 // register. If there is no hardware instruction that can store to \p
118 // DstRC, then AMDGPU::COPY is returned.
119 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
120 unsigned commuteOpcode(const MachineInstr &MI) const;
122 MachineInstr *commuteInstruction(MachineInstr *MI,
123 bool NewMI = false) const override;
124 bool findCommutedOpIndices(MachineInstr *MI,
126 unsigned &SrcOpIdx2) const override;
128 bool isTriviallyReMaterializable(const MachineInstr *MI,
129 AliasAnalysis *AA = nullptr) const;
131 bool areMemAccessesTriviallyDisjoint(
132 MachineInstr *MIa, MachineInstr *MIb,
133 AliasAnalysis *AA = nullptr) const override;
135 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
136 MachineBasicBlock::iterator I,
137 unsigned DstReg, unsigned SrcReg) const override;
138 bool isMov(unsigned Opcode) const override;
140 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
142 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
143 unsigned Reg, MachineRegisterInfo *MRI) const final;
145 bool isSALU(uint16_t Opcode) const {
146 return get(Opcode).TSFlags & SIInstrFlags::SALU;
149 bool isVALU(uint16_t Opcode) const {
150 return get(Opcode).TSFlags & SIInstrFlags::VALU;
153 bool isSOP1(uint16_t Opcode) const {
154 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
157 bool isSOP2(uint16_t Opcode) const {
158 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
161 bool isSOPC(uint16_t Opcode) const {
162 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
165 bool isSOPK(uint16_t Opcode) const {
166 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
169 bool isSOPP(uint16_t Opcode) const {
170 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
173 bool isVOP1(uint16_t Opcode) const {
174 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
177 bool isVOP2(uint16_t Opcode) const {
178 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
181 bool isVOP3(uint16_t Opcode) const {
182 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
185 bool isVOPC(uint16_t Opcode) const {
186 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
189 bool isMUBUF(uint16_t Opcode) const {
190 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
193 bool isMTBUF(uint16_t Opcode) const {
194 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
197 bool isSMRD(uint16_t Opcode) const {
198 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
201 bool isDS(uint16_t Opcode) const {
202 return get(Opcode).TSFlags & SIInstrFlags::DS;
205 bool isMIMG(uint16_t Opcode) const {
206 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
209 bool isFLAT(uint16_t Opcode) const {
210 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
213 bool isWQM(uint16_t Opcode) const {
214 return get(Opcode).TSFlags & SIInstrFlags::WQM;
217 bool isInlineConstant(const APInt &Imm) const;
218 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
219 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
221 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
222 const MachineOperand &MO) const;
224 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
225 /// This function will return false if you pass it a 32-bit instruction.
226 bool hasVALU32BitEncoding(unsigned Opcode) const;
228 /// \brief Returns true if this operand uses the constant bus.
229 bool usesConstantBus(const MachineRegisterInfo &MRI,
230 const MachineOperand &MO,
231 unsigned OpSize) const;
233 /// \brief Return true if this instruction has any modifiers.
234 /// e.g. src[012]_mod, omod, clamp.
235 bool hasModifiers(unsigned Opcode) const;
237 bool hasModifiersSet(const MachineInstr &MI,
238 unsigned OpName) const;
240 bool verifyInstruction(const MachineInstr *MI,
241 StringRef &ErrInfo) const override;
243 static unsigned getVALUOp(const MachineInstr &MI);
245 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
247 /// \brief Return the correct register class for \p OpNo. For target-specific
248 /// instructions, this will return the register class that has been defined
249 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
250 /// the register class of its machine operand.
251 /// to infer the correct register class base on the other operands.
252 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
253 unsigned OpNo) const;
255 /// \brief Return the size in bytes of the operand OpNo on the given
256 // instruction opcode.
257 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
258 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
260 if (OpInfo.RegClass == -1) {
261 // If this is an immediate operand, this must be a 32-bit literal.
262 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
266 return RI.getRegClass(OpInfo.RegClass)->getSize();
269 /// \brief This form should usually be preferred since it handles operands
270 /// with unknown register classes.
271 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
272 return getOpRegClass(MI, OpNo)->getSize();
275 /// \returns true if it is legal for the operand at index \p OpNo
277 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
279 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
280 /// a MOV. For example:
281 /// ADD_I32_e32 VGPR0, 15
284 /// ADD_I32_e32 VGPR0, VGPR1
286 /// If the operand being legalized is a register, then a COPY will be used
288 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
290 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
292 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
293 const MachineOperand *MO = nullptr) const;
295 /// \brief Legalize all operands in this instruction. This function may
296 /// create new instruction and insert them before \p MI.
297 void legalizeOperands(MachineInstr *MI) const;
299 /// \brief Split an SMRD instruction into two smaller loads of half the
300 // size storing the results in \p Lo and \p Hi.
301 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
302 unsigned HalfImmOp, unsigned HalfSGPROp,
303 MachineInstr *&Lo, MachineInstr *&Hi) const;
305 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
307 /// \brief Replace this instruction's opcode with the equivalent VALU
308 /// opcode. This function will also move the users of \p MI to the
309 /// VALU if necessary.
310 void moveToVALU(MachineInstr &MI) const;
312 unsigned calculateIndirectAddress(unsigned RegIndex,
313 unsigned Channel) const override;
315 const TargetRegisterClass *getIndirectAddrRegClass() const override;
317 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
318 MachineBasicBlock::iterator I,
321 unsigned OffsetReg) const override;
323 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
324 MachineBasicBlock::iterator I,
327 unsigned OffsetReg) const override;
328 void reserveIndirectRegisters(BitVector &Reserved,
329 const MachineFunction &MF) const;
331 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
332 unsigned SavReg, unsigned IndexReg) const;
334 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
336 /// \brief Returns the operand named \p Op. If \p MI does not have an
337 /// operand named \c Op, this function returns nullptr.
338 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
340 const MachineOperand *getNamedOperand(const MachineInstr &MI,
341 unsigned OpName) const {
342 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
345 uint64_t getDefaultRsrcDataFormat() const;
351 int getVOPe64(uint16_t Opcode);
352 int getVOPe32(uint16_t Opcode);
353 int getCommuteRev(uint16_t Opcode);
354 int getCommuteOrig(uint16_t Opcode);
355 int getAddr64Inst(uint16_t Opcode);
356 int getAtomicRetOp(uint16_t Opcode);
357 int getAtomicNoRetOp(uint16_t Opcode);
359 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
360 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
362 } // End namespace AMDGPU
365 namespace KernelInputOffsets {
367 /// Offsets in bytes from the start of the input buffer
380 } // End namespace KernelInputOffsets
381 } // End namespace SI
383 } // End namespace llvm