1 //===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
29 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
31 const SIRegisterInfo &getRegisterInfo() const;
33 virtual void copyPhysReg(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MI, DebugLoc DL,
35 unsigned DestReg, unsigned SrcReg,
38 unsigned commuteOpcode(unsigned Opcode) const;
40 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
41 bool NewMI=false) const;
43 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
46 virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
47 virtual bool isMov(unsigned Opcode) const;
49 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
50 int isMIMG(uint16_t Opcode) const;
51 int isSMRD(uint16_t Opcode) const;
53 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
55 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
57 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
58 unsigned Channel) const;
60 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
61 unsigned SourceReg) const;
63 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
65 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
66 MachineBasicBlock::iterator I,
69 unsigned OffsetReg) const;
71 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
72 MachineBasicBlock::iterator I,
75 unsigned OffsetReg) const;
77 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
82 int getVOPe64(uint16_t Opcode);
83 int getCommuteRev(uint16_t Opcode);
84 int getCommuteOrig(uint16_t Opcode);
86 } // End namespace AMDGPU
88 } // End namespace llvm
90 namespace SIInstrFlags {
92 // First 4 bits are the instruction encoding
99 #endif //SIINSTRINFO_H