1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
35 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
36 MachineBasicBlock::iterator MI,
37 MachineRegisterInfo &MRI,
38 const TargetRegisterClass *RC,
39 const MachineOperand &Op) const;
42 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
44 const SIRegisterInfo &getRegisterInfo() const {
48 virtual void copyPhysReg(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI, DebugLoc DL,
50 unsigned DestReg, unsigned SrcReg,
53 void storeRegToStackSlot(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MI,
55 unsigned SrcReg, bool isKill, int FrameIndex,
56 const TargetRegisterClass *RC,
57 const TargetRegisterInfo *TRI) const;
59 void loadRegFromStackSlot(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MI,
61 unsigned DestReg, int FrameIndex,
62 const TargetRegisterClass *RC,
63 const TargetRegisterInfo *TRI) const;
65 unsigned commuteOpcode(unsigned Opcode) const;
67 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
68 bool NewMI=false) const;
70 virtual unsigned getIEQOpcode() const {
71 llvm_unreachable("Unimplemented");
74 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
75 MachineBasicBlock::iterator I,
76 unsigned DstReg, unsigned SrcReg) const;
77 virtual bool isMov(unsigned Opcode) const;
79 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
80 bool isDS(uint16_t Opcode) const;
81 int isMIMG(uint16_t Opcode) const;
82 int isSMRD(uint16_t Opcode) const;
83 bool isVOP1(uint16_t Opcode) const;
84 bool isVOP2(uint16_t Opcode) const;
85 bool isVOP3(uint16_t Opcode) const;
86 bool isVOPC(uint16_t Opcode) const;
87 bool isInlineConstant(const MachineOperand &MO) const;
88 bool isLiteralConstant(const MachineOperand &MO) const;
90 virtual bool verifyInstruction(const MachineInstr *MI,
91 StringRef &ErrInfo) const;
93 bool isSALUInstr(const MachineInstr &MI) const;
94 static unsigned getVALUOp(const MachineInstr &MI);
95 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
97 /// \brief Return the correct register class for \p OpNo. For target-specific
98 /// instructions, this will return the register class that has been defined
99 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
100 /// the register class of its machine operand.
101 /// to infer the correct register class base on the other operands.
102 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
103 unsigned OpNo) const;\
105 /// \returns true if it is legal for the operand at index \p OpNo
107 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
109 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
110 /// a MOV. For example:
111 /// ADD_I32_e32 VGPR0, 15
114 /// ADD_I32_e32 VGPR0, VGPR1
116 /// If the operand being legalized is a register, then a COPY will be used
118 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
120 /// \brief Legalize all operands in this instruction. This function may
121 /// create new instruction and insert them before \p MI.
122 void legalizeOperands(MachineInstr *MI) const;
124 /// \brief Replace this instruction's opcode with the equivalent VALU
125 /// opcode. This function will also move the users of \p MI to the
126 /// VALU if necessary.
127 void moveToVALU(MachineInstr &MI) const;
129 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
130 unsigned Channel) const;
132 virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
134 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
135 MachineBasicBlock::iterator I,
138 unsigned OffsetReg) const;
140 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
141 MachineBasicBlock::iterator I,
144 unsigned OffsetReg) const;
145 void reserveIndirectRegisters(BitVector &Reserved,
146 const MachineFunction &MF) const;
148 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
149 unsigned SavReg, unsigned IndexReg) const;
154 int getVOPe64(uint16_t Opcode);
155 int getCommuteRev(uint16_t Opcode);
156 int getCommuteOrig(uint16_t Opcode);
158 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
161 } // End namespace AMDGPU
163 } // End namespace llvm
165 namespace SIInstrFlags {
167 // First 4 bits are the instruction encoding
174 #endif //SIINSTRINFO_H