1 //===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
29 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
31 const SIRegisterInfo &getRegisterInfo() const;
33 virtual void copyPhysReg(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MI, DebugLoc DL,
35 unsigned DestReg, unsigned SrcReg,
38 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
41 virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
42 virtual bool isMov(unsigned Opcode) const;
44 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
46 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
48 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
50 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
51 unsigned Channel) const;
53 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
54 unsigned SourceReg) const;
56 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
58 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
59 MachineBasicBlock::iterator I,
62 unsigned OffsetReg) const;
64 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
65 MachineBasicBlock::iterator I,
68 unsigned OffsetReg) const;
70 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
73 } // End namespace llvm
75 namespace SIInstrFlags {
77 // First 4 bits are the instruction encoding
84 #endif //SIINSTRINFO_H