1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35 MachineRegisterInfo &MRI,
36 MachineOperand &SuperReg,
37 const TargetRegisterClass *SuperRC,
39 const TargetRegisterClass *SubRC) const;
41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42 MachineBasicBlock::iterator MI,
43 MachineRegisterInfo &MRI,
44 const TargetRegisterClass *RC,
45 const MachineOperand &Op) const;
47 void splitScalar64BitOp(SmallVectorImpl<MachineInstr *> & Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
53 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
55 const SIRegisterInfo &getRegisterInfo() const override {
59 void copyPhysReg(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MI, DebugLoc DL,
61 unsigned DestReg, unsigned SrcReg,
62 bool KillSrc) const override;
64 void storeRegToStackSlot(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned SrcReg, bool isKill, int FrameIndex,
67 const TargetRegisterClass *RC,
68 const TargetRegisterInfo *TRI) const override;
70 void loadRegFromStackSlot(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator MI,
72 unsigned DestReg, int FrameIndex,
73 const TargetRegisterClass *RC,
74 const TargetRegisterInfo *TRI) const override;
76 unsigned commuteOpcode(unsigned Opcode) const;
78 MachineInstr *commuteInstruction(MachineInstr *MI,
79 bool NewMI=false) const override;
81 bool isTriviallyReMaterializable(const MachineInstr *MI,
82 AliasAnalysis *AA = nullptr) const;
84 unsigned getIEQOpcode() const override {
85 llvm_unreachable("Unimplemented");
88 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
89 MachineBasicBlock::iterator I,
90 unsigned DstReg, unsigned SrcReg) const override;
91 bool isMov(unsigned Opcode) const override;
93 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
94 bool isDS(uint16_t Opcode) const;
95 int isMIMG(uint16_t Opcode) const;
96 int isSMRD(uint16_t Opcode) const;
97 bool isVOP1(uint16_t Opcode) const;
98 bool isVOP2(uint16_t Opcode) const;
99 bool isVOP3(uint16_t Opcode) const;
100 bool isVOPC(uint16_t Opcode) const;
101 bool isInlineConstant(const APInt &Imm) const;
102 bool isInlineConstant(const MachineOperand &MO) const;
103 bool isLiteralConstant(const MachineOperand &MO) const;
105 bool verifyInstruction(const MachineInstr *MI,
106 StringRef &ErrInfo) const override;
108 bool isSALUInstr(const MachineInstr &MI) const;
109 static unsigned getVALUOp(const MachineInstr &MI);
111 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
113 /// \brief Return the correct register class for \p OpNo. For target-specific
114 /// instructions, this will return the register class that has been defined
115 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
116 /// the register class of its machine operand.
117 /// to infer the correct register class base on the other operands.
118 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
119 unsigned OpNo) const;\
121 /// \returns true if it is legal for the operand at index \p OpNo
123 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
125 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
126 /// a MOV. For example:
127 /// ADD_I32_e32 VGPR0, 15
130 /// ADD_I32_e32 VGPR0, VGPR1
132 /// If the operand being legalized is a register, then a COPY will be used
134 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
136 /// \brief Legalize all operands in this instruction. This function may
137 /// create new instruction and insert them before \p MI.
138 void legalizeOperands(MachineInstr *MI) const;
140 /// \brief Replace this instruction's opcode with the equivalent VALU
141 /// opcode. This function will also move the users of \p MI to the
142 /// VALU if necessary.
143 void moveToVALU(MachineInstr &MI) const;
145 unsigned calculateIndirectAddress(unsigned RegIndex,
146 unsigned Channel) const override;
148 const TargetRegisterClass *getIndirectAddrRegClass() const override;
150 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
151 MachineBasicBlock::iterator I,
154 unsigned OffsetReg) const override;
156 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
157 MachineBasicBlock::iterator I,
160 unsigned OffsetReg) const override;
161 void reserveIndirectRegisters(BitVector &Reserved,
162 const MachineFunction &MF) const;
164 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
165 unsigned SavReg, unsigned IndexReg) const;
170 int getVOPe64(uint16_t Opcode);
171 int getCommuteRev(uint16_t Opcode);
172 int getCommuteOrig(uint16_t Opcode);
174 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
177 } // End namespace AMDGPU
179 } // End namespace llvm
181 namespace SIInstrFlags {
183 // First 4 bits are the instruction encoding
190 #endif //SIINSTRINFO_H