1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35 MachineRegisterInfo &MRI,
36 MachineOperand &SuperReg,
37 const TargetRegisterClass *SuperRC,
39 const TargetRegisterClass *SubRC) const;
41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42 MachineBasicBlock::iterator MI,
43 MachineRegisterInfo &MRI,
44 const TargetRegisterClass *RC,
45 const MachineOperand &Op) const;
47 void splitScalar64BitOp(SmallVectorImpl<MachineInstr *> & Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
52 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
54 const SIRegisterInfo &getRegisterInfo() const {
58 virtual void copyPhysReg(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator MI, DebugLoc DL,
60 unsigned DestReg, unsigned SrcReg,
63 void storeRegToStackSlot(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator MI,
65 unsigned SrcReg, bool isKill, int FrameIndex,
66 const TargetRegisterClass *RC,
67 const TargetRegisterInfo *TRI) const;
69 void loadRegFromStackSlot(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI,
71 unsigned DestReg, int FrameIndex,
72 const TargetRegisterClass *RC,
73 const TargetRegisterInfo *TRI) const;
75 unsigned commuteOpcode(unsigned Opcode) const;
77 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
78 bool NewMI=false) const;
80 bool isTriviallyReMaterializable(const MachineInstr *MI,
81 AliasAnalysis *AA = 0) const;
83 virtual unsigned getIEQOpcode() const {
84 llvm_unreachable("Unimplemented");
87 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
88 MachineBasicBlock::iterator I,
89 unsigned DstReg, unsigned SrcReg) const;
90 virtual bool isMov(unsigned Opcode) const;
92 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
93 bool isDS(uint16_t Opcode) const;
94 int isMIMG(uint16_t Opcode) const;
95 int isSMRD(uint16_t Opcode) const;
96 bool isVOP1(uint16_t Opcode) const;
97 bool isVOP2(uint16_t Opcode) const;
98 bool isVOP3(uint16_t Opcode) const;
99 bool isVOPC(uint16_t Opcode) const;
100 bool isInlineConstant(const MachineOperand &MO) const;
101 bool isLiteralConstant(const MachineOperand &MO) const;
103 virtual bool verifyInstruction(const MachineInstr *MI,
104 StringRef &ErrInfo) const;
106 bool isSALUInstr(const MachineInstr &MI) const;
107 static unsigned getVALUOp(const MachineInstr &MI);
109 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
111 /// \brief Return the correct register class for \p OpNo. For target-specific
112 /// instructions, this will return the register class that has been defined
113 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
114 /// the register class of its machine operand.
115 /// to infer the correct register class base on the other operands.
116 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
117 unsigned OpNo) const;\
119 /// \returns true if it is legal for the operand at index \p OpNo
121 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
123 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
124 /// a MOV. For example:
125 /// ADD_I32_e32 VGPR0, 15
128 /// ADD_I32_e32 VGPR0, VGPR1
130 /// If the operand being legalized is a register, then a COPY will be used
132 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
134 /// \brief Legalize all operands in this instruction. This function may
135 /// create new instruction and insert them before \p MI.
136 void legalizeOperands(MachineInstr *MI) const;
138 /// \brief Replace this instruction's opcode with the equivalent VALU
139 /// opcode. This function will also move the users of \p MI to the
140 /// VALU if necessary.
141 void moveToVALU(MachineInstr &MI) const;
143 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
144 unsigned Channel) const;
146 virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
148 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
149 MachineBasicBlock::iterator I,
152 unsigned OffsetReg) const;
154 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
155 MachineBasicBlock::iterator I,
158 unsigned OffsetReg) const;
159 void reserveIndirectRegisters(BitVector &Reserved,
160 const MachineFunction &MF) const;
162 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
163 unsigned SavReg, unsigned IndexReg) const;
168 int getVOPe64(uint16_t Opcode);
169 int getCommuteRev(uint16_t Opcode);
170 int getCommuteOrig(uint16_t Opcode);
172 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
175 } // End namespace AMDGPU
177 } // End namespace llvm
179 namespace SIInstrFlags {
181 // First 4 bits are the instruction encoding
188 #endif //SIINSTRINFO_H