lib/Target/R600/SIInstrInfo.h

   1 //===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief Interface definition for SIInstrInfo.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15
  16 #ifndef SIINSTRINFO_H
  17 #define SIINSTRINFO_H
  18
  19 #include "AMDGPUInstrInfo.h"
  20 #include "SIRegisterInfo.h"
  21
  22 namespace llvm {
  23
  24 class SIInstrInfo : public AMDGPUInstrInfo {
  25 private:
  26   const SIRegisterInfo RI;
  27
  28 public:
  29   explicit SIInstrInfo(AMDGPUTargetMachine &tm);
  30
  31   const SIRegisterInfo &getRegisterInfo() const;
  32
  33   virtual void copyPhysReg(MachineBasicBlock &MBB,
  34                            MachineBasicBlock::iterator MI, DebugLoc DL,
  35                            unsigned DestReg, unsigned SrcReg,
  36                            bool KillSrc) const;
  37
  38   /// \returns the encoding type of this instruction.
  39   unsigned getEncodingType(const MachineInstr &MI) const;
  40
  41   /// \returns the size of this instructions encoding in number of bytes.
  42   unsigned getEncodingBytes(const MachineInstr &MI) const;
  43
  44   virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
  45                                         int64_t Imm) const;
  46
  47   virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
  48   virtual bool isMov(unsigned Opcode) const;
  49
  50   virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
  51
  52   virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
  53
  54   virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
  55
  56   virtual unsigned calculateIndirectAddress(unsigned RegIndex,
  57                                             unsigned Channel) const;
  58
  59   virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
  60                                                       unsigned SourceReg) const;
  61
  62   virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
  63
  64   virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
  65                                                  MachineBasicBlock::iterator I,
  66                                                  unsigned ValueReg,
  67                                                  unsigned Address,
  68                                                  unsigned OffsetReg) const;
  69
  70   virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
  71                                                 MachineBasicBlock::iterator I,
  72                                                 unsigned ValueReg,
  73                                                 unsigned Address,
  74                                                 unsigned OffsetReg) const;
  75
  76   virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
  77   };
  78
  79 } // End namespace llvm
  80
  81 namespace SIInstrFlags {
  82   enum Flags {
  83     // First 4 bits are the instruction encoding
  84     VM_CNT = 1 << 4,
  85     EXP_CNT = 1 << 5,
  86     LGKM_CNT = 1 << 6
  87   };
  88 }
  89
  90 #endif //SIINSTRINFO_H