1 //===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
29 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
31 const SIRegisterInfo &getRegisterInfo() const;
33 virtual void copyPhysReg(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MI, DebugLoc DL,
35 unsigned DestReg, unsigned SrcReg,
38 /// \returns the encoding type of this instruction.
39 unsigned getEncodingType(const MachineInstr &MI) const;
41 /// \returns the size of this instructions encoding in number of bytes.
42 unsigned getEncodingBytes(const MachineInstr &MI) const;
44 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
47 virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
48 virtual bool isMov(unsigned Opcode) const;
50 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
52 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
54 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
56 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
57 unsigned Channel) const;
59 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
60 unsigned SourceReg) const;
62 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
64 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
65 MachineBasicBlock::iterator I,
68 unsigned OffsetReg) const;
70 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
71 MachineBasicBlock::iterator I,
74 unsigned OffsetReg) const;
76 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
79 } // End namespace llvm
81 namespace SIInstrFlags {
83 // First 4 bits are the instruction encoding
90 #endif //SIINSTRINFO_H