1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
43 MachineBasicBlock::iterator MI,
44 MachineRegisterInfo &MRI,
45 const TargetRegisterClass *RC,
46 const MachineOperand &Op) const;
48 void swapOperands(MachineBasicBlock::iterator Inst) const;
50 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst, unsigned Opcode) const;
56 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57 MachineInstr *Inst) const;
58 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59 MachineInstr *Inst) const;
61 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
63 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
64 MachineInstr *MIb) const;
66 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
69 explicit SIInstrInfo(const AMDGPUSubtarget &st);
71 const SIRegisterInfo &getRegisterInfo() const override {
75 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
77 int64_t &Offset2) const override;
79 bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
80 unsigned &BaseReg, unsigned &Offset,
81 const TargetRegisterInfo *TRI) const final;
83 bool shouldClusterLoads(MachineInstr *FirstLdSt,
84 MachineInstr *SecondLdSt,
85 unsigned NumLoads) const final;
87 void copyPhysReg(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MI, DebugLoc DL,
89 unsigned DestReg, unsigned SrcReg,
90 bool KillSrc) const override;
92 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MI,
99 void storeRegToStackSlot(MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator MI,
101 unsigned SrcReg, bool isKill, int FrameIndex,
102 const TargetRegisterClass *RC,
103 const TargetRegisterInfo *TRI) const override;
105 void loadRegFromStackSlot(MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator MI,
107 unsigned DestReg, int FrameIndex,
108 const TargetRegisterClass *RC,
109 const TargetRegisterInfo *TRI) const override;
111 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
113 // \brief Returns an opcode that can be used to move a value to a \p DstRC
114 // register. If there is no hardware instruction that can store to \p
115 // DstRC, then AMDGPU::COPY is returned.
116 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
117 unsigned commuteOpcode(unsigned Opcode) const;
119 MachineInstr *commuteInstruction(MachineInstr *MI,
120 bool NewMI = false) const override;
121 bool findCommutedOpIndices(MachineInstr *MI,
123 unsigned &SrcOpIdx2) const override;
125 bool isTriviallyReMaterializable(const MachineInstr *MI,
126 AliasAnalysis *AA = nullptr) const;
128 bool areMemAccessesTriviallyDisjoint(
129 MachineInstr *MIa, MachineInstr *MIb,
130 AliasAnalysis *AA = nullptr) const override;
132 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
133 MachineBasicBlock::iterator I,
134 unsigned DstReg, unsigned SrcReg) const override;
135 bool isMov(unsigned Opcode) const override;
137 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
139 bool isSALU(uint16_t Opcode) const {
140 return get(Opcode).TSFlags & SIInstrFlags::SALU;
143 bool isVALU(uint16_t Opcode) const {
144 return get(Opcode).TSFlags & SIInstrFlags::VALU;
147 bool isSOP1(uint16_t Opcode) const {
148 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
151 bool isSOP2(uint16_t Opcode) const {
152 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
155 bool isSOPC(uint16_t Opcode) const {
156 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
159 bool isSOPK(uint16_t Opcode) const {
160 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
163 bool isSOPP(uint16_t Opcode) const {
164 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
167 bool isVOP1(uint16_t Opcode) const {
168 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
171 bool isVOP2(uint16_t Opcode) const {
172 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
175 bool isVOP3(uint16_t Opcode) const {
176 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
179 bool isVOPC(uint16_t Opcode) const {
180 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
183 bool isMUBUF(uint16_t Opcode) const {
184 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
187 bool isMTBUF(uint16_t Opcode) const {
188 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
191 bool isSMRD(uint16_t Opcode) const {
192 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
195 bool isDS(uint16_t Opcode) const {
196 return get(Opcode).TSFlags & SIInstrFlags::DS;
199 bool isMIMG(uint16_t Opcode) const {
200 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
203 bool isFLAT(uint16_t Opcode) const {
204 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
207 bool isWQM(uint16_t Opcode) const {
208 return get(Opcode).TSFlags & SIInstrFlags::WQM;
211 bool isInlineConstant(const APInt &Imm) const;
212 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
213 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
215 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
216 const MachineOperand &MO) const;
218 /// \brief Return true if the given offset Size in bytes can be folded into
219 /// the immediate offsets of a memory instruction for the given address space.
220 bool canFoldOffset(unsigned OffsetSize, unsigned AS) const;
222 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
223 /// This function will return false if you pass it a 32-bit instruction.
224 bool hasVALU32BitEncoding(unsigned Opcode) const;
226 /// \brief Returns true if this operand uses the constant bus.
227 bool usesConstantBus(const MachineRegisterInfo &MRI,
228 const MachineOperand &MO,
229 unsigned OpSize) const;
231 /// \brief Return true if this instruction has any modifiers.
232 /// e.g. src[012]_mod, omod, clamp.
233 bool hasModifiers(unsigned Opcode) const;
235 bool hasModifiersSet(const MachineInstr &MI,
236 unsigned OpName) const;
238 bool verifyInstruction(const MachineInstr *MI,
239 StringRef &ErrInfo) const override;
241 static unsigned getVALUOp(const MachineInstr &MI);
243 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
245 /// \brief Return the correct register class for \p OpNo. For target-specific
246 /// instructions, this will return the register class that has been defined
247 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
248 /// the register class of its machine operand.
249 /// to infer the correct register class base on the other operands.
250 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
251 unsigned OpNo) const;
253 /// \brief Return the size in bytes of the operand OpNo on the given
254 // instruction opcode.
255 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
256 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
257 return RI.getRegClass(OpInfo.RegClass)->getSize();
260 /// \brief This form should usually be preferred since it handles operands
261 /// with unknown register classes.
262 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
263 return getOpRegClass(MI, OpNo)->getSize();
266 /// \returns true if it is legal for the operand at index \p OpNo
268 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
270 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
271 /// a MOV. For example:
272 /// ADD_I32_e32 VGPR0, 15
275 /// ADD_I32_e32 VGPR0, VGPR1
277 /// If the operand being legalized is a register, then a COPY will be used
279 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
281 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
283 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
284 const MachineOperand *MO = nullptr) const;
286 /// \brief Legalize all operands in this instruction. This function may
287 /// create new instruction and insert them before \p MI.
288 void legalizeOperands(MachineInstr *MI) const;
290 /// \brief Split an SMRD instruction into two smaller loads of half the
291 // size storing the results in \p Lo and \p Hi.
292 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
293 unsigned HalfImmOp, unsigned HalfSGPROp,
294 MachineInstr *&Lo, MachineInstr *&Hi) const;
296 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
298 /// \brief Replace this instruction's opcode with the equivalent VALU
299 /// opcode. This function will also move the users of \p MI to the
300 /// VALU if necessary.
301 void moveToVALU(MachineInstr &MI) const;
303 unsigned calculateIndirectAddress(unsigned RegIndex,
304 unsigned Channel) const override;
306 const TargetRegisterClass *getIndirectAddrRegClass() const override;
308 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
309 MachineBasicBlock::iterator I,
312 unsigned OffsetReg) const override;
314 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
315 MachineBasicBlock::iterator I,
318 unsigned OffsetReg) const override;
319 void reserveIndirectRegisters(BitVector &Reserved,
320 const MachineFunction &MF) const;
322 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
323 unsigned SavReg, unsigned IndexReg) const;
325 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
327 /// \brief Returns the operand named \p Op. If \p MI does not have an
328 /// operand named \c Op, this function returns nullptr.
329 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
331 const MachineOperand *getNamedOperand(const MachineInstr &MI,
332 unsigned OpName) const {
333 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
336 uint64_t getDefaultRsrcDataFormat() const;
342 int getVOPe64(uint16_t Opcode);
343 int getVOPe32(uint16_t Opcode);
344 int getCommuteRev(uint16_t Opcode);
345 int getCommuteOrig(uint16_t Opcode);
346 int getAddr64Inst(uint16_t Opcode);
347 int getAtomicRetOp(uint16_t Opcode);
348 int getAtomicNoRetOp(uint16_t Opcode);
350 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
351 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
353 } // End namespace AMDGPU
356 namespace KernelInputOffsets {
358 /// Offsets in bytes from the start of the input buffer
371 } // End namespace KernelInputOffsets
372 } // End namespace SI
374 } // End namespace llvm