1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35 MachineRegisterInfo &MRI,
36 MachineOperand &SuperReg,
37 const TargetRegisterClass *SuperRC,
39 const TargetRegisterClass *SubRC) const;
41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42 MachineBasicBlock::iterator MI,
43 MachineRegisterInfo &MRI,
44 const TargetRegisterClass *RC,
45 const MachineOperand &Op) const;
47 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst) const;
56 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
59 explicit SIInstrInfo(const AMDGPUSubtarget &st);
61 const SIRegisterInfo &getRegisterInfo() const override {
65 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
67 int64_t &Offset2) const override;
69 bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
70 unsigned &BaseReg, unsigned &Offset,
71 const TargetRegisterInfo *TRI) const final;
73 void copyPhysReg(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MI, DebugLoc DL,
75 unsigned DestReg, unsigned SrcReg,
76 bool KillSrc) const override;
78 void storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI,
80 unsigned SrcReg, bool isKill, int FrameIndex,
81 const TargetRegisterClass *RC,
82 const TargetRegisterInfo *TRI) const override;
84 void loadRegFromStackSlot(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MI,
86 unsigned DestReg, int FrameIndex,
87 const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI) const override;
90 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
92 unsigned commuteOpcode(unsigned Opcode) const;
94 MachineInstr *commuteInstruction(MachineInstr *MI,
95 bool NewMI=false) const override;
97 bool isTriviallyReMaterializable(const MachineInstr *MI,
98 AliasAnalysis *AA = nullptr) const;
100 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
101 MachineBasicBlock::iterator I,
102 unsigned DstReg, unsigned SrcReg) const override;
103 bool isMov(unsigned Opcode) const override;
105 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
106 bool isDS(uint16_t Opcode) const;
107 bool isMIMG(uint16_t Opcode) const;
108 bool isSMRD(uint16_t Opcode) const;
109 bool isMUBUF(uint16_t Opcode) const;
110 bool isMTBUF(uint16_t Opcode) const;
111 bool isVOP1(uint16_t Opcode) const;
112 bool isVOP2(uint16_t Opcode) const;
113 bool isVOP3(uint16_t Opcode) const;
114 bool isVOPC(uint16_t Opcode) const;
115 bool isInlineConstant(const APInt &Imm) const;
116 bool isInlineConstant(const MachineOperand &MO) const;
117 bool isLiteralConstant(const MachineOperand &MO) const;
119 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
120 const MachineOperand &MO) const;
122 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
123 /// This function will return false if you pass it a 32-bit instruction.
124 bool hasVALU32BitEncoding(unsigned Opcode) const;
126 /// \brief Return true if this instruction has any modifiers.
127 /// e.g. src[012]_mod, omod, clamp.
128 bool hasModifiers(unsigned Opcode) const;
129 bool verifyInstruction(const MachineInstr *MI,
130 StringRef &ErrInfo) const override;
132 bool isSALUInstr(const MachineInstr &MI) const;
133 static unsigned getVALUOp(const MachineInstr &MI);
135 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
137 /// \brief Return the correct register class for \p OpNo. For target-specific
138 /// instructions, this will return the register class that has been defined
139 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
140 /// the register class of its machine operand.
141 /// to infer the correct register class base on the other operands.
142 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
143 unsigned OpNo) const;\
145 /// \returns true if it is legal for the operand at index \p OpNo
147 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
149 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
150 /// a MOV. For example:
151 /// ADD_I32_e32 VGPR0, 15
154 /// ADD_I32_e32 VGPR0, VGPR1
156 /// If the operand being legalized is a register, then a COPY will be used
158 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
160 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
162 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
163 const MachineOperand *MO = nullptr) const;
165 /// \brief Legalize all operands in this instruction. This function may
166 /// create new instruction and insert them before \p MI.
167 void legalizeOperands(MachineInstr *MI) const;
169 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
171 /// \brief Replace this instruction's opcode with the equivalent VALU
172 /// opcode. This function will also move the users of \p MI to the
173 /// VALU if necessary.
174 void moveToVALU(MachineInstr &MI) const;
176 unsigned calculateIndirectAddress(unsigned RegIndex,
177 unsigned Channel) const override;
179 const TargetRegisterClass *getIndirectAddrRegClass() const override;
181 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
182 MachineBasicBlock::iterator I,
185 unsigned OffsetReg) const override;
187 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
188 MachineBasicBlock::iterator I,
191 unsigned OffsetReg) const override;
192 void reserveIndirectRegisters(BitVector &Reserved,
193 const MachineFunction &MF) const;
195 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
196 unsigned SavReg, unsigned IndexReg) const;
198 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
200 /// \brief Returns the operand named \p Op. If \p MI does not have an
201 /// operand named \c Op, this function returns nullptr.
202 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
207 int getVOPe64(uint16_t Opcode);
208 int getVOPe32(uint16_t Opcode);
209 int getCommuteRev(uint16_t Opcode);
210 int getCommuteOrig(uint16_t Opcode);
211 int getMCOpcode(uint16_t Opcode, unsigned Gen);
212 int getAddr64Inst(uint16_t Opcode);
214 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
215 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
217 } // End namespace AMDGPU
219 } // End namespace llvm
221 namespace SIInstrFlags {
223 // First 4 bits are the instruction encoding
230 namespace SISrcMods {