1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35 MachineRegisterInfo &MRI,
36 MachineOperand &SuperReg,
37 const TargetRegisterClass *SuperRC,
39 const TargetRegisterClass *SubRC) const;
41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42 MachineBasicBlock::iterator MI,
43 MachineRegisterInfo &MRI,
44 const TargetRegisterClass *RC,
45 const MachineOperand &Op) const;
47 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
56 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
58 const SIRegisterInfo &getRegisterInfo() const override {
62 void copyPhysReg(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI, DebugLoc DL,
64 unsigned DestReg, unsigned SrcReg,
65 bool KillSrc) const override;
67 void storeRegToStackSlot(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator MI,
69 unsigned SrcReg, bool isKill, int FrameIndex,
70 const TargetRegisterClass *RC,
71 const TargetRegisterInfo *TRI) const override;
73 void loadRegFromStackSlot(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MI,
75 unsigned DestReg, int FrameIndex,
76 const TargetRegisterClass *RC,
77 const TargetRegisterInfo *TRI) const override;
79 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
81 unsigned commuteOpcode(unsigned Opcode) const;
83 MachineInstr *commuteInstruction(MachineInstr *MI,
84 bool NewMI=false) const override;
86 bool isTriviallyReMaterializable(const MachineInstr *MI,
87 AliasAnalysis *AA = nullptr) const;
89 unsigned getIEQOpcode() const override {
90 llvm_unreachable("Unimplemented");
93 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
94 MachineBasicBlock::iterator I,
95 unsigned DstReg, unsigned SrcReg) const override;
96 bool isMov(unsigned Opcode) const override;
98 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
99 bool isDS(uint16_t Opcode) const;
100 int isMIMG(uint16_t Opcode) const;
101 int isSMRD(uint16_t Opcode) const;
102 bool isVOP1(uint16_t Opcode) const;
103 bool isVOP2(uint16_t Opcode) const;
104 bool isVOP3(uint16_t Opcode) const;
105 bool isVOPC(uint16_t Opcode) const;
106 bool isInlineConstant(const APInt &Imm) const;
107 bool isInlineConstant(const MachineOperand &MO) const;
108 bool isLiteralConstant(const MachineOperand &MO) const;
110 bool verifyInstruction(const MachineInstr *MI,
111 StringRef &ErrInfo) const override;
113 bool isSALUInstr(const MachineInstr &MI) const;
114 static unsigned getVALUOp(const MachineInstr &MI);
116 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
118 /// \brief Return the correct register class for \p OpNo. For target-specific
119 /// instructions, this will return the register class that has been defined
120 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
121 /// the register class of its machine operand.
122 /// to infer the correct register class base on the other operands.
123 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
124 unsigned OpNo) const;\
126 /// \returns true if it is legal for the operand at index \p OpNo
128 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
130 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
131 /// a MOV. For example:
132 /// ADD_I32_e32 VGPR0, 15
135 /// ADD_I32_e32 VGPR0, VGPR1
137 /// If the operand being legalized is a register, then a COPY will be used
139 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
141 /// \brief Legalize all operands in this instruction. This function may
142 /// create new instruction and insert them before \p MI.
143 void legalizeOperands(MachineInstr *MI) const;
145 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
147 /// \brief Replace this instruction's opcode with the equivalent VALU
148 /// opcode. This function will also move the users of \p MI to the
149 /// VALU if necessary.
150 void moveToVALU(MachineInstr &MI) const;
152 unsigned calculateIndirectAddress(unsigned RegIndex,
153 unsigned Channel) const override;
155 const TargetRegisterClass *getIndirectAddrRegClass() const override;
157 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
158 MachineBasicBlock::iterator I,
161 unsigned OffsetReg) const override;
163 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
164 MachineBasicBlock::iterator I,
167 unsigned OffsetReg) const override;
168 void reserveIndirectRegisters(BitVector &Reserved,
169 const MachineFunction &MF) const;
171 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
172 unsigned SavReg, unsigned IndexReg) const;
174 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
179 int getVOPe64(uint16_t Opcode);
180 int getCommuteRev(uint16_t Opcode);
181 int getCommuteOrig(uint16_t Opcode);
182 int getMCOpcode(uint16_t Opcode, unsigned Gen);
184 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
187 } // End namespace AMDGPU
189 } // End namespace llvm
191 namespace SIInstrFlags {
193 // First 4 bits are the instruction encoding
200 #endif //SIINSTRINFO_H