1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35 MachineRegisterInfo &MRI,
36 MachineOperand &SuperReg,
37 const TargetRegisterClass *SuperRC,
39 const TargetRegisterClass *SubRC) const;
41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42 MachineBasicBlock::iterator MI,
43 MachineRegisterInfo &MRI,
44 const TargetRegisterClass *RC,
45 const MachineOperand &Op) const;
47 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst) const;
56 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
59 explicit SIInstrInfo(const AMDGPUSubtarget &st);
61 const SIRegisterInfo &getRegisterInfo() const override {
65 void copyPhysReg(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator MI, DebugLoc DL,
67 unsigned DestReg, unsigned SrcReg,
68 bool KillSrc) const override;
70 void storeRegToStackSlot(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator MI,
72 unsigned SrcReg, bool isKill, int FrameIndex,
73 const TargetRegisterClass *RC,
74 const TargetRegisterInfo *TRI) const override;
76 void loadRegFromStackSlot(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator MI,
78 unsigned DestReg, int FrameIndex,
79 const TargetRegisterClass *RC,
80 const TargetRegisterInfo *TRI) const override;
82 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
84 unsigned commuteOpcode(unsigned Opcode) const;
86 MachineInstr *commuteInstruction(MachineInstr *MI,
87 bool NewMI=false) const override;
89 bool isTriviallyReMaterializable(const MachineInstr *MI,
90 AliasAnalysis *AA = nullptr) const;
92 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
93 MachineBasicBlock::iterator I,
94 unsigned DstReg, unsigned SrcReg) const override;
95 bool isMov(unsigned Opcode) const override;
97 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
98 bool isDS(uint16_t Opcode) const;
99 bool isMIMG(uint16_t Opcode) const;
100 bool isSMRD(uint16_t Opcode) const;
101 bool isMUBUF(uint16_t Opcode) const;
102 bool isMTBUF(uint16_t Opcode) const;
103 bool isVOP1(uint16_t Opcode) const;
104 bool isVOP2(uint16_t Opcode) const;
105 bool isVOP3(uint16_t Opcode) const;
106 bool isVOPC(uint16_t Opcode) const;
107 bool isInlineConstant(const APInt &Imm) const;
108 bool isInlineConstant(const MachineOperand &MO) const;
109 bool isLiteralConstant(const MachineOperand &MO) const;
111 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
112 const MachineOperand &MO) const;
114 bool verifyInstruction(const MachineInstr *MI,
115 StringRef &ErrInfo) const override;
117 bool isSALUInstr(const MachineInstr &MI) const;
118 static unsigned getVALUOp(const MachineInstr &MI);
120 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
122 /// \brief Return the correct register class for \p OpNo. For target-specific
123 /// instructions, this will return the register class that has been defined
124 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
125 /// the register class of its machine operand.
126 /// to infer the correct register class base on the other operands.
127 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
128 unsigned OpNo) const;\
130 /// \returns true if it is legal for the operand at index \p OpNo
132 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
134 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
135 /// a MOV. For example:
136 /// ADD_I32_e32 VGPR0, 15
139 /// ADD_I32_e32 VGPR0, VGPR1
141 /// If the operand being legalized is a register, then a COPY will be used
143 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
145 /// \brief Legalize all operands in this instruction. This function may
146 /// create new instruction and insert them before \p MI.
147 void legalizeOperands(MachineInstr *MI) const;
149 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
151 /// \brief Replace this instruction's opcode with the equivalent VALU
152 /// opcode. This function will also move the users of \p MI to the
153 /// VALU if necessary.
154 void moveToVALU(MachineInstr &MI) const;
156 unsigned calculateIndirectAddress(unsigned RegIndex,
157 unsigned Channel) const override;
159 const TargetRegisterClass *getIndirectAddrRegClass() const override;
161 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
162 MachineBasicBlock::iterator I,
165 unsigned OffsetReg) const override;
167 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
168 MachineBasicBlock::iterator I,
171 unsigned OffsetReg) const override;
172 void reserveIndirectRegisters(BitVector &Reserved,
173 const MachineFunction &MF) const;
175 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
176 unsigned SavReg, unsigned IndexReg) const;
178 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
180 /// \brief Returns the operand named \p Op. If \p MI does not have an
181 /// operand named \c Op, this function returns nullptr.
182 const MachineOperand *getNamedOperand(const MachineInstr& MI,
183 unsigned OperandName) const;
188 int getVOPe64(uint16_t Opcode);
189 int getVOPe32(uint16_t Opcode);
190 int getCommuteRev(uint16_t Opcode);
191 int getCommuteOrig(uint16_t Opcode);
192 int getMCOpcode(uint16_t Opcode, unsigned Gen);
194 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
195 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
197 } // End namespace AMDGPU
199 } // End namespace llvm
201 namespace SIInstrFlags {
203 // First 4 bits are the instruction encoding
210 #endif //SIINSTRINFO_H