1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 MachineInstrBuilder buildIndirectIndexLoop(MachineBasicBlock &MBB,
29 MachineBasicBlock::iterator I,
35 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
37 const SIRegisterInfo &getRegisterInfo() const {
41 virtual void copyPhysReg(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MI, DebugLoc DL,
43 unsigned DestReg, unsigned SrcReg,
46 void storeRegToStackSlot(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MI,
48 unsigned SrcReg, bool isKill, int FrameIndex,
49 const TargetRegisterClass *RC,
50 const TargetRegisterInfo *TRI) const;
52 void loadRegFromStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MI,
54 unsigned DestReg, int FrameIndex,
55 const TargetRegisterClass *RC,
56 const TargetRegisterInfo *TRI) const;
58 unsigned commuteOpcode(unsigned Opcode) const;
60 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
61 bool NewMI=false) const;
63 virtual unsigned getIEQOpcode() const {
64 llvm_unreachable("Unimplemented");
67 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
68 MachineBasicBlock::iterator I,
69 unsigned DstReg, unsigned SrcReg) const;
70 virtual bool isMov(unsigned Opcode) const;
72 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
73 bool isDS(uint16_t Opcode) const;
74 int isMIMG(uint16_t Opcode) const;
75 int isSMRD(uint16_t Opcode) const;
76 bool isVOP1(uint16_t Opcode) const;
77 bool isVOP2(uint16_t Opcode) const;
78 bool isVOP3(uint16_t Opcode) const;
79 bool isVOPC(uint16_t Opcode) const;
80 bool isInlineConstant(const MachineOperand &MO) const;
81 bool isLiteralConstant(const MachineOperand &MO) const;
83 virtual bool verifyInstruction(const MachineInstr *MI,
84 StringRef &ErrInfo) const;
86 bool isSALUInstr(const MachineInstr &MI) const;
87 static unsigned getVALUOp(const MachineInstr &MI);
88 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
90 /// \brief Return the correct register class for \p OpNo. For target-specific
91 /// instructions, this will return the register class that has been defined
92 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
93 /// the register class of its machine operand.
94 /// to infer the correct register class base on the other operands.
95 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
96 unsigned OpNo) const;\
98 /// \returns true if it is legal for the operand at index \p OpNo
100 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
102 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
103 /// a MOV. For example:
104 /// ADD_I32_e32 VGPR0, 15
107 /// ADD_I32_e32 VGPR0, VGPR1
109 /// If the operand being legalized is a register, then a COPY will be used
111 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
113 /// \brief Legalize all operands in this instruction. This function may
114 /// create new instruction and insert them before \p MI.
115 void legalizeOperands(MachineInstr *MI) const;
117 /// \brief Replace this instruction's opcode with the equivalent VALU
118 /// opcode. This function will also move the users of \p MI to the
119 /// VALU if necessary.
120 void moveToVALU(MachineInstr &MI) const;
122 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
123 unsigned Channel) const;
125 virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
127 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
128 MachineBasicBlock::iterator I,
131 unsigned OffsetReg) const;
133 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
134 MachineBasicBlock::iterator I,
137 unsigned OffsetReg) const;
138 void reserveIndirectRegisters(BitVector &Reserved,
139 const MachineFunction &MF) const;
141 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
142 unsigned SavReg, unsigned IndexReg) const;
147 int getVOPe64(uint16_t Opcode);
148 int getCommuteRev(uint16_t Opcode);
149 int getCommuteOrig(uint16_t Opcode);
151 } // End namespace AMDGPU
153 } // End namespace llvm
155 namespace SIInstrFlags {
157 // First 4 bits are the instruction encoding
164 #endif //SIINSTRINFO_H