1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 } // End OperandType = "OPERAND_IMMEDIATE"
190 //===----------------------------------------------------------------------===//
192 //===----------------------------------------------------------------------===//
194 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
195 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
196 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
197 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
199 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
200 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
202 //===----------------------------------------------------------------------===//
203 // SI assembler operands
204 //===----------------------------------------------------------------------===//
223 //===----------------------------------------------------------------------===//
225 // SI Instruction multiclass helpers.
227 // Instructions with _32 take 32-bit operands.
228 // Instructions with _64 take 64-bit operands.
230 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
231 // encoding is the standard encoding, but instruction that make use of
232 // any of the instruction modifiers must use the 64-bit encoding.
234 // Instructions with _e32 use the 32-bit encoding.
235 // Instructions with _e64 use the 64-bit encoding.
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
241 //===----------------------------------------------------------------------===//
243 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
244 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
245 opName#" $dst, $src0", pattern
248 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
249 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
250 opName#" $dst, $src0", pattern
253 // 64-bit input, 32-bit output.
254 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
255 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
256 opName#" $dst, $src0", pattern
259 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
260 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
261 opName#" $dst, $src0, $src1", pattern
264 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
265 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
266 opName#" $dst, $src0, $src1", pattern
269 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
270 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
271 opName#" $dst, $src0, $src1", pattern
275 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
276 string opName, PatLeaf cond> : SOPC <
277 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
278 opName#" $dst, $src0, $src1", []>;
280 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
281 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
283 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
284 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
286 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
287 op, (outs SReg_32:$dst), (ins i16imm:$src0),
288 opName#" $dst, $src0", pattern
291 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
292 op, (outs SReg_64:$dst), (ins i16imm:$src0),
293 opName#" $dst, $src0", pattern
296 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
297 RegisterClass dstClass> {
299 op, 1, (outs dstClass:$dst),
300 (ins baseClass:$sbase, u32imm:$offset),
301 asm#" $dst, $sbase, $offset", []
305 op, 0, (outs dstClass:$dst),
306 (ins baseClass:$sbase, SReg_32:$soff),
307 asm#" $dst, $sbase, $soff", []
311 //===----------------------------------------------------------------------===//
312 // Vector ALU classes
313 //===----------------------------------------------------------------------===//
315 // This must always be right before the operand being input modified.
316 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
317 let PrintMethod = "printOperandAndMods";
319 def InputModsNoDefault : Operand <i32> {
320 let PrintMethod = "printOperandAndMods";
323 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
325 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
326 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
330 // Returns the register class to use for the destination of VOP[123C]
331 // instructions for the given VT.
332 class getVALUDstForVT<ValueType VT> {
333 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
336 // Returns the register class to use for source 0 of VOP[12C]
337 // instructions for the given VT.
338 class getVOPSrc0ForVT<ValueType VT> {
339 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
342 // Returns the register class to use for source 1 of VOP[12C] for the
344 class getVOPSrc1ForVT<ValueType VT> {
345 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
348 // Returns the register classes for the source arguments of a VOP[12C]
349 // instruction for the given SrcVTs.
350 class getInRC32 <list<ValueType> SrcVT> {
351 list<RegisterClass> ret = [
352 getVOPSrc0ForVT<SrcVT[0]>.ret,
353 getVOPSrc1ForVT<SrcVT[1]>.ret
357 // Returns the register class to use for sources of VOP3 instructions for the
359 class getVOP3SrcForVT<ValueType VT> {
360 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
363 // Returns the register classes for the source arguments of a VOP3
364 // instruction for the given SrcVTs.
365 class getInRC64 <list<ValueType> SrcVT> {
366 list<RegisterClass> ret = [
367 getVOP3SrcForVT<SrcVT[0]>.ret,
368 getVOP3SrcForVT<SrcVT[1]>.ret,
369 getVOP3SrcForVT<SrcVT[2]>.ret
373 // Returns 1 if the source arguments have modifiers, 0 if they do not.
374 class hasModifiers<ValueType SrcVT> {
375 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
376 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
379 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
380 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
381 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
382 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
386 // Returns the input arguments for VOP3 instructions for the given SrcVT.
387 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
388 RegisterClass Src2RC, int NumSrcArgs,
392 !if (!eq(NumSrcArgs, 1),
393 !if (!eq(HasModifiers, 1),
394 // VOP1 with modifiers
395 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
396 i32imm:$clamp, i32imm:$omod)
398 // VOP1 without modifiers
401 !if (!eq(NumSrcArgs, 2),
402 !if (!eq(HasModifiers, 1),
403 // VOP 2 with modifiers
404 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
405 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
406 i32imm:$clamp, i32imm:$omod)
408 // VOP2 without modifiers
409 (ins Src0RC:$src0, Src1RC:$src1)
411 /* NumSrcArgs == 3 */,
412 !if (!eq(HasModifiers, 1),
413 // VOP3 with modifiers
414 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
415 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
416 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
417 i32imm:$clamp, i32imm:$omod)
419 // VOP3 without modifiers
420 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
424 // Returns the assembly string for the inputs and outputs of a VOP[12C]
425 // instruction. This does not add the _e32 suffix, so it can be reused
427 class getAsm32 <int NumSrcArgs> {
428 string src1 = ", $src1";
429 string src2 = ", $src2";
430 string ret = " $dst, $src0"#
431 !if(!eq(NumSrcArgs, 1), "", src1)#
432 !if(!eq(NumSrcArgs, 3), src2, "");
435 // Returns the assembly string for the inputs and outputs of a VOP3
437 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
438 string src0 = "$src0_modifiers,";
439 string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
440 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
442 !if(!eq(HasModifiers, 0),
443 getAsm32<NumSrcArgs>.ret,
444 " $dst, "#src0#src1#src2#" $clamp, $omod");
448 class VOPProfile <list<ValueType> _ArgVT> {
450 field list<ValueType> ArgVT = _ArgVT;
452 field ValueType DstVT = ArgVT[0];
453 field ValueType Src0VT = ArgVT[1];
454 field ValueType Src1VT = ArgVT[2];
455 field ValueType Src2VT = ArgVT[3];
456 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
457 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
458 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
459 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
460 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
461 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
463 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
464 field bit HasModifiers = hasModifiers<Src0VT>.ret;
466 field dag Outs = (outs DstRC:$dst);
468 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
469 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
472 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
473 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
476 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
477 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
478 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
479 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
480 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
481 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
482 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
483 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
484 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
486 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
487 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
488 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
489 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
490 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
491 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
492 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
493 let Src0RC32 = VReg_32;
495 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
496 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
498 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
499 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
500 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
501 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
504 class VOP <string opName> {
505 string OpName = opName;
508 class VOP2_REV <string revOp, bit isOrig> {
509 string RevOp = revOp;
513 class SIMCInstr <string pseudo, int subtarget> {
514 string PseudoInstr = pseudo;
515 int Subtarget = subtarget;
518 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
520 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
521 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
522 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
523 bits<2> omod = !if(HasModifiers, ?, 0);
524 bits<1> clamp = !if(HasModifiers, ?, 0);
525 bits<9> src1 = !if(HasSrc1, ?, 0);
526 bits<9> src2 = !if(HasSrc2, ?, 0);
529 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
530 VOP3Common <outs, ins, "", pattern>,
532 SIMCInstr<opName, SISubtarget.NONE> {
536 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
537 VOP3 <op, outs, ins, asm, []>,
538 SIMCInstr<opName, SISubtarget.SI>;
540 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
541 string opName, int NumSrcArgs, bit HasMods = 1> {
543 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
545 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
546 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
547 !if(!eq(NumSrcArgs, 2), 0, 1),
552 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
553 list<dag> pattern, string opName, bit HasMods = 1> {
555 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
557 def _si : VOP3_Real_si <
558 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
559 outs, ins, asm, opName>,
560 VOP3DisableFields<0, 0, HasMods>;
563 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
564 list<dag> pattern, string opName, string revOp,
565 bit HasMods = 1, bit UseFullOp = 0> {
567 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
568 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
570 def _si : VOP3_Real_si <op,
571 outs, ins, asm, opName>,
572 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
573 VOP3DisableFields<1, 0, HasMods>;
576 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
577 list<dag> pattern, string opName, string revOp,
578 bit HasMods = 1, bit UseFullOp = 0> {
579 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
580 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
582 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
583 // can write it into any SGPR. We currently don't use the carry out,
584 // so for now hardcode it to VCC as well.
585 let sdst = SIOperand.VCC, Defs = [VCC] in {
586 def _si : VOP3b <op, outs, ins, asm, pattern>,
587 VOP3DisableFields<1, 0, HasMods>,
588 SIMCInstr<opName, SISubtarget.SI>,
589 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
590 } // End sdst = SIOperand.VCC, Defs = [VCC]
593 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
594 list<dag> pattern, string opName,
595 bit HasMods, bit defExec> {
597 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
599 def _si : VOP3_Real_si <
600 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
601 outs, ins, asm, opName>,
602 VOP3DisableFields<1, 0, HasMods> {
603 let Defs = !if(defExec, [EXEC], []);
607 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
608 dag ins32, string asm32, list<dag> pat32,
609 dag ins64, string asm64, list<dag> pat64,
612 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
614 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
617 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
618 SDPatternOperator node = null_frag> : VOP1_Helper <
620 P.Ins32, P.Asm32, [],
623 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
624 i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
625 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
629 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
630 list<dag> pattern, string revOp> :
631 VOP2 <op, outs, ins, opName#asm, pattern>,
633 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
635 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
636 dag ins32, string asm32, list<dag> pat32,
637 dag ins64, string asm64, list<dag> pat64,
638 string revOp, bit HasMods> {
639 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
641 defm _e64 : VOP3_2_m <
642 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
643 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
647 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
648 SDPatternOperator node = null_frag,
649 string revOp = opName> : VOP2_Helper <
651 P.Ins32, P.Asm32, [],
655 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
656 i32:$clamp, i32:$omod)),
657 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
658 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
659 revOp, P.HasModifiers
662 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
663 dag ins32, string asm32, list<dag> pat32,
664 dag ins64, string asm64, list<dag> pat64,
665 string revOp, bit HasMods> {
667 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
669 defm _e64 : VOP3b_2_m <
670 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
671 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
675 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
676 SDPatternOperator node = null_frag,
677 string revOp = opName> : VOP2b_Helper <
679 P.Ins32, P.Asm32, [],
683 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
684 i32:$clamp, i32:$omod)),
685 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
686 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
687 revOp, P.HasModifiers
690 multiclass VOPC_Helper <bits<8> op, string opName,
691 dag ins32, string asm32, list<dag> pat32,
692 dag out64, dag ins64, string asm64, list<dag> pat64,
693 bit HasMods, bit DefExec> {
694 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
695 let Defs = !if(DefExec, [EXEC], []);
698 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
702 multiclass VOPCInst <bits<8> op, string opName,
703 VOPProfile P, PatLeaf cond = COND_NULL,
704 bit DefExec = 0> : VOPC_Helper <
706 P.Ins32, P.Asm32, [],
707 (outs SReg_64:$dst), P.Ins64, P.Asm64,
710 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
711 i32:$clamp, i32:$omod)),
712 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
714 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
715 P.HasModifiers, DefExec
718 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
719 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
721 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
722 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
724 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
725 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
727 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
728 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
731 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
732 PatLeaf cond = COND_NULL>
733 : VOPCInst <op, opName, P, cond, 1>;
735 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
736 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
738 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
739 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
741 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
742 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
744 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
745 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
747 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
748 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
749 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
752 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
753 SDPatternOperator node = null_frag> : VOP3_Helper <
754 op, opName, P.Outs, P.Ins64, P.Asm64,
755 !if(!eq(P.NumSrcArgs, 3),
758 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
759 i32:$clamp, i32:$omod)),
760 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
761 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
762 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
764 !if(!eq(P.NumSrcArgs, 2),
767 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
768 i32:$clamp, i32:$omod)),
769 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
770 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
771 /* P.NumSrcArgs == 1 */,
774 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
775 i32:$clamp, i32:$omod))))],
776 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
777 P.NumSrcArgs, P.HasModifiers
780 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
781 string opName, list<dag> pattern> :
783 op, (outs vrc:$dst0, SReg_64:$dst1),
784 (ins arc:$src0, arc:$src1, arc:$src2,
785 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
786 opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern,
790 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
791 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
793 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
794 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
796 //===----------------------------------------------------------------------===//
797 // Vector I/O classes
798 //===----------------------------------------------------------------------===//
800 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
801 DS <op, outs, ins, asm, pat> {
804 // Single load interpret the 2 i8imm operands as a single i16 offset.
805 let offset0 = offset{7-0};
806 let offset1 = offset{15-8};
809 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
811 (outs regClass:$vdst),
812 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
813 asm#" $vdst, $addr, $offset, [M0]",
821 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
823 (outs regClass:$vdst),
824 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
825 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
833 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
836 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
837 asm#" $addr, $data0, $offset [M0]",
845 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
848 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
849 u8imm:$offset0, u8imm:$offset1),
850 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
857 // 1 address, 1 data.
858 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
861 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
862 asm#" $vdst, $addr, $data0, $offset, [M0]",
870 // 1 address, 2 data.
871 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
874 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
875 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
881 // 1 address, 2 data.
882 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
885 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
886 asm#" $addr, $data0, $data1, $offset, [M0]",
892 // 1 address, 1 data.
893 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
896 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
897 asm#" $addr, $data0, $offset, [M0]",
905 class MUBUFAddr64Table <bit is_addr64> {
907 bit IsAddr64 = is_addr64;
910 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
913 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
914 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
915 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
916 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
917 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
923 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
924 ValueType load_vt = i32,
925 SDPatternOperator ld = null_frag> {
927 let lds = 0, mayLoad = 1 in {
931 let offen = 0, idxen = 0, vaddr = 0 in {
932 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
933 (ins SReg_128:$srsrc,
934 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
936 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
937 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
938 i32:$soffset, i16:$offset,
939 i1:$glc, i1:$slc, i1:$tfe)))]>,
943 let offen = 1, idxen = 0 in {
944 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
945 (ins SReg_128:$srsrc, VReg_32:$vaddr,
946 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
948 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
951 let offen = 0, idxen = 1 in {
952 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
953 (ins SReg_128:$srsrc, VReg_32:$vaddr,
954 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
956 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
959 let offen = 1, idxen = 1 in {
960 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
961 (ins SReg_128:$srsrc, VReg_64:$vaddr,
962 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
963 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
967 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
968 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
969 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
970 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
971 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
972 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
977 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
978 ValueType store_vt, SDPatternOperator st> {
980 let addr64 = 0, lds = 0 in {
984 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
985 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
987 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
988 "$glc"#"$slc"#"$tfe",
992 let offen = 0, idxen = 0, vaddr = 0 in {
993 def _OFFSET : MUBUF <
995 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
996 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
997 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
998 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
999 i16:$offset, i1:$glc, i1:$slc,
1001 >, MUBUFAddr64Table<0>;
1002 } // offen = 0, idxen = 0, vaddr = 0
1004 let offen = 1, idxen = 0 in {
1005 def _OFFEN : MUBUF <
1007 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1008 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1009 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1010 "$glc"#"$slc"#"$tfe",
1013 } // end offen = 1, idxen = 0
1015 } // End addr64 = 0, lds = 0
1017 def _ADDR64 : MUBUF <
1019 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1020 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1021 [(st store_vt:$vdata,
1022 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1036 let soffset = 128; // ZERO
1040 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
1042 (outs regClass:$dst),
1043 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1044 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1045 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1046 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1047 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
1053 class MIMG_Mask <string op, int channels> {
1055 int Channels = channels;
1058 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1059 RegisterClass dst_rc,
1060 RegisterClass src_rc> : MIMG <
1062 (outs dst_rc:$vdata),
1063 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1064 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1066 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1067 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1072 let hasPostISelHook = 1;
1075 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1076 RegisterClass dst_rc,
1078 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1079 MIMG_Mask<asm#"_V1", channels>;
1080 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1081 MIMG_Mask<asm#"_V2", channels>;
1082 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1083 MIMG_Mask<asm#"_V4", channels>;
1086 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1087 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1088 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1089 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1090 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1093 class MIMG_Sampler_Helper <bits<7> op, string asm,
1094 RegisterClass dst_rc,
1095 RegisterClass src_rc> : MIMG <
1097 (outs dst_rc:$vdata),
1098 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1099 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1100 SReg_256:$srsrc, SReg_128:$ssamp),
1101 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1102 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1106 let hasPostISelHook = 1;
1109 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1110 RegisterClass dst_rc,
1112 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1113 MIMG_Mask<asm#"_V1", channels>;
1114 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1115 MIMG_Mask<asm#"_V2", channels>;
1116 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1117 MIMG_Mask<asm#"_V4", channels>;
1118 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1119 MIMG_Mask<asm#"_V8", channels>;
1120 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1121 MIMG_Mask<asm#"_V16", channels>;
1124 multiclass MIMG_Sampler <bits<7> op, string asm> {
1125 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1126 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1127 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1128 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1131 class MIMG_Gather_Helper <bits<7> op, string asm,
1132 RegisterClass dst_rc,
1133 RegisterClass src_rc> : MIMG <
1135 (outs dst_rc:$vdata),
1136 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1137 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1138 SReg_256:$srsrc, SReg_128:$ssamp),
1139 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1140 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1145 // DMASK was repurposed for GATHER4. 4 components are always
1146 // returned and DMASK works like a swizzle - it selects
1147 // the component to fetch. The only useful DMASK values are
1148 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1149 // (red,red,red,red) etc.) The ISA document doesn't mention
1151 // Therefore, disable all code which updates DMASK by setting these two:
1153 let hasPostISelHook = 0;
1156 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1157 RegisterClass dst_rc,
1159 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1160 MIMG_Mask<asm#"_V1", channels>;
1161 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1162 MIMG_Mask<asm#"_V2", channels>;
1163 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1164 MIMG_Mask<asm#"_V4", channels>;
1165 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1166 MIMG_Mask<asm#"_V8", channels>;
1167 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1168 MIMG_Mask<asm#"_V16", channels>;
1171 multiclass MIMG_Gather <bits<7> op, string asm> {
1172 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1173 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1174 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1175 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1178 //===----------------------------------------------------------------------===//
1179 // Vector instruction mappings
1180 //===----------------------------------------------------------------------===//
1182 // Maps an opcode in e32 form to its e64 equivalent
1183 def getVOPe64 : InstrMapping {
1184 let FilterClass = "VOP";
1185 let RowFields = ["OpName"];
1186 let ColFields = ["Size"];
1188 let ValueCols = [["8"]];
1191 // Maps an opcode in e64 form to its e32 equivalent
1192 def getVOPe32 : InstrMapping {
1193 let FilterClass = "VOP";
1194 let RowFields = ["OpName"];
1195 let ColFields = ["Size"];
1197 let ValueCols = [["4"]];
1200 // Maps an original opcode to its commuted version
1201 def getCommuteRev : InstrMapping {
1202 let FilterClass = "VOP2_REV";
1203 let RowFields = ["RevOp"];
1204 let ColFields = ["IsOrig"];
1206 let ValueCols = [["0"]];
1209 def getMaskedMIMGOp : InstrMapping {
1210 let FilterClass = "MIMG_Mask";
1211 let RowFields = ["Op"];
1212 let ColFields = ["Channels"];
1214 let ValueCols = [["1"], ["2"], ["3"] ];
1217 // Maps an commuted opcode to its original version
1218 def getCommuteOrig : InstrMapping {
1219 let FilterClass = "VOP2_REV";
1220 let RowFields = ["RevOp"];
1221 let ColFields = ["IsOrig"];
1223 let ValueCols = [["1"]];
1226 def isDS : InstrMapping {
1227 let FilterClass = "DS";
1228 let RowFields = ["Inst"];
1229 let ColFields = ["Size"];
1231 let ValueCols = [["8"]];
1234 def getMCOpcode : InstrMapping {
1235 let FilterClass = "SIMCInstr";
1236 let RowFields = ["PseudoInstr"];
1237 let ColFields = ["Subtarget"];
1238 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1239 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1242 def getAddr64Inst : InstrMapping {
1243 let FilterClass = "MUBUFAddr64Table";
1244 let RowFields = ["NAME"];
1245 let ColFields = ["IsAddr64"];
1247 let ValueCols = [["1"]];
1250 include "SIInstructions.td"