1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 // SMRD takes a 64bit memory address and can only add an 32bit offset
15 def SIadd64bit32bit : SDNode<"ISD::ADD",
16 SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i32>]>
19 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
20 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, i128>, SDTCisVT<2, i32>]>,
21 [SDNPMayLoad, SDNPMemOperand]
24 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
26 [SDTCisVT<0, i128>, // rsrc(SGPR)
27 SDTCisVT<1, iAny>, // vdata(VGPR)
28 SDTCisVT<2, i32>, // num_channels(imm)
29 SDTCisVT<3, i32>, // vaddr(VGPR)
30 SDTCisVT<4, i32>, // soffset(SGPR)
31 SDTCisVT<5, i32>, // inst_offset(imm)
32 SDTCisVT<6, i32>, // dfmt(imm)
33 SDTCisVT<7, i32>, // nfmt(imm)
34 SDTCisVT<8, i32>, // offen(imm)
35 SDTCisVT<9, i32>, // idxen(imm)
36 SDTCisVT<10, i32>, // glc(imm)
37 SDTCisVT<11, i32>, // slc(imm)
38 SDTCisVT<12, i32> // tfe(imm)
40 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
43 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, i128>, SDTCisVT<2, i16>,
48 class SDSample<string opcode> : SDNode <opcode,
49 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
50 SDTCisVT<3, i128>, SDTCisVT<4, i32>]>
53 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
54 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
55 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
56 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
58 // Transformation function, extract the lower 32bit of a 64bit immediate
59 def LO32 : SDNodeXForm<imm, [{
60 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
63 def LO32f : SDNodeXForm<fpimm, [{
64 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
65 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
68 // Transformation function, extract the upper 32bit of a 64bit immediate
69 def HI32 : SDNodeXForm<imm, [{
70 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
73 def HI32f : SDNodeXForm<fpimm, [{
74 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
75 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
78 def IMM8bitDWORD : PatLeaf <(imm),
79 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
82 def as_dword_i32imm : SDNodeXForm<imm, [{
83 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
86 def as_i1imm : SDNodeXForm<imm, [{
87 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
90 def as_i8imm : SDNodeXForm<imm, [{
91 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
94 def as_i16imm : SDNodeXForm<imm, [{
95 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
98 def as_i32imm: SDNodeXForm<imm, [{
99 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
102 def IMM8bit : PatLeaf <(imm),
103 [{return isUInt<8>(N->getZExtValue());}]
106 def IMM12bit : PatLeaf <(imm),
107 [{return isUInt<12>(N->getZExtValue());}]
110 def IMM16bit : PatLeaf <(imm),
111 [{return isUInt<16>(N->getZExtValue());}]
114 def mubuf_vaddr_offset : PatFrag<
115 (ops node:$ptr, node:$offset, node:$imm_offset),
116 (add (add node:$ptr, node:$offset), node:$imm_offset)
119 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
120 return isInlineImmediate(N);
123 class SGPRImm <dag frag> : PatLeaf<frag, [{
124 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
125 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
128 const SIRegisterInfo *SIRI =
129 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
130 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
132 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
139 def FRAMEri32 : Operand<iPTR> {
140 let MIOperandInfo = (ops SReg_32:$ptr, i32imm:$index);
143 //===----------------------------------------------------------------------===//
144 // SI assembler operands
145 //===----------------------------------------------------------------------===//
152 include "SIInstrFormats.td"
154 //===----------------------------------------------------------------------===//
156 // SI Instruction multiclass helpers.
158 // Instructions with _32 take 32-bit operands.
159 // Instructions with _64 take 64-bit operands.
161 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
162 // encoding is the standard encoding, but instruction that make use of
163 // any of the instruction modifiers must use the 64-bit encoding.
165 // Instructions with _e32 use the 32-bit encoding.
166 // Instructions with _e64 use the 64-bit encoding.
168 //===----------------------------------------------------------------------===//
170 //===----------------------------------------------------------------------===//
172 //===----------------------------------------------------------------------===//
174 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
175 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
176 opName#" $dst, $src0", pattern
179 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
180 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
181 opName#" $dst, $src0", pattern
184 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
185 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
186 opName#" $dst, $src0, $src1", pattern
189 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
190 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
191 opName#" $dst, $src0, $src1", pattern
194 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
195 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
196 opName#" $dst, $src0, $src1", pattern
199 class SOPC_32 <bits<7> op, string opName, list<dag> pattern> : SOPC <
200 op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
201 opName#" $dst, $src0, $src1", pattern
204 class SOPC_64 <bits<7> op, string opName, list<dag> pattern> : SOPC <
205 op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
206 opName#" $dst, $src0, $src1", pattern
209 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
210 op, (outs SReg_32:$dst), (ins i16imm:$src0),
211 opName#" $dst, $src0", pattern
214 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
215 op, (outs SReg_64:$dst), (ins i16imm:$src0),
216 opName#" $dst, $src0", pattern
219 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
220 RegisterClass dstClass> {
222 op, 1, (outs dstClass:$dst),
223 (ins baseClass:$sbase, i32imm:$offset),
224 asm#" $dst, $sbase, $offset", []
228 op, 0, (outs dstClass:$dst),
229 (ins baseClass:$sbase, SReg_32:$soff),
230 asm#" $dst, $sbase, $soff", []
234 //===----------------------------------------------------------------------===//
235 // Vector ALU classes
236 //===----------------------------------------------------------------------===//
238 class VOP <string opName> {
239 string OpName = opName;
242 class VOP2_REV <string revOp, bit isOrig> {
243 string RevOp = revOp;
247 multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
248 string opName, list<dag> pattern> {
251 op, (outs drc:$dst), (ins src:$src0),
252 opName#"_e32 $dst, $src0", pattern
256 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
259 i32imm:$abs, i32imm:$clamp,
260 i32imm:$omod, i32imm:$neg),
261 opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
263 let src1 = SIOperand.ZERO;
264 let src2 = SIOperand.ZERO;
268 multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern>
269 : VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
271 multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
272 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
274 multiclass VOP1_32_64 <bits<8> op, string opName, list<dag> pattern>
275 : VOP1_Helper <op, VReg_32, VSrc_64, opName, pattern>;
277 multiclass VOP1_64_32 <bits<8> op, string opName, list<dag> pattern>
278 : VOP1_Helper <op, VReg_64, VSrc_32, opName, pattern>;
280 multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
281 string opName, list<dag> pattern, string revOp> {
283 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1),
284 opName#"_e32 $dst, $src0, $src1", pattern
285 >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
288 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
290 (ins arc:$src0, arc:$src1,
291 i32imm:$abs, i32imm:$clamp,
292 i32imm:$omod, i32imm:$neg),
293 opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
294 >, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
295 let src2 = SIOperand.ZERO;
299 multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern,
300 string revOp = opName>
301 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern, revOp>;
303 multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern,
304 string revOp = opName>
305 : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern, revOp>;
307 multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
308 RegisterClass src0_rc, string revOp = opName> {
311 op, (outs VReg_32:$dst), (ins src0_rc:$src0, VReg_32:$src1),
312 opName#"_e32 $dst, $src0, $src1", pattern
313 >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
316 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
318 (ins VSrc_32:$src0, VSrc_32:$src1,
319 i32imm:$abs, i32imm:$clamp,
320 i32imm:$omod, i32imm:$neg),
321 opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
322 >, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
323 let src2 = SIOperand.ZERO;
324 /* the VOP2 variant puts the carry out into VCC, the VOP3 variant
325 can write it into any SGPR. We currently don't use the carry out,
326 so for now hardcode it to VCC as well */
327 let sdst = SIOperand.VCC;
331 multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
332 string opName, ValueType vt, PatLeaf cond> {
335 op, (ins arc:$src0, vrc:$src1),
336 opName#"_e32 $dst, $src0, $src1", []
340 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
342 (ins arc:$src0, arc:$src1,
343 InstFlag:$abs, InstFlag:$clamp,
344 InstFlag:$omod, InstFlag:$neg),
345 opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg",
346 !if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>,
347 [(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
350 let src2 = SIOperand.ZERO;
354 multiclass VOPC_32 <bits<8> op, string opName,
355 ValueType vt = untyped, PatLeaf cond = COND_NULL>
356 : VOPC_Helper <op, VReg_32, VSrc_32, opName, vt, cond>;
358 multiclass VOPC_64 <bits<8> op, string opName,
359 ValueType vt = untyped, PatLeaf cond = COND_NULL>
360 : VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>;
362 class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
363 op, (outs VReg_32:$dst),
364 (ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
365 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
366 opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
369 class VOP3_64_Shift <bits <9> op, string opName, list<dag> pattern> : VOP3 <
370 op, (outs VReg_64:$dst),
371 (ins VSrc_64:$src0, VSrc_32:$src1),
372 opName#" $dst, $src0, $src1", pattern
375 let src2 = SIOperand.ZERO;
382 class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
383 op, (outs VReg_64:$dst),
384 (ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
385 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
386 opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
389 //===----------------------------------------------------------------------===//
390 // Vector I/O classes
391 //===----------------------------------------------------------------------===//
393 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
394 DS <op, outs, ins, asm, pat> {
397 // Single load interpret the 2 i8imm operands as a single i16 offset.
398 let offset0 = offset{7-0};
399 let offset1 = offset{15-8};
402 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
404 (outs regClass:$vdst),
405 (ins i1imm:$gds, VReg_32:$addr, i16imm:$offset),
406 asm#" $vdst, $addr, $offset, [M0]",
414 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
416 (outs regClass:$vdst),
417 (ins i1imm:$gds, VReg_32:$addr, i8imm:$offset0, i8imm:$offset1),
418 asm#" $gds, $vdst, $addr, $offset0, $offset1, [M0]",
426 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
429 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, i16imm:$offset),
430 asm#" $addr, $data0, $offset [M0]",
438 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
441 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, i8imm:$offset0, i8imm:$offset1),
442 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
449 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
452 (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset),
453 asm#" $vdst, $addr, $data0, $offset, [M0]",
461 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
464 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
465 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
466 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
467 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
468 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
474 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
476 let lds = 0, mayLoad = 1 in {
480 let offen = 0, idxen = 0 in {
481 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
482 (ins SReg_128:$srsrc, VReg_32:$vaddr,
483 i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
484 i1imm:$slc, i1imm:$tfe),
485 asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
488 let offen = 1, idxen = 0, offset = 0 in {
489 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
490 (ins SReg_128:$srsrc, VReg_32:$vaddr,
491 SSrc_32:$soffset, i1imm:$glc, i1imm:$slc,
493 asm#" $vdata, $srsrc + $vaddr + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
496 let offen = 0, idxen = 1 in {
497 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
498 (ins SReg_128:$srsrc, VReg_32:$vaddr,
499 i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
500 i1imm:$slc, i1imm:$tfe),
501 asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
504 let offen = 1, idxen = 1 in {
505 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
506 (ins SReg_128:$srsrc, VReg_64:$vaddr,
507 SSrc_32:$soffset, i1imm:$glc,
508 i1imm:$slc, i1imm:$tfe),
509 asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
513 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
514 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
515 (ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
516 asm#" $vdata, $srsrc + $vaddr + $offset", []>;
521 class MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
522 MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
524 name#" $vdata, $srsrc + $vaddr + $offset",
538 let soffset = 128; // ZERO
541 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
543 (outs regClass:$dst),
544 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
545 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
546 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
547 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
548 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
554 class MIMG_Mask <string op, int channels> {
556 int Channels = channels;
559 class MIMG_NoSampler_Helper <bits<7> op, string asm,
560 RegisterClass dst_rc,
561 RegisterClass src_rc> : MIMG <
563 (outs dst_rc:$vdata),
564 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
565 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
567 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
568 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
573 let hasPostISelHook = 1;
576 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
577 RegisterClass dst_rc,
579 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
580 MIMG_Mask<asm#"_V1", channels>;
581 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
582 MIMG_Mask<asm#"_V2", channels>;
583 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
584 MIMG_Mask<asm#"_V4", channels>;
587 multiclass MIMG_NoSampler <bits<7> op, string asm> {
588 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
589 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
590 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
591 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
594 class MIMG_Sampler_Helper <bits<7> op, string asm,
595 RegisterClass dst_rc,
596 RegisterClass src_rc> : MIMG <
598 (outs dst_rc:$vdata),
599 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
600 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
601 SReg_256:$srsrc, SReg_128:$ssamp),
602 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
603 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
607 let hasPostISelHook = 1;
610 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
611 RegisterClass dst_rc,
613 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
614 MIMG_Mask<asm#"_V1", channels>;
615 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
616 MIMG_Mask<asm#"_V2", channels>;
617 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
618 MIMG_Mask<asm#"_V4", channels>;
619 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
620 MIMG_Mask<asm#"_V8", channels>;
621 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
622 MIMG_Mask<asm#"_V16", channels>;
625 multiclass MIMG_Sampler <bits<7> op, string asm> {
626 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
627 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
628 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
629 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
632 //===----------------------------------------------------------------------===//
633 // Vector instruction mappings
634 //===----------------------------------------------------------------------===//
636 // Maps an opcode in e32 form to its e64 equivalent
637 def getVOPe64 : InstrMapping {
638 let FilterClass = "VOP";
639 let RowFields = ["OpName"];
640 let ColFields = ["Size"];
642 let ValueCols = [["8"]];
645 // Maps an original opcode to its commuted version
646 def getCommuteRev : InstrMapping {
647 let FilterClass = "VOP2_REV";
648 let RowFields = ["RevOp"];
649 let ColFields = ["IsOrig"];
651 let ValueCols = [["0"]];
654 def getMaskedMIMGOp : InstrMapping {
655 let FilterClass = "MIMG_Mask";
656 let RowFields = ["Op"];
657 let ColFields = ["Channels"];
659 let ValueCols = [["1"], ["2"], ["3"] ];
662 // Maps an commuted opcode to its original version
663 def getCommuteOrig : InstrMapping {
664 let FilterClass = "VOP2_REV";
665 let RowFields = ["RevOp"];
666 let ColFields = ["IsOrig"];
668 let ValueCols = [["1"]];
671 def isDS : InstrMapping {
672 let FilterClass = "DS";
673 let RowFields = ["Inst"];
674 let ColFields = ["Size"];
676 let ValueCols = [["8"]];
679 include "SIInstructions.td"