1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isVI : Predicate <
12 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
13 AssemblerPredicate<"FeatureGCN3Encoding">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
22 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
23 field bits<8> SI = si;
24 field bits<8> VI = vi;
26 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
30 class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
34 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
38 class vop2 <bits<6> si, bits<6> vi = si> : vop {
39 field bits<6> SI = si;
40 field bits<6> VI = vi;
42 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
48 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
52 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
57 class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
62 class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
67 class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
72 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
73 // in AMDGPUInstrInfo.cpp
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
85 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
86 [SDNPMayLoad, SDNPMemOperand]
89 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
91 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
92 SDTCisVT<1, iAny>, // vdata(VGPR)
93 SDTCisVT<2, i32>, // num_channels(imm)
94 SDTCisVT<3, i32>, // vaddr(VGPR)
95 SDTCisVT<4, i32>, // soffset(SGPR)
96 SDTCisVT<5, i32>, // inst_offset(imm)
97 SDTCisVT<6, i32>, // dfmt(imm)
98 SDTCisVT<7, i32>, // nfmt(imm)
99 SDTCisVT<8, i32>, // offen(imm)
100 SDTCisVT<9, i32>, // idxen(imm)
101 SDTCisVT<10, i32>, // glc(imm)
102 SDTCisVT<11, i32>, // slc(imm)
103 SDTCisVT<12, i32> // tfe(imm)
105 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
108 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
109 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
113 class SDSample<string opcode> : SDNode <opcode,
114 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
115 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
118 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
119 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
120 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
121 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
123 def SIconstdata_ptr : SDNode<
124 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
127 //===----------------------------------------------------------------------===//
128 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
129 // to be glued to the memory instructions.
130 //===----------------------------------------------------------------------===//
132 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
136 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
137 return isLocalLoad(cast<LoadSDNode>(N));
140 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
141 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
142 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
145 def si_load_local_align8 : Aligned8Bytes <
146 (ops node:$ptr), (si_load_local node:$ptr)
149 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
150 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
152 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
154 multiclass SIExtLoadLocal <PatFrag ld_node> {
156 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
157 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
160 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
161 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
165 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
166 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
168 def SIst_local : SDNode <"ISD::STORE", SDTStore,
169 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
172 def si_st_local : PatFrag <
173 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
174 return isLocalStore(cast<StoreSDNode>(N));
177 def si_store_local : PatFrag <
178 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
179 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
180 !cast<StoreSDNode>(N)->isTruncatingStore();
183 def si_store_local_align8 : Aligned8Bytes <
184 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
187 def si_truncstore_local : PatFrag <
188 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
189 return cast<StoreSDNode>(N)->isTruncatingStore();
192 def si_truncstore_local_i8 : PatFrag <
193 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
194 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
197 def si_truncstore_local_i16 : PatFrag <
198 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
199 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
202 multiclass SIAtomicM0Glue2 <string op_name> {
204 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
205 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
208 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
211 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
212 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
213 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
214 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
215 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
216 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
217 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
218 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
219 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
220 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
222 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
223 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
226 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
228 // Transformation function, extract the lower 32bit of a 64bit immediate
229 def LO32 : SDNodeXForm<imm, [{
230 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
234 def LO32f : SDNodeXForm<fpimm, [{
235 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
236 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
239 // Transformation function, extract the upper 32bit of a 64bit immediate
240 def HI32 : SDNodeXForm<imm, [{
241 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
244 def HI32f : SDNodeXForm<fpimm, [{
245 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
246 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
250 def IMM8bitDWORD : PatLeaf <(imm),
251 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
254 def as_dword_i32imm : SDNodeXForm<imm, [{
255 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
258 def as_i1imm : SDNodeXForm<imm, [{
259 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
262 def as_i8imm : SDNodeXForm<imm, [{
263 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
266 def as_i16imm : SDNodeXForm<imm, [{
267 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
270 def as_i32imm: SDNodeXForm<imm, [{
271 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
274 def as_i64imm: SDNodeXForm<imm, [{
275 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
278 // Copied from the AArch64 backend:
279 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
280 return CurDAG->getTargetConstant(
281 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
284 // Copied from the AArch64 backend:
285 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
286 return CurDAG->getTargetConstant(
287 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
290 def IMM8bit : PatLeaf <(imm),
291 [{return isUInt<8>(N->getZExtValue());}]
294 def IMM12bit : PatLeaf <(imm),
295 [{return isUInt<12>(N->getZExtValue());}]
298 def IMM16bit : PatLeaf <(imm),
299 [{return isUInt<16>(N->getZExtValue());}]
302 def IMM20bit : PatLeaf <(imm),
303 [{return isUInt<20>(N->getZExtValue());}]
306 def IMM32bit : PatLeaf <(imm),
307 [{return isUInt<32>(N->getZExtValue());}]
310 def mubuf_vaddr_offset : PatFrag<
311 (ops node:$ptr, node:$offset, node:$imm_offset),
312 (add (add node:$ptr, node:$offset), node:$imm_offset)
315 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
316 return isInlineImmediate(N);
319 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
320 return isInlineImmediate(N);
323 class SGPRImm <dag frag> : PatLeaf<frag, [{
324 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
327 const SIRegisterInfo *SIRI =
328 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
329 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
331 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
338 //===----------------------------------------------------------------------===//
340 //===----------------------------------------------------------------------===//
342 def FRAMEri32 : Operand<iPTR> {
343 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
346 def SoppBrTarget : AsmOperandClass {
347 let Name = "SoppBrTarget";
348 let ParserMethod = "parseSOppBrTarget";
351 def sopp_brtarget : Operand<OtherVT> {
352 let EncoderMethod = "getSOPPBrEncoding";
353 let OperandType = "OPERAND_PCREL";
354 let ParserMatchClass = SoppBrTarget;
357 include "SIInstrFormats.td"
358 include "VIInstrFormats.td"
360 def MubufOffsetMatchClass : AsmOperandClass {
361 let Name = "MubufOffset";
362 let ParserMethod = "parseMubufOptionalOps";
363 let RenderMethod = "addImmOperands";
366 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
367 let Name = "DSOffset"#parser;
368 let ParserMethod = parser;
369 let RenderMethod = "addImmOperands";
370 let PredicateMethod = "isDSOffset";
373 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
374 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
376 def DSOffset01MatchClass : AsmOperandClass {
377 let Name = "DSOffset1";
378 let ParserMethod = "parseDSOff01OptionalOps";
379 let RenderMethod = "addImmOperands";
380 let PredicateMethod = "isDSOffset01";
383 class GDSBaseMatchClass <string parser> : AsmOperandClass {
384 let Name = "GDS"#parser;
385 let PredicateMethod = "isImm";
386 let ParserMethod = parser;
387 let RenderMethod = "addImmOperands";
390 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
391 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
393 def GLCMatchClass : AsmOperandClass {
395 let PredicateMethod = "isImm";
396 let ParserMethod = "parseMubufOptionalOps";
397 let RenderMethod = "addImmOperands";
400 def SLCMatchClass : AsmOperandClass {
402 let PredicateMethod = "isImm";
403 let ParserMethod = "parseMubufOptionalOps";
404 let RenderMethod = "addImmOperands";
407 def TFEMatchClass : AsmOperandClass {
409 let PredicateMethod = "isImm";
410 let ParserMethod = "parseMubufOptionalOps";
411 let RenderMethod = "addImmOperands";
414 def OModMatchClass : AsmOperandClass {
416 let PredicateMethod = "isImm";
417 let ParserMethod = "parseVOP3OptionalOps";
418 let RenderMethod = "addImmOperands";
421 def ClampMatchClass : AsmOperandClass {
423 let PredicateMethod = "isImm";
424 let ParserMethod = "parseVOP3OptionalOps";
425 let RenderMethod = "addImmOperands";
428 let OperandType = "OPERAND_IMMEDIATE" in {
430 def offen : Operand<i1> {
431 let PrintMethod = "printOffen";
433 def idxen : Operand<i1> {
434 let PrintMethod = "printIdxen";
436 def addr64 : Operand<i1> {
437 let PrintMethod = "printAddr64";
439 def mbuf_offset : Operand<i16> {
440 let PrintMethod = "printMBUFOffset";
441 let ParserMatchClass = MubufOffsetMatchClass;
443 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
444 let PrintMethod = "printDSOffset";
445 let ParserMatchClass = mc;
447 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
448 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
450 def ds_offset0 : Operand<i8> {
451 let PrintMethod = "printDSOffset0";
452 let ParserMatchClass = DSOffset01MatchClass;
454 def ds_offset1 : Operand<i8> {
455 let PrintMethod = "printDSOffset1";
456 let ParserMatchClass = DSOffset01MatchClass;
458 class gds_base <AsmOperandClass mc> : Operand <i1> {
459 let PrintMethod = "printGDS";
460 let ParserMatchClass = mc;
462 def gds : gds_base <GDSMatchClass>;
464 def gds01 : gds_base <GDS01MatchClass>;
466 def glc : Operand <i1> {
467 let PrintMethod = "printGLC";
468 let ParserMatchClass = GLCMatchClass;
470 def slc : Operand <i1> {
471 let PrintMethod = "printSLC";
472 let ParserMatchClass = SLCMatchClass;
474 def tfe : Operand <i1> {
475 let PrintMethod = "printTFE";
476 let ParserMatchClass = TFEMatchClass;
479 def omod : Operand <i32> {
480 let PrintMethod = "printOModSI";
481 let ParserMatchClass = OModMatchClass;
484 def ClampMod : Operand <i1> {
485 let PrintMethod = "printClampSI";
486 let ParserMatchClass = ClampMatchClass;
489 } // End OperandType = "OPERAND_IMMEDIATE"
491 def VOPDstS64 : VOPDstOperand <SReg_64>;
493 //===----------------------------------------------------------------------===//
495 //===----------------------------------------------------------------------===//
497 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
498 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
500 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
501 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
502 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
503 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
504 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
505 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
507 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
508 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
509 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
510 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
512 //===----------------------------------------------------------------------===//
513 // SI assembler operands
514 //===----------------------------------------------------------------------===//
535 //===----------------------------------------------------------------------===//
537 // SI Instruction multiclass helpers.
539 // Instructions with _32 take 32-bit operands.
540 // Instructions with _64 take 64-bit operands.
542 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
543 // encoding is the standard encoding, but instruction that make use of
544 // any of the instruction modifiers must use the 64-bit encoding.
546 // Instructions with _e32 use the 32-bit encoding.
547 // Instructions with _e64 use the 64-bit encoding.
549 //===----------------------------------------------------------------------===//
551 class SIMCInstr <string pseudo, int subtarget> {
552 string PseudoInstr = pseudo;
553 int Subtarget = subtarget;
556 //===----------------------------------------------------------------------===//
558 //===----------------------------------------------------------------------===//
560 class EXPCommon : InstSI<
562 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
563 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
564 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
573 let isPseudo = 1, isCodeGenOnly = 1 in {
574 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
577 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
579 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
582 //===----------------------------------------------------------------------===//
584 //===----------------------------------------------------------------------===//
586 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
587 SOP1 <outs, ins, "", pattern>,
588 SIMCInstr<opName, SISubtarget.NONE> {
590 let isCodeGenOnly = 1;
593 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
594 SOP1 <outs, ins, asm, []>,
596 SIMCInstr<opName, SISubtarget.SI> {
597 let isCodeGenOnly = 0;
598 let AssemblerPredicates = [isSICI];
601 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
602 SOP1 <outs, ins, asm, []>,
604 SIMCInstr<opName, SISubtarget.VI> {
605 let isCodeGenOnly = 0;
606 let AssemblerPredicates = [isVI];
609 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
612 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
614 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
616 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
620 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
621 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
622 opName#" $dst, $src0", pattern
625 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
626 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
627 opName#" $dst, $src0", pattern
630 // no input, 64-bit output.
631 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
632 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
634 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
639 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
645 // 64-bit input, no output
646 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
647 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
649 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
654 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
660 // 64-bit input, 32-bit output.
661 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
662 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
663 opName#" $dst, $src0", pattern
666 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
667 SOP2<outs, ins, "", pattern>,
668 SIMCInstr<opName, SISubtarget.NONE> {
670 let isCodeGenOnly = 1;
673 // Pseudo instructions have no encodings, but adding this field here allows
675 // let sdst = xxx in {
676 // for multiclasses that include both real and pseudo instructions.
677 field bits<7> sdst = 0;
680 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
681 SOP2<outs, ins, asm, []>,
683 SIMCInstr<opName, SISubtarget.SI> {
684 let AssemblerPredicates = [isSICI];
687 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
688 SOP2<outs, ins, asm, []>,
690 SIMCInstr<opName, SISubtarget.VI> {
691 let AssemblerPredicates = [isVI];
694 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
695 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
696 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
698 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
699 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
700 opName#" $dst, $src0, $src1 [$scc]">;
702 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
703 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
704 opName#" $dst, $src0, $src1 [$scc]">;
707 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
710 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
712 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
714 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
718 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
719 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
720 opName#" $dst, $src0, $src1", pattern
723 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
724 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
725 opName#" $dst, $src0, $src1", pattern
728 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
729 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
730 opName#" $dst, $src0, $src1", pattern
733 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
734 string opName, PatLeaf cond> : SOPC <
735 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
736 opName#" $src0, $src1", []>;
738 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
739 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
741 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
742 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
744 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
745 SOPK <outs, ins, "", pattern>,
746 SIMCInstr<opName, SISubtarget.NONE> {
748 let isCodeGenOnly = 1;
751 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
752 SOPK <outs, ins, asm, []>,
754 SIMCInstr<opName, SISubtarget.SI> {
755 let AssemblerPredicates = [isSICI];
756 let isCodeGenOnly = 0;
759 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
760 SOPK <outs, ins, asm, []>,
762 SIMCInstr<opName, SISubtarget.VI> {
763 let AssemblerPredicates = [isVI];
764 let isCodeGenOnly = 0;
767 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
768 string asm = opName#opAsm> {
769 def "" : SOPK_Pseudo <opName, outs, ins, []>;
771 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
773 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
777 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
778 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
781 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
782 opName#" $dst, $src0">;
784 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
785 opName#" $dst, $src0">;
788 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
789 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
790 (ins SReg_32:$src0, u16imm:$src1), pattern>;
792 let DisableEncoding = "$dst" in {
793 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
794 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
796 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
797 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
801 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
802 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
806 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
807 string argAsm, string asm = opName#argAsm> {
809 def "" : SOPK_Pseudo <opName, outs, ins, []>;
811 def _si : SOPK <outs, ins, asm, []>,
813 SIMCInstr<opName, SISubtarget.SI> {
814 let AssemblerPredicates = [isSICI];
815 let isCodeGenOnly = 0;
818 def _vi : SOPK <outs, ins, asm, []>,
820 SIMCInstr<opName, SISubtarget.VI> {
821 let AssemblerPredicates = [isVI];
822 let isCodeGenOnly = 0;
825 //===----------------------------------------------------------------------===//
827 //===----------------------------------------------------------------------===//
829 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
830 SMRD <outs, ins, "", pattern>,
831 SIMCInstr<opName, SISubtarget.NONE> {
833 let isCodeGenOnly = 1;
836 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
838 SMRD <outs, ins, asm, []>,
840 SIMCInstr<opName, SISubtarget.SI> {
841 let AssemblerPredicates = [isSICI];
844 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
846 SMRD <outs, ins, asm, []>,
848 SIMCInstr<opName, SISubtarget.VI> {
849 let AssemblerPredicates = [isVI];
852 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
853 string asm, list<dag> pattern> {
855 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
857 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
859 // glc is only applicable to scalar stores, which are not yet
862 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
866 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
867 RegisterClass dstClass> {
869 op, opName#"_IMM", 1, (outs dstClass:$dst),
870 (ins baseClass:$sbase, u32imm:$offset),
871 opName#" $dst, $sbase, $offset", []
874 defm _SGPR : SMRD_m <
875 op, opName#"_SGPR", 0, (outs dstClass:$dst),
876 (ins baseClass:$sbase, SReg_32:$soff),
877 opName#" $dst, $sbase, $soff", []
881 //===----------------------------------------------------------------------===//
882 // Vector ALU classes
883 //===----------------------------------------------------------------------===//
885 // This must always be right before the operand being input modified.
886 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
887 let PrintMethod = "printOperandAndMods";
890 def InputModsMatchClass : AsmOperandClass {
891 let Name = "RegWithInputMods";
894 def InputModsNoDefault : Operand <i32> {
895 let PrintMethod = "printOperandAndMods";
896 let ParserMatchClass = InputModsMatchClass;
899 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
901 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
902 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
906 // Returns the register class to use for the destination of VOP[123C]
907 // instructions for the given VT.
908 class getVALUDstForVT<ValueType VT> {
909 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
910 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
911 VOPDstOperand<SReg_64>)); // else VT == i1
914 // Returns the register class to use for source 0 of VOP[12C]
915 // instructions for the given VT.
916 class getVOPSrc0ForVT<ValueType VT> {
917 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
920 // Returns the register class to use for source 1 of VOP[12C] for the
922 class getVOPSrc1ForVT<ValueType VT> {
923 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
926 // Returns the register class to use for sources of VOP3 instructions for the
928 class getVOP3SrcForVT<ValueType VT> {
929 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
932 // Returns 1 if the source arguments have modifiers, 0 if they do not.
933 class hasModifiers<ValueType SrcVT> {
934 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
935 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
938 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
939 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
940 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
941 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
945 // Returns the input arguments for VOP3 instructions for the given SrcVT.
946 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
947 RegisterOperand Src2RC, int NumSrcArgs,
951 !if (!eq(NumSrcArgs, 1),
952 !if (!eq(HasModifiers, 1),
953 // VOP1 with modifiers
954 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
955 ClampMod:$clamp, omod:$omod)
957 // VOP1 without modifiers
960 !if (!eq(NumSrcArgs, 2),
961 !if (!eq(HasModifiers, 1),
962 // VOP 2 with modifiers
963 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
964 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
965 ClampMod:$clamp, omod:$omod)
967 // VOP2 without modifiers
968 (ins Src0RC:$src0, Src1RC:$src1)
970 /* NumSrcArgs == 3 */,
971 !if (!eq(HasModifiers, 1),
972 // VOP3 with modifiers
973 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
974 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
975 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
976 ClampMod:$clamp, omod:$omod)
978 // VOP3 without modifiers
979 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
983 // Returns the assembly string for the inputs and outputs of a VOP[12C]
984 // instruction. This does not add the _e32 suffix, so it can be reused
986 class getAsm32 <int NumSrcArgs> {
987 string src1 = ", $src1";
988 string src2 = ", $src2";
989 string ret = "$dst, $src0"#
990 !if(!eq(NumSrcArgs, 1), "", src1)#
991 !if(!eq(NumSrcArgs, 3), src2, "");
994 // Returns the assembly string for the inputs and outputs of a VOP3
996 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
997 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
998 string src1 = !if(!eq(NumSrcArgs, 1), "",
999 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1000 " $src1_modifiers,"));
1001 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1003 !if(!eq(HasModifiers, 0),
1004 getAsm32<NumSrcArgs>.ret,
1005 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1009 class VOPProfile <list<ValueType> _ArgVT> {
1011 field list<ValueType> ArgVT = _ArgVT;
1013 field ValueType DstVT = ArgVT[0];
1014 field ValueType Src0VT = ArgVT[1];
1015 field ValueType Src1VT = ArgVT[2];
1016 field ValueType Src2VT = ArgVT[3];
1017 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1018 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1019 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1020 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1021 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1022 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1024 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
1025 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1027 field dag Outs = (outs DstRC:$dst);
1029 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1030 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1033 field string Asm32 = getAsm32<NumSrcArgs>.ret;
1034 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
1037 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
1038 // for the instruction patterns to work.
1039 def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
1040 def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
1041 def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
1043 def VOP_F16_F16_F16 : VOPProfile <[f32, f32, f32, untyped]>;
1044 def VOP_F16_F16_I16 : VOPProfile <[f32, f32, i32, untyped]>;
1045 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1047 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1048 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1049 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1050 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1051 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1052 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1053 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1054 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1055 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1057 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1058 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1059 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1060 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1061 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1062 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1063 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1064 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
1065 let Src0RC32 = VCSrc_32;
1068 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
1069 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1070 let Asm64 = "$dst, $src0_modifiers, $src1";
1073 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
1074 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1075 let Asm64 = "$dst, $src0_modifiers, $src1";
1078 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1079 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1080 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1081 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1082 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
1083 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1084 let Asm64 = "$dst, $src0, $src1, $src2";
1087 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1088 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1089 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1090 field string Asm = "$dst, $src0, $vsrc1, $src2";
1092 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1093 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1094 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1097 class VOP <string opName> {
1098 string OpName = opName;
1101 class VOP2_REV <string revOp, bit isOrig> {
1102 string RevOp = revOp;
1103 bit IsOrig = isOrig;
1106 class AtomicNoRet <string noRetOp, bit isRet> {
1107 string NoRetOp = noRetOp;
1111 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1112 VOP1Common <outs, ins, "", pattern>,
1114 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1115 MnemonicAlias<opName#"_e32", opName> {
1117 let isCodeGenOnly = 1;
1123 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1124 VOP1<op.SI, outs, ins, asm, []>,
1125 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1126 let AssemblerPredicate = SIAssemblerPredicate;
1129 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1130 VOP1<op.VI, outs, ins, asm, []>,
1131 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1132 let AssemblerPredicates = [isVI];
1135 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1137 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1139 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1141 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1144 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1146 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1148 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1151 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1152 VOP2Common <outs, ins, "", pattern>,
1154 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1155 MnemonicAlias<opName#"_e32", opName> {
1157 let isCodeGenOnly = 1;
1160 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1161 VOP2 <op.SI, outs, ins, opName#asm, []>,
1162 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1163 let AssemblerPredicates = [isSICI];
1166 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1167 VOP2 <op.VI, outs, ins, opName#asm, []>,
1168 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1169 let AssemblerPredicates = [isVI];
1172 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1173 string opName, string revOp> {
1174 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1175 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1177 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1180 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1181 string opName, string revOp> {
1182 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1183 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1185 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1187 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1191 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1193 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1194 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1195 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1196 bits<2> omod = !if(HasModifiers, ?, 0);
1197 bits<1> clamp = !if(HasModifiers, ?, 0);
1198 bits<9> src1 = !if(HasSrc1, ?, 0);
1199 bits<9> src2 = !if(HasSrc2, ?, 0);
1202 class VOP3DisableModFields <bit HasSrc0Mods,
1203 bit HasSrc1Mods = 0,
1204 bit HasSrc2Mods = 0,
1205 bit HasOutputMods = 0> {
1206 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1207 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1208 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1209 bits<2> omod = !if(HasOutputMods, ?, 0);
1210 bits<1> clamp = !if(HasOutputMods, ?, 0);
1213 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1214 VOP3Common <outs, ins, "", pattern>,
1216 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1217 MnemonicAlias<opName#"_e64", opName> {
1219 let isCodeGenOnly = 1;
1222 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1223 VOP3Common <outs, ins, asm, []>,
1225 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1226 let AssemblerPredicates = [isSICI];
1229 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1230 VOP3Common <outs, ins, asm, []>,
1232 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1233 let AssemblerPredicates = [isVI];
1236 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1237 VOP3Common <outs, ins, asm, []>,
1239 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1240 let AssemblerPredicates = [isSICI];
1243 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1244 VOP3Common <outs, ins, asm, []>,
1246 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1247 let AssemblerPredicates = [isVI];
1250 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1251 string opName, int NumSrcArgs, bit HasMods = 1> {
1253 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1255 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1256 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1257 !if(!eq(NumSrcArgs, 2), 0, 1),
1259 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1260 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1261 !if(!eq(NumSrcArgs, 2), 0, 1),
1265 // VOP3_m without source modifiers
1266 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1267 string opName, int NumSrcArgs, bit HasMods = 1> {
1269 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1271 let src0_modifiers = 0,
1276 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1277 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1281 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1282 list<dag> pattern, string opName, bit HasMods = 1> {
1284 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1286 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1287 VOP3DisableFields<0, 0, HasMods>;
1289 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1290 VOP3DisableFields<0, 0, HasMods>;
1293 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1294 list<dag> pattern, string opName, bit HasMods = 1> {
1296 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1298 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1299 VOP3DisableFields<0, 0, HasMods>;
1300 // No VI instruction. This class is for SI only.
1303 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1304 list<dag> pattern, string opName, string revOp,
1305 bit HasMods = 1, bit UseFullOp = 0> {
1307 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1308 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1310 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1311 VOP3DisableFields<1, 0, HasMods>;
1313 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1314 VOP3DisableFields<1, 0, HasMods>;
1317 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1318 list<dag> pattern, string opName, string revOp,
1319 bit HasMods = 1, bit UseFullOp = 0> {
1321 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1322 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1324 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1325 VOP3DisableFields<1, 0, HasMods>;
1327 // No VI instruction. This class is for SI only.
1330 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1331 // option of implicit vcc use?
1332 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1333 list<dag> pattern, string opName, string revOp,
1334 bit HasMods = 1, bit UseFullOp = 0> {
1335 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1336 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1338 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1339 // can write it into any SGPR. We currently don't use the carry out,
1340 // so for now hardcode it to VCC as well.
1341 let sdst = SIOperand.VCC, Defs = [VCC] in {
1342 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1343 VOP3DisableFields<1, 0, HasMods>;
1345 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1346 VOP3DisableFields<1, 0, HasMods>;
1347 } // End sdst = SIOperand.VCC, Defs = [VCC]
1350 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1351 list<dag> pattern, string opName, string revOp,
1352 bit HasMods = 1, bit UseFullOp = 0> {
1353 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1356 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1357 VOP3DisableFields<1, 1, HasMods>;
1359 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1360 VOP3DisableFields<1, 1, HasMods>;
1363 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1364 list<dag> pattern, string opName,
1365 bit HasMods, bit defExec, string revOp> {
1367 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1368 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1370 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1371 VOP3DisableFields<1, 0, HasMods> {
1372 let Defs = !if(defExec, [EXEC], []);
1375 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1376 VOP3DisableFields<1, 0, HasMods> {
1377 let Defs = !if(defExec, [EXEC], []);
1381 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1382 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1383 string asm, list<dag> pattern = []> {
1384 let isPseudo = 1, isCodeGenOnly = 1 in {
1385 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1386 SIMCInstr<opName, SISubtarget.NONE>;
1389 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1390 SIMCInstr <opName, SISubtarget.SI> {
1391 let AssemblerPredicates = [isSICI];
1394 def _vi : VOP3Common <outs, ins, asm, []>,
1396 VOP3DisableFields <1, 0, 0>,
1397 SIMCInstr <opName, SISubtarget.VI> {
1398 let AssemblerPredicates = [isVI];
1402 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1403 dag ins32, string asm32, list<dag> pat32,
1404 dag ins64, string asm64, list<dag> pat64,
1407 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1409 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1412 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1413 SDPatternOperator node = null_frag> : VOP1_Helper <
1415 P.Ins32, P.Asm32, [],
1418 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1419 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1420 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1424 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1425 SDPatternOperator node = null_frag> {
1427 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1429 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1431 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1432 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1433 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1434 opName, P.HasModifiers>;
1437 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1438 dag ins32, string asm32, list<dag> pat32,
1439 dag ins64, string asm64, list<dag> pat64,
1440 string revOp, bit HasMods> {
1441 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1443 defm _e64 : VOP3_2_m <op,
1444 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1448 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1449 SDPatternOperator node = null_frag,
1450 string revOp = opName> : VOP2_Helper <
1452 P.Ins32, P.Asm32, [],
1456 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1457 i1:$clamp, i32:$omod)),
1458 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1459 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1460 revOp, P.HasModifiers
1463 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1464 SDPatternOperator node = null_frag,
1465 string revOp = opName> {
1466 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1468 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1471 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1472 i1:$clamp, i32:$omod)),
1473 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1474 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1475 opName, revOp, P.HasModifiers>;
1478 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1479 dag ins32, string asm32, list<dag> pat32,
1480 dag ins64, string asm64, list<dag> pat64,
1481 string revOp, bit HasMods> {
1483 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1485 defm _e64 : VOP3b_2_m <op,
1486 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1490 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1491 SDPatternOperator node = null_frag,
1492 string revOp = opName> : VOP2b_Helper <
1494 P.Ins32, P.Asm32, [],
1498 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1499 i1:$clamp, i32:$omod)),
1500 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1501 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1502 revOp, P.HasModifiers
1505 // A VOP2 instruction that is VOP3-only on VI.
1506 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1507 dag ins32, string asm32, list<dag> pat32,
1508 dag ins64, string asm64, list<dag> pat64,
1509 string revOp, bit HasMods> {
1510 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1512 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1516 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1517 SDPatternOperator node = null_frag,
1518 string revOp = opName>
1521 P.Ins32, P.Asm32, [],
1525 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1526 i1:$clamp, i32:$omod)),
1527 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1528 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1529 revOp, P.HasModifiers
1532 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1534 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1536 let isCodeGenOnly = 0 in {
1537 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1538 !strconcat(opName, VOP_MADK.Asm), []>,
1539 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1540 VOP2_MADKe <op.SI> {
1541 let AssemblerPredicates = [isSICI];
1544 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1545 !strconcat(opName, VOP_MADK.Asm), []>,
1546 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1547 VOP2_MADKe <op.VI> {
1548 let AssemblerPredicates = [isVI];
1550 } // End isCodeGenOnly = 0
1553 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1554 VOPCCommon <ins, "", pattern>,
1556 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1557 MnemonicAlias<opName#"_e32", opName> {
1559 let isCodeGenOnly = 1;
1562 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1563 string opName, bit DefExec, string revOpName = ""> {
1564 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1566 def _si : VOPC<op.SI, ins, asm, []>,
1567 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1568 let Defs = !if(DefExec, [EXEC], []);
1569 let hasSideEffects = DefExec;
1572 def _vi : VOPC<op.VI, ins, asm, []>,
1573 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1574 let Defs = !if(DefExec, [EXEC], []);
1575 let hasSideEffects = DefExec;
1579 multiclass VOPC_Helper <vopc op, string opName,
1580 dag ins32, string asm32, list<dag> pat32,
1581 dag out64, dag ins64, string asm64, list<dag> pat64,
1582 bit HasMods, bit DefExec, string revOp> {
1583 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1585 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1586 opName, HasMods, DefExec, revOp>;
1589 // Special case for class instructions which only have modifiers on
1590 // the 1st source operand.
1591 multiclass VOPC_Class_Helper <vopc op, string opName,
1592 dag ins32, string asm32, list<dag> pat32,
1593 dag out64, dag ins64, string asm64, list<dag> pat64,
1594 bit HasMods, bit DefExec, string revOp> {
1595 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1597 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1598 opName, HasMods, DefExec, revOp>,
1599 VOP3DisableModFields<1, 0, 0>;
1602 multiclass VOPCInst <vopc op, string opName,
1603 VOPProfile P, PatLeaf cond = COND_NULL,
1604 string revOp = opName,
1605 bit DefExec = 0> : VOPC_Helper <
1607 P.Ins32, P.Asm32, [],
1608 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1611 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1612 i1:$clamp, i32:$omod)),
1613 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1615 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1616 P.HasModifiers, DefExec, revOp
1619 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1620 bit DefExec = 0> : VOPC_Class_Helper <
1622 P.Ins32, P.Asm32, [],
1623 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1626 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1627 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1628 P.HasModifiers, DefExec, opName
1632 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1633 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1635 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1636 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1638 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1639 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1641 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1642 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1645 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1646 PatLeaf cond = COND_NULL,
1648 : VOPCInst <op, opName, P, cond, revOp, 1>;
1650 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1651 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1653 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1654 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1656 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1657 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1659 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1660 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1662 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1663 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1664 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1667 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1668 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1670 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1671 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1673 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1674 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1676 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1677 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1679 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1680 SDPatternOperator node = null_frag> : VOP3_Helper <
1681 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1682 !if(!eq(P.NumSrcArgs, 3),
1685 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1686 i1:$clamp, i32:$omod)),
1687 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1688 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1689 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1691 !if(!eq(P.NumSrcArgs, 2),
1694 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1695 i1:$clamp, i32:$omod)),
1696 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1697 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1698 /* P.NumSrcArgs == 1 */,
1701 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1702 i1:$clamp, i32:$omod))))],
1703 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1704 P.NumSrcArgs, P.HasModifiers
1707 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1708 // only VOP instruction that implicitly reads VCC.
1709 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1711 SDPatternOperator node = null_frag> : VOP3_Helper <
1713 (outs P.DstRC.RegClass:$dst),
1714 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1715 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1716 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1719 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1721 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1722 i1:$clamp, i32:$omod)),
1723 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1724 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1729 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1730 string opName, list<dag> pattern> :
1732 op, (outs vrc:$vdst, SReg_64:$sdst),
1733 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1734 InputModsNoDefault:$src1_modifiers, arc:$src1,
1735 InputModsNoDefault:$src2_modifiers, arc:$src2,
1736 ClampMod:$clamp, omod:$omod),
1737 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1738 opName, opName, 1, 1
1741 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1742 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1744 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1745 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1748 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1749 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1750 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1751 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1752 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1753 i32:$src1_modifiers, P.Src1VT:$src1,
1754 i32:$src2_modifiers, P.Src2VT:$src2,
1758 //===----------------------------------------------------------------------===//
1759 // Interpolation opcodes
1760 //===----------------------------------------------------------------------===//
1762 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1763 VINTRPCommon <outs, ins, "", pattern>,
1764 SIMCInstr<opName, SISubtarget.NONE> {
1766 let isCodeGenOnly = 1;
1769 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1771 VINTRPCommon <outs, ins, asm, []>,
1773 SIMCInstr<opName, SISubtarget.SI>;
1775 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1777 VINTRPCommon <outs, ins, asm, []>,
1779 SIMCInstr<opName, SISubtarget.VI>;
1781 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1782 list<dag> pattern = []> {
1783 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1785 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1787 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1790 //===----------------------------------------------------------------------===//
1791 // Vector I/O classes
1792 //===----------------------------------------------------------------------===//
1794 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1795 DS <outs, ins, "", pattern>,
1796 SIMCInstr <opName, SISubtarget.NONE> {
1798 let isCodeGenOnly = 1;
1801 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1802 DS <outs, ins, asm, []>,
1804 SIMCInstr <opName, SISubtarget.SI> {
1805 let isCodeGenOnly = 0;
1808 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1809 DS <outs, ins, asm, []>,
1811 SIMCInstr <opName, SISubtarget.VI>;
1813 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1814 DS_Real_si <op,opName, outs, ins, asm> {
1816 // Single load interpret the 2 i8imm operands as a single i16 offset.
1818 let offset0 = offset{7-0};
1819 let offset1 = offset{15-8};
1820 let isCodeGenOnly = 0;
1823 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1824 DS_Real_vi <op, opName, outs, ins, asm> {
1826 // Single load interpret the 2 i8imm operands as a single i16 offset.
1828 let offset0 = offset{7-0};
1829 let offset1 = offset{15-8};
1832 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1833 dag outs = (outs rc:$vdst),
1834 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
1835 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1837 def "" : DS_Pseudo <opName, outs, ins, []>;
1839 let data0 = 0, data1 = 0 in {
1840 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1841 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1845 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1846 dag outs = (outs rc:$vdst),
1847 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1849 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1851 def "" : DS_Pseudo <opName, outs, ins, []>;
1853 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1854 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1855 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1859 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1861 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1862 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1864 def "" : DS_Pseudo <opName, outs, ins, []>,
1865 AtomicNoRet<opName, 0>;
1867 let data1 = 0, vdst = 0 in {
1868 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1869 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1873 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1875 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1876 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
1877 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1879 def "" : DS_Pseudo <opName, outs, ins, []>;
1881 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1882 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1883 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1887 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1888 string noRetOp = "",
1889 dag outs = (outs rc:$vdst),
1890 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1891 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1893 def "" : DS_Pseudo <opName, outs, ins, []>,
1894 AtomicNoRet<noRetOp, 1>;
1897 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1898 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1902 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1903 string noRetOp = "", dag ins,
1904 dag outs = (outs rc:$vdst),
1905 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1907 def "" : DS_Pseudo <opName, outs, ins, []>,
1908 AtomicNoRet<noRetOp, 1>;
1910 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1911 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1914 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1915 string noRetOp = "", RegisterClass src = rc> :
1916 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1917 (ins VGPR_32:$addr, src:$data0, src:$data1,
1918 ds_offset:$offset, gds:$gds)
1921 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1922 string noRetOp = opName,
1924 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1925 ds_offset:$offset, gds:$gds),
1926 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1928 def "" : DS_Pseudo <opName, outs, ins, []>,
1929 AtomicNoRet<noRetOp, 0>;
1932 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1933 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1937 multiclass DS_0A_RET <bits<8> op, string opName,
1938 dag outs = (outs VGPR_32:$vdst),
1939 dag ins = (ins ds_offset:$offset, gds:$gds),
1940 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1942 let mayLoad = 1, mayStore = 1 in {
1943 def "" : DS_Pseudo <opName, outs, ins, []>;
1945 let addr = 0, data0 = 0, data1 = 0 in {
1946 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1947 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1948 } // end addr = 0, data0 = 0, data1 = 0
1949 } // end mayLoad = 1, mayStore = 1
1952 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1953 dag outs = (outs VGPR_32:$vdst),
1954 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
1955 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1957 def "" : DS_Pseudo <opName, outs, ins, []>;
1959 let data0 = 0, data1 = 0, gds = 1 in {
1960 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1961 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1962 } // end data0 = 0, data1 = 0, gds = 1
1965 multiclass DS_1A_GDS <bits<8> op, string opName,
1967 dag ins = (ins VGPR_32:$addr),
1968 string asm = opName#" $addr gds"> {
1970 def "" : DS_Pseudo <opName, outs, ins, []>;
1972 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1973 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1974 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1975 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1978 multiclass DS_1A <bits<8> op, string opName,
1980 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
1981 string asm = opName#" $addr"#"$offset"#"$gds"> {
1983 let mayLoad = 1, mayStore = 1 in {
1984 def "" : DS_Pseudo <opName, outs, ins, []>;
1986 let vdst = 0, data0 = 0, data1 = 0 in {
1987 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1988 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1989 } // let vdst = 0, data0 = 0, data1 = 0
1990 } // end mayLoad = 1, mayStore = 1
1993 //===----------------------------------------------------------------------===//
1995 //===----------------------------------------------------------------------===//
1997 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1998 MTBUF <outs, ins, "", pattern>,
1999 SIMCInstr<opName, SISubtarget.NONE> {
2001 let isCodeGenOnly = 1;
2004 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2006 MTBUF <outs, ins, asm, []>,
2008 SIMCInstr<opName, SISubtarget.SI>;
2010 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2011 MTBUF <outs, ins, asm, []>,
2013 SIMCInstr <opName, SISubtarget.VI>;
2015 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2016 list<dag> pattern> {
2018 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2020 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2022 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2026 let mayStore = 1, mayLoad = 0 in {
2028 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2029 RegisterClass regClass> : MTBUF_m <
2031 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2032 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2033 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2034 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2035 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2038 } // mayStore = 1, mayLoad = 0
2040 let mayLoad = 1, mayStore = 0 in {
2042 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2043 RegisterClass regClass> : MTBUF_m <
2044 op, opName, (outs regClass:$dst),
2045 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2046 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2047 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2048 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2049 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2052 } // mayLoad = 1, mayStore = 0
2054 //===----------------------------------------------------------------------===//
2056 //===----------------------------------------------------------------------===//
2058 class mubuf <bits<7> si, bits<7> vi = si> {
2059 field bits<7> SI = si;
2060 field bits<7> VI = vi;
2063 let isCodeGenOnly = 0 in {
2065 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2066 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2070 } // End let isCodeGenOnly = 0
2072 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2073 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2077 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2078 bit IsAddr64 = is_addr64;
2079 string OpName = NAME # suffix;
2082 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2083 MUBUF <outs, ins, "", pattern>,
2084 SIMCInstr<opName, SISubtarget.NONE> {
2086 let isCodeGenOnly = 1;
2088 // dummy fields, so that we can use let statements around multiclasses
2098 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2100 MUBUF <outs, ins, asm, []>,
2102 SIMCInstr<opName, SISubtarget.SI> {
2106 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2108 MUBUF <outs, ins, asm, []>,
2110 SIMCInstr<opName, SISubtarget.VI> {
2114 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2115 list<dag> pattern> {
2117 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2118 MUBUFAddr64Table <0>;
2120 let addr64 = 0, isCodeGenOnly = 0 in {
2121 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2124 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2127 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2128 dag ins, string asm, list<dag> pattern> {
2130 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2131 MUBUFAddr64Table <1>;
2133 let addr64 = 1, isCodeGenOnly = 0 in {
2134 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2137 // There is no VI version. If the pseudo is selected, it should be lowered
2138 // for VI appropriately.
2141 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2142 string asm, list<dag> pattern, bit is_return> {
2144 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2145 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2146 AtomicNoRet<NAME#"_OFFSET", is_return>;
2148 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2150 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2153 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2157 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2158 string asm, list<dag> pattern, bit is_return> {
2160 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2161 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2162 AtomicNoRet<NAME#"_ADDR64", is_return>;
2164 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2165 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2168 // There is no VI version. If the pseudo is selected, it should be lowered
2169 // for VI appropriately.
2172 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2173 ValueType vt, SDPatternOperator atomic> {
2175 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2177 // No return variants
2180 defm _ADDR64 : MUBUFAtomicAddr64_m <
2181 op, name#"_addr64", (outs),
2182 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2183 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2184 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2187 defm _OFFSET : MUBUFAtomicOffset_m <
2188 op, name#"_offset", (outs),
2189 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2191 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2195 // Variant that return values
2196 let glc = 1, Constraints = "$vdata = $vdata_in",
2197 DisableEncoding = "$vdata_in" in {
2199 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2200 op, name#"_rtn_addr64", (outs rc:$vdata),
2201 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2202 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2203 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2205 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2206 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2209 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2210 op, name#"_rtn_offset", (outs rc:$vdata),
2211 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2212 mbuf_offset:$offset, slc:$slc),
2213 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2215 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2216 i1:$slc), vt:$vdata_in))], 1
2221 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2224 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2225 ValueType load_vt = i32,
2226 SDPatternOperator ld = null_frag> {
2228 let mayLoad = 1, mayStore = 0 in {
2229 let offen = 0, idxen = 0, vaddr = 0 in {
2230 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2231 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2232 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2233 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2234 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2235 i32:$soffset, i16:$offset,
2236 i1:$glc, i1:$slc, i1:$tfe)))]>;
2239 let offen = 1, idxen = 0 in {
2240 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2241 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2242 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2244 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2247 let offen = 0, idxen = 1 in {
2248 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2249 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2250 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2251 slc:$slc, tfe:$tfe),
2252 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2255 let offen = 1, idxen = 1 in {
2256 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2257 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2258 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2259 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2262 let offen = 0, idxen = 0 in {
2263 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2264 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2265 SCSrc_32:$soffset, mbuf_offset:$offset,
2266 glc:$glc, slc:$slc, tfe:$tfe),
2267 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2268 "$glc"#"$slc"#"$tfe",
2269 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2270 i64:$vaddr, i32:$soffset,
2271 i16:$offset, i1:$glc, i1:$slc,
2277 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2278 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2279 let mayLoad = 0, mayStore = 1 in {
2280 defm : MUBUF_m <op, name, (outs),
2281 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2282 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2284 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2285 "$glc"#"$slc"#"$tfe", []>;
2287 let offen = 0, idxen = 0, vaddr = 0 in {
2288 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2289 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2290 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2291 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2292 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2293 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2294 } // offen = 0, idxen = 0, vaddr = 0
2296 let offen = 1, idxen = 0 in {
2297 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2298 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2299 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2300 slc:$slc, tfe:$tfe),
2301 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2302 "$glc"#"$slc"#"$tfe", []>;
2303 } // end offen = 1, idxen = 0
2305 let offen = 0, idxen = 1 in {
2306 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2307 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2308 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2309 slc:$slc, tfe:$tfe),
2310 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2313 let offen = 1, idxen = 1 in {
2314 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2315 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2316 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2317 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2320 let offen = 0, idxen = 0 in {
2321 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2322 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2324 mbuf_offset:$offset, glc:$glc, slc:$slc,
2326 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2327 "$offset"#"$glc"#"$slc"#"$tfe",
2328 [(st store_vt:$vdata,
2329 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2330 i32:$soffset, i16:$offset,
2331 i1:$glc, i1:$slc, i1:$tfe))]>;
2333 } // End mayLoad = 0, mayStore = 1
2336 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2337 FLAT <op, (outs regClass:$vdst),
2338 (ins VReg_64:$addr),
2339 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2347 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2348 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2349 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2362 class MIMG_Mask <string op, int channels> {
2364 int Channels = channels;
2367 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2368 RegisterClass dst_rc,
2369 RegisterClass src_rc> : MIMG <
2371 (outs dst_rc:$vdata),
2372 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2373 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2375 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2376 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2381 let hasPostISelHook = 1;
2384 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2385 RegisterClass dst_rc,
2387 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2388 MIMG_Mask<asm#"_V1", channels>;
2389 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2390 MIMG_Mask<asm#"_V2", channels>;
2391 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2392 MIMG_Mask<asm#"_V4", channels>;
2395 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2396 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2397 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2398 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2399 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2402 class MIMG_Sampler_Helper <bits<7> op, string asm,
2403 RegisterClass dst_rc,
2404 RegisterClass src_rc, int wqm> : MIMG <
2406 (outs dst_rc:$vdata),
2407 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2408 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2409 SReg_256:$srsrc, SReg_128:$ssamp),
2410 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2411 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2415 let hasPostISelHook = 1;
2419 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2420 RegisterClass dst_rc,
2421 int channels, int wqm> {
2422 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2423 MIMG_Mask<asm#"_V1", channels>;
2424 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2425 MIMG_Mask<asm#"_V2", channels>;
2426 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2427 MIMG_Mask<asm#"_V4", channels>;
2428 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2429 MIMG_Mask<asm#"_V8", channels>;
2430 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2431 MIMG_Mask<asm#"_V16", channels>;
2434 multiclass MIMG_Sampler <bits<7> op, string asm> {
2435 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2436 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2437 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2438 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2441 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2442 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2443 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2444 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2445 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2448 class MIMG_Gather_Helper <bits<7> op, string asm,
2449 RegisterClass dst_rc,
2450 RegisterClass src_rc, int wqm> : MIMG <
2452 (outs dst_rc:$vdata),
2453 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2454 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2455 SReg_256:$srsrc, SReg_128:$ssamp),
2456 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2457 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2462 // DMASK was repurposed for GATHER4. 4 components are always
2463 // returned and DMASK works like a swizzle - it selects
2464 // the component to fetch. The only useful DMASK values are
2465 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2466 // (red,red,red,red) etc.) The ISA document doesn't mention
2468 // Therefore, disable all code which updates DMASK by setting these two:
2470 let hasPostISelHook = 0;
2474 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2475 RegisterClass dst_rc,
2476 int channels, int wqm> {
2477 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2478 MIMG_Mask<asm#"_V1", channels>;
2479 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2480 MIMG_Mask<asm#"_V2", channels>;
2481 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2482 MIMG_Mask<asm#"_V4", channels>;
2483 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2484 MIMG_Mask<asm#"_V8", channels>;
2485 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2486 MIMG_Mask<asm#"_V16", channels>;
2489 multiclass MIMG_Gather <bits<7> op, string asm> {
2490 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2491 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2492 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2493 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2496 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2497 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2498 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2499 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2500 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2503 //===----------------------------------------------------------------------===//
2504 // Vector instruction mappings
2505 //===----------------------------------------------------------------------===//
2507 // Maps an opcode in e32 form to its e64 equivalent
2508 def getVOPe64 : InstrMapping {
2509 let FilterClass = "VOP";
2510 let RowFields = ["OpName"];
2511 let ColFields = ["Size"];
2513 let ValueCols = [["8"]];
2516 // Maps an opcode in e64 form to its e32 equivalent
2517 def getVOPe32 : InstrMapping {
2518 let FilterClass = "VOP";
2519 let RowFields = ["OpName"];
2520 let ColFields = ["Size"];
2522 let ValueCols = [["4"]];
2525 def getMaskedMIMGOp : InstrMapping {
2526 let FilterClass = "MIMG_Mask";
2527 let RowFields = ["Op"];
2528 let ColFields = ["Channels"];
2530 let ValueCols = [["1"], ["2"], ["3"] ];
2533 // Maps an commuted opcode to its original version
2534 def getCommuteOrig : InstrMapping {
2535 let FilterClass = "VOP2_REV";
2536 let RowFields = ["RevOp"];
2537 let ColFields = ["IsOrig"];
2539 let ValueCols = [["1"]];
2542 // Maps an original opcode to its commuted version
2543 def getCommuteRev : InstrMapping {
2544 let FilterClass = "VOP2_REV";
2545 let RowFields = ["RevOp"];
2546 let ColFields = ["IsOrig"];
2548 let ValueCols = [["0"]];
2551 def getCommuteCmpOrig : InstrMapping {
2552 let FilterClass = "VOP2_REV";
2553 let RowFields = ["RevOp"];
2554 let ColFields = ["IsOrig"];
2556 let ValueCols = [["1"]];
2559 // Maps an original opcode to its commuted version
2560 def getCommuteCmpRev : InstrMapping {
2561 let FilterClass = "VOP2_REV";
2562 let RowFields = ["RevOp"];
2563 let ColFields = ["IsOrig"];
2565 let ValueCols = [["0"]];
2569 def getMCOpcodeGen : InstrMapping {
2570 let FilterClass = "SIMCInstr";
2571 let RowFields = ["PseudoInstr"];
2572 let ColFields = ["Subtarget"];
2573 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2574 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2577 def getAddr64Inst : InstrMapping {
2578 let FilterClass = "MUBUFAddr64Table";
2579 let RowFields = ["OpName"];
2580 let ColFields = ["IsAddr64"];
2582 let ValueCols = [["1"]];
2585 // Maps an atomic opcode to its version with a return value.
2586 def getAtomicRetOp : InstrMapping {
2587 let FilterClass = "AtomicNoRet";
2588 let RowFields = ["NoRetOp"];
2589 let ColFields = ["IsRet"];
2591 let ValueCols = [["1"]];
2594 // Maps an atomic opcode to its returnless version.
2595 def getAtomicNoRetOp : InstrMapping {
2596 let FilterClass = "AtomicNoRet";
2597 let RowFields = ["NoRetOp"];
2598 let ColFields = ["IsRet"];
2600 let ValueCols = [["0"]];
2603 include "SIInstructions.td"
2604 include "CIInstructions.td"
2605 include "VIInstructions.td"