1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
44 class sop1 <bits<8> si, bits<8> vi = si> {
45 field bits<8> SI = si;
46 field bits<8> VI = vi;
49 class sop2 <bits<7> si, bits<7> vi = si> {
50 field bits<7> SI = si;
51 field bits<7> VI = vi;
54 class sopk <bits<5> si, bits<5> vi = si> {
55 field bits<5> SI = si;
56 field bits<5> VI = vi;
59 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
60 // in AMDGPUMCInstLower.h
67 //===----------------------------------------------------------------------===//
69 //===----------------------------------------------------------------------===//
71 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
72 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
73 [SDNPMayLoad, SDNPMemOperand]
76 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
78 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
79 SDTCisVT<1, iAny>, // vdata(VGPR)
80 SDTCisVT<2, i32>, // num_channels(imm)
81 SDTCisVT<3, i32>, // vaddr(VGPR)
82 SDTCisVT<4, i32>, // soffset(SGPR)
83 SDTCisVT<5, i32>, // inst_offset(imm)
84 SDTCisVT<6, i32>, // dfmt(imm)
85 SDTCisVT<7, i32>, // nfmt(imm)
86 SDTCisVT<8, i32>, // offen(imm)
87 SDTCisVT<9, i32>, // idxen(imm)
88 SDTCisVT<10, i32>, // glc(imm)
89 SDTCisVT<11, i32>, // slc(imm)
90 SDTCisVT<12, i32> // tfe(imm)
92 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
95 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
100 class SDSample<string opcode> : SDNode <opcode,
101 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
102 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
105 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
106 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
107 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
108 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
110 def SIconstdata_ptr : SDNode<
111 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
114 // Transformation function, extract the lower 32bit of a 64bit immediate
115 def LO32 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
119 def LO32f : SDNodeXForm<fpimm, [{
120 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
121 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
124 // Transformation function, extract the upper 32bit of a 64bit immediate
125 def HI32 : SDNodeXForm<imm, [{
126 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
129 def HI32f : SDNodeXForm<fpimm, [{
130 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
131 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
134 def IMM8bitDWORD : PatLeaf <(imm),
135 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
138 def as_dword_i32imm : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
142 def as_i1imm : SDNodeXForm<imm, [{
143 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
146 def as_i8imm : SDNodeXForm<imm, [{
147 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
150 def as_i16imm : SDNodeXForm<imm, [{
151 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
154 def as_i32imm: SDNodeXForm<imm, [{
155 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
158 def as_i64imm: SDNodeXForm<imm, [{
159 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
162 // Copied from the AArch64 backend:
163 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
164 return CurDAG->getTargetConstant(
165 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
174 def IMM8bit : PatLeaf <(imm),
175 [{return isUInt<8>(N->getZExtValue());}]
178 def IMM12bit : PatLeaf <(imm),
179 [{return isUInt<12>(N->getZExtValue());}]
182 def IMM16bit : PatLeaf <(imm),
183 [{return isUInt<16>(N->getZExtValue());}]
186 def IMM20bit : PatLeaf <(imm),
187 [{return isUInt<20>(N->getZExtValue());}]
190 def IMM32bit : PatLeaf <(imm),
191 [{return isUInt<32>(N->getZExtValue());}]
194 def mubuf_vaddr_offset : PatFrag<
195 (ops node:$ptr, node:$offset, node:$imm_offset),
196 (add (add node:$ptr, node:$offset), node:$imm_offset)
199 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
200 return isInlineImmediate(N);
203 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
204 return isInlineImmediate(N);
207 class SGPRImm <dag frag> : PatLeaf<frag, [{
208 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
209 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
212 const SIRegisterInfo *SIRI =
213 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
214 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
216 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
223 //===----------------------------------------------------------------------===//
225 //===----------------------------------------------------------------------===//
227 def FRAMEri32 : Operand<iPTR> {
228 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
231 def sopp_brtarget : Operand<OtherVT> {
232 let EncoderMethod = "getSOPPBrEncoding";
233 let OperandType = "OPERAND_PCREL";
236 include "SIInstrFormats.td"
237 include "VIInstrFormats.td"
239 let OperandType = "OPERAND_IMMEDIATE" in {
241 def offen : Operand<i1> {
242 let PrintMethod = "printOffen";
244 def idxen : Operand<i1> {
245 let PrintMethod = "printIdxen";
247 def addr64 : Operand<i1> {
248 let PrintMethod = "printAddr64";
250 def mbuf_offset : Operand<i16> {
251 let PrintMethod = "printMBUFOffset";
253 def ds_offset : Operand<i16> {
254 let PrintMethod = "printDSOffset";
256 def ds_offset0 : Operand<i8> {
257 let PrintMethod = "printDSOffset0";
259 def ds_offset1 : Operand<i8> {
260 let PrintMethod = "printDSOffset1";
262 def glc : Operand <i1> {
263 let PrintMethod = "printGLC";
265 def slc : Operand <i1> {
266 let PrintMethod = "printSLC";
268 def tfe : Operand <i1> {
269 let PrintMethod = "printTFE";
272 def omod : Operand <i32> {
273 let PrintMethod = "printOModSI";
276 def ClampMod : Operand <i1> {
277 let PrintMethod = "printClampSI";
280 } // End OperandType = "OPERAND_IMMEDIATE"
282 //===----------------------------------------------------------------------===//
284 //===----------------------------------------------------------------------===//
286 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
287 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
289 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
290 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
291 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
292 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
293 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
294 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
296 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
297 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
298 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
299 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
301 //===----------------------------------------------------------------------===//
302 // SI assembler operands
303 //===----------------------------------------------------------------------===//
323 //===----------------------------------------------------------------------===//
325 // SI Instruction multiclass helpers.
327 // Instructions with _32 take 32-bit operands.
328 // Instructions with _64 take 64-bit operands.
330 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
331 // encoding is the standard encoding, but instruction that make use of
332 // any of the instruction modifiers must use the 64-bit encoding.
334 // Instructions with _e32 use the 32-bit encoding.
335 // Instructions with _e64 use the 64-bit encoding.
337 //===----------------------------------------------------------------------===//
339 class SIMCInstr <string pseudo, int subtarget> {
340 string PseudoInstr = pseudo;
341 int Subtarget = subtarget;
344 //===----------------------------------------------------------------------===//
346 //===----------------------------------------------------------------------===//
348 class EXPCommon : InstSI<
350 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
351 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
352 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
361 let isPseudo = 1 in {
362 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
365 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
367 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
375 SOP1 <outs, ins, "", pattern>,
376 SIMCInstr<opName, SISubtarget.NONE> {
380 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm,
382 SOP1 <outs, ins, asm, pattern>,
384 SIMCInstr<opName, SISubtarget.SI>;
386 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm,
388 SOP1 <outs, ins, asm, pattern>,
390 SIMCInstr<opName, SISubtarget.VI>;
392 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
393 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
396 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
397 opName#" $dst, $src0", pattern>;
399 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
400 opName#" $dst, $src0", pattern>;
403 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
404 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
407 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
408 opName#" $dst, $src0", pattern>;
410 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
411 opName#" $dst, $src0", pattern>;
414 // no input, 64-bit output.
415 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
416 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
418 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
419 opName#" $dst", pattern> {
423 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
424 opName#" $dst", pattern> {
429 // 64-bit input, 32-bit output.
430 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
431 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
434 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
435 opName#" $dst, $src0", pattern>;
437 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
438 opName#" $dst, $src0", pattern>;
441 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
442 SOP2<outs, ins, "", pattern>,
443 SIMCInstr<opName, SISubtarget.NONE> {
448 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm,
450 SOP2<outs, ins, asm, pattern>,
452 SIMCInstr<opName, SISubtarget.SI>;
454 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm,
456 SOP2<outs, ins, asm, pattern>,
458 SIMCInstr<opName, SISubtarget.VI>;
460 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
461 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
462 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
464 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
465 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
466 opName#" $dst, $src0, $src1 [$scc]", pattern>;
468 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
469 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
470 opName#" $dst, $src0, $src1 [$scc]", pattern>;
473 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
474 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
475 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
477 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
478 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
480 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
481 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
484 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
485 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
486 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
488 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
489 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
491 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
492 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
495 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
496 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
497 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
499 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
500 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
502 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
503 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
507 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
508 string opName, PatLeaf cond> : SOPC <
509 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
510 opName#" $dst, $src0, $src1", []>;
512 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
513 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
515 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
516 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
518 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
519 SOPK <outs, ins, "", pattern>,
520 SIMCInstr<opName, SISubtarget.NONE> {
524 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm,
526 SOPK <outs, ins, asm, pattern>,
528 SIMCInstr<opName, SISubtarget.SI>;
530 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm,
532 SOPK <outs, ins, asm, pattern>,
534 SIMCInstr<opName, SISubtarget.VI>;
536 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
537 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
540 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
541 opName#" $dst, $src0", pattern>;
543 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
544 opName#" $dst, $src0", pattern>;
547 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
548 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
549 (ins SReg_32:$src0, u16imm:$src1), pattern>;
551 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
552 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
554 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
555 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
558 //===----------------------------------------------------------------------===//
560 //===----------------------------------------------------------------------===//
562 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
563 SMRD <outs, ins, "", pattern>,
564 SIMCInstr<opName, SISubtarget.NONE> {
568 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
570 SMRD <outs, ins, asm, []>,
572 SIMCInstr<opName, SISubtarget.SI>;
574 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
576 SMRD <outs, ins, asm, []>,
578 SIMCInstr<opName, SISubtarget.VI>;
580 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
581 string asm, list<dag> pattern> {
583 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
585 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
587 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
590 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
591 RegisterClass dstClass> {
593 op, opName#"_IMM", 1, (outs dstClass:$dst),
594 (ins baseClass:$sbase, u32imm:$offset),
595 opName#" $dst, $sbase, $offset", []
598 defm _SGPR : SMRD_m <
599 op, opName#"_SGPR", 0, (outs dstClass:$dst),
600 (ins baseClass:$sbase, SReg_32:$soff),
601 opName#" $dst, $sbase, $soff", []
605 //===----------------------------------------------------------------------===//
606 // Vector ALU classes
607 //===----------------------------------------------------------------------===//
609 // This must always be right before the operand being input modified.
610 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
611 let PrintMethod = "printOperandAndMods";
613 def InputModsNoDefault : Operand <i32> {
614 let PrintMethod = "printOperandAndMods";
617 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
619 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
620 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
624 // Returns the register class to use for the destination of VOP[123C]
625 // instructions for the given VT.
626 class getVALUDstForVT<ValueType VT> {
627 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
628 !if(!eq(VT.Size, 64), VReg_64,
629 SReg_64)); // else VT == i1
632 // Returns the register class to use for source 0 of VOP[12C]
633 // instructions for the given VT.
634 class getVOPSrc0ForVT<ValueType VT> {
635 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
638 // Returns the register class to use for source 1 of VOP[12C] for the
640 class getVOPSrc1ForVT<ValueType VT> {
641 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
644 // Returns the register classes for the source arguments of a VOP[12C]
645 // instruction for the given SrcVTs.
646 class getInRC32 <list<ValueType> SrcVT> {
647 list<DAGOperand> ret = [
648 getVOPSrc0ForVT<SrcVT[0]>.ret,
649 getVOPSrc1ForVT<SrcVT[1]>.ret
653 // Returns the register class to use for sources of VOP3 instructions for the
655 class getVOP3SrcForVT<ValueType VT> {
656 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
659 // Returns the register classes for the source arguments of a VOP3
660 // instruction for the given SrcVTs.
661 class getInRC64 <list<ValueType> SrcVT> {
662 list<DAGOperand> ret = [
663 getVOP3SrcForVT<SrcVT[0]>.ret,
664 getVOP3SrcForVT<SrcVT[1]>.ret,
665 getVOP3SrcForVT<SrcVT[2]>.ret
669 // Returns 1 if the source arguments have modifiers, 0 if they do not.
670 class hasModifiers<ValueType SrcVT> {
671 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
672 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
675 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
676 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
677 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
678 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
682 // Returns the input arguments for VOP3 instructions for the given SrcVT.
683 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
684 RegisterOperand Src2RC, int NumSrcArgs,
688 !if (!eq(NumSrcArgs, 1),
689 !if (!eq(HasModifiers, 1),
690 // VOP1 with modifiers
691 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
692 ClampMod:$clamp, omod:$omod)
694 // VOP1 without modifiers
697 !if (!eq(NumSrcArgs, 2),
698 !if (!eq(HasModifiers, 1),
699 // VOP 2 with modifiers
700 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
701 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
702 ClampMod:$clamp, omod:$omod)
704 // VOP2 without modifiers
705 (ins Src0RC:$src0, Src1RC:$src1)
707 /* NumSrcArgs == 3 */,
708 !if (!eq(HasModifiers, 1),
709 // VOP3 with modifiers
710 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
711 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
712 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
713 ClampMod:$clamp, omod:$omod)
715 // VOP3 without modifiers
716 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
720 // Returns the assembly string for the inputs and outputs of a VOP[12C]
721 // instruction. This does not add the _e32 suffix, so it can be reused
723 class getAsm32 <int NumSrcArgs> {
724 string src1 = ", $src1";
725 string src2 = ", $src2";
726 string ret = " $dst, $src0"#
727 !if(!eq(NumSrcArgs, 1), "", src1)#
728 !if(!eq(NumSrcArgs, 3), src2, "");
731 // Returns the assembly string for the inputs and outputs of a VOP3
733 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
734 string src0 = "$src0_modifiers,";
735 string src1 = !if(!eq(NumSrcArgs, 1), "",
736 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
737 " $src1_modifiers,"));
738 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
740 !if(!eq(HasModifiers, 0),
741 getAsm32<NumSrcArgs>.ret,
742 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
746 class VOPProfile <list<ValueType> _ArgVT> {
748 field list<ValueType> ArgVT = _ArgVT;
750 field ValueType DstVT = ArgVT[0];
751 field ValueType Src0VT = ArgVT[1];
752 field ValueType Src1VT = ArgVT[2];
753 field ValueType Src2VT = ArgVT[3];
754 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
755 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
756 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
757 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
758 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
759 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
761 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
762 field bit HasModifiers = hasModifiers<Src0VT>.ret;
764 field dag Outs = (outs DstRC:$dst);
766 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
767 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
770 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
771 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
774 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
775 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
776 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
777 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
778 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
779 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
780 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
781 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
782 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
784 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
785 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
786 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
787 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
788 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
789 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
790 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
791 let Src0RC32 = VCSrc_32;
794 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
795 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
796 let Asm64 = " $dst, $src0_modifiers, $src1";
799 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
800 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
801 let Asm64 = " $dst, $src0_modifiers, $src1";
804 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
805 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
807 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
808 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
809 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
810 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
813 class VOP <string opName> {
814 string OpName = opName;
817 class VOP2_REV <string revOp, bit isOrig> {
818 string RevOp = revOp;
822 class AtomicNoRet <string noRetOp, bit isRet> {
823 string NoRetOp = noRetOp;
827 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
828 VOP1Common <outs, ins, "", pattern>,
830 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
834 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
836 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
838 def _si : VOP1<op.SI, outs, ins, asm, []>,
839 SIMCInstr <opName#"_e32", SISubtarget.SI>;
840 def _vi : VOP1<op.VI, outs, ins, asm, []>,
841 SIMCInstr <opName#"_e32", SISubtarget.VI>;
844 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
845 VOP2Common <outs, ins, "", pattern>,
847 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
851 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
852 string opName, string revOpSI, string revOpVI> {
853 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
854 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
856 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
857 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
858 SIMCInstr <opName#"_e32", SISubtarget.SI>;
859 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
860 VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
861 SIMCInstr <opName#"_e32", SISubtarget.VI>;
864 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
866 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
867 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
868 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
869 bits<2> omod = !if(HasModifiers, ?, 0);
870 bits<1> clamp = !if(HasModifiers, ?, 0);
871 bits<9> src1 = !if(HasSrc1, ?, 0);
872 bits<9> src2 = !if(HasSrc2, ?, 0);
875 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
876 VOP3Common <outs, ins, "", pattern>,
878 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
882 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
883 VOP3Common <outs, ins, asm, []>,
885 SIMCInstr<opName#"_e64", SISubtarget.SI>;
887 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
888 VOP3Common <outs, ins, asm, []>,
890 SIMCInstr <opName#"_e64", SISubtarget.VI>;
892 // VI only instruction
893 class VOP3_vi <bits<10> op, string opName, dag outs, dag ins, string asm,
894 list<dag> pattern, int NumSrcArgs, bit HasMods = 1> :
895 VOP3Common <outs, ins, asm, pattern>,
898 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
899 !if(!eq(NumSrcArgs, 2), 0, 1),
902 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
903 string opName, int NumSrcArgs, bit HasMods = 1> {
905 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
907 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
908 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
909 !if(!eq(NumSrcArgs, 2), 0, 1),
911 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
912 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
913 !if(!eq(NumSrcArgs, 2), 0, 1),
917 // VOP3_m without source modifiers
918 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
919 string opName, int NumSrcArgs, bit HasMods = 1> {
921 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
923 let src0_modifiers = 0,
925 src2_modifiers = 0 in {
926 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
927 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
931 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
932 list<dag> pattern, string opName, bit HasMods = 1> {
934 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
936 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
937 VOP3DisableFields<0, 0, HasMods>;
939 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
940 VOP3DisableFields<0, 0, HasMods>;
943 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
944 list<dag> pattern, string opName, string revOpSI, string revOpVI,
945 bit HasMods = 1, bit UseFullOp = 0> {
947 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
948 VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>;
950 def _si : VOP3_Real_si <op.SI3,
951 outs, ins, asm, opName>,
952 VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
953 VOP3DisableFields<1, 0, HasMods>;
955 def _vi : VOP3_Real_vi <op.VI3,
956 outs, ins, asm, opName>,
957 VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
958 VOP3DisableFields<1, 0, HasMods>;
961 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
962 list<dag> pattern, string opName, string revOp,
963 bit HasMods = 1, bit UseFullOp = 0> {
964 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
965 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
967 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
968 // can write it into any SGPR. We currently don't use the carry out,
969 // so for now hardcode it to VCC as well.
970 let sdst = SIOperand.VCC, Defs = [VCC] in {
971 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
972 VOP3DisableFields<1, 0, HasMods>,
973 SIMCInstr<opName#"_e64", SISubtarget.SI>,
974 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
976 // TODO: Do we need this VI variant here?
977 /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, pattern>,
978 VOP3DisableFields<1, 0, HasMods>,
979 SIMCInstr<opName#"_e64", SISubtarget.VI>,
980 VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
981 } // End sdst = SIOperand.VCC, Defs = [VCC]
984 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
985 list<dag> pattern, string opName,
986 bit HasMods, bit defExec> {
988 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
990 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
991 VOP3DisableFields<1, 0, HasMods> {
992 let Defs = !if(defExec, [EXEC], []);
995 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
996 VOP3DisableFields<1, 0, HasMods> {
997 let Defs = !if(defExec, [EXEC], []);
1001 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1002 dag ins32, string asm32, list<dag> pat32,
1003 dag ins64, string asm64, list<dag> pat64,
1006 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1008 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1011 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1012 SDPatternOperator node = null_frag> : VOP1_Helper <
1014 P.Ins32, P.Asm32, [],
1017 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1018 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1019 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1023 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1024 SDPatternOperator node = null_frag> {
1026 def _e32 : VOP1 <op.SI, P.Outs, P.Ins32, opName#P.Asm32, []>,
1029 def _e64 : VOP3Common <P.Outs, P.Ins64, opName#P.Asm64,
1031 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1032 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1033 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])>,
1036 VOP3DisableFields<0, 0, P.HasModifiers>;
1039 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1040 dag ins32, string asm32, list<dag> pat32,
1041 dag ins64, string asm64, list<dag> pat64,
1042 string revOpSI, string revOpVI, bit HasMods> {
1043 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>;
1045 defm _e64 : VOP3_2_m <op,
1046 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods
1050 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1051 SDPatternOperator node = null_frag,
1052 string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper <
1054 P.Ins32, P.Asm32, [],
1058 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1059 i1:$clamp, i32:$omod)),
1060 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1061 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1062 revOpSI, revOpVI, P.HasModifiers
1065 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1066 dag ins32, string asm32, list<dag> pat32,
1067 dag ins64, string asm64, list<dag> pat64,
1068 string revOp, bit HasMods> {
1070 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>;
1072 defm _e64 : VOP3b_2_m <op,
1073 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1077 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1078 SDPatternOperator node = null_frag,
1079 string revOp = opName> : VOP2b_Helper <
1081 P.Ins32, P.Asm32, [],
1085 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1086 i1:$clamp, i32:$omod)),
1087 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1088 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1089 revOp, P.HasModifiers
1092 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1093 VOPCCommon <ins, "", pattern>,
1095 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1099 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1100 string opName, bit DefExec> {
1101 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1103 def _si : VOPC<op.SI, ins, asm, []>,
1104 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1105 let Defs = !if(DefExec, [EXEC], []);
1108 def _vi : VOPC<op.VI, ins, asm, []>,
1109 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1110 let Defs = !if(DefExec, [EXEC], []);
1114 multiclass VOPC_Helper <vopc op, string opName,
1115 dag ins32, string asm32, list<dag> pat32,
1116 dag out64, dag ins64, string asm64, list<dag> pat64,
1117 bit HasMods, bit DefExec> {
1118 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1120 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1121 opName, HasMods, DefExec>;
1124 multiclass VOPCInst <vopc op, string opName,
1125 VOPProfile P, PatLeaf cond = COND_NULL,
1126 bit DefExec = 0> : VOPC_Helper <
1128 P.Ins32, P.Asm32, [],
1129 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1132 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1133 i1:$clamp, i32:$omod)),
1134 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1136 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1137 P.HasModifiers, DefExec
1140 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1141 bit DefExec = 0> : VOPC_Helper <
1143 P.Ins32, P.Asm32, [],
1144 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1147 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1148 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1149 P.HasModifiers, DefExec
1153 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1154 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1156 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1157 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1159 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1160 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1162 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1163 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1166 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1167 PatLeaf cond = COND_NULL>
1168 : VOPCInst <op, opName, P, cond, 1>;
1170 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1171 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1173 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1174 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1176 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1177 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1179 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1180 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1182 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1183 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1184 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1187 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1188 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1190 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1191 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1193 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1194 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1196 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1197 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1199 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1200 SDPatternOperator node = null_frag> : VOP3_Helper <
1201 op, opName, P.Outs, P.Ins64, P.Asm64,
1202 !if(!eq(P.NumSrcArgs, 3),
1205 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1206 i1:$clamp, i32:$omod)),
1207 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1208 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1209 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1211 !if(!eq(P.NumSrcArgs, 2),
1214 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1215 i1:$clamp, i32:$omod)),
1216 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1217 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1218 /* P.NumSrcArgs == 1 */,
1221 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1222 i1:$clamp, i32:$omod))))],
1223 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1224 P.NumSrcArgs, P.HasModifiers
1227 class VOP3InstVI <bits<10> op, string opName, VOPProfile P,
1228 SDPatternOperator node = null_frag> : VOP3_vi <
1229 op, opName#"_vi", P.Outs, P.Ins64, opName#P.Asm64,
1230 !if(!eq(P.NumSrcArgs, 3),
1233 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1234 i1:$clamp, i32:$omod)),
1235 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1236 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1237 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1239 !if(!eq(P.NumSrcArgs, 2),
1242 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1243 i1:$clamp, i32:$omod)),
1244 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1245 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1246 /* P.NumSrcArgs == 1 */,
1249 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1250 i1:$clamp, i32:$omod))))],
1251 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1252 P.NumSrcArgs, P.HasModifiers
1255 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1256 string opName, list<dag> pattern> :
1258 op, (outs vrc:$vdst, SReg_64:$sdst),
1259 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1260 InputModsNoDefault:$src1_modifiers, arc:$src1,
1261 InputModsNoDefault:$src2_modifiers, arc:$src2,
1262 ClampMod:$clamp, omod:$omod),
1263 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1264 opName, opName, 1, 1
1267 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1268 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1270 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1271 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1274 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1275 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1276 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1277 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1278 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1279 i32:$src1_modifiers, P.Src1VT:$src1,
1280 i32:$src2_modifiers, P.Src2VT:$src2,
1284 //===----------------------------------------------------------------------===//
1285 // Interpolation opcodes
1286 //===----------------------------------------------------------------------===//
1288 class VINTRP_Pseudo <string opName, dag outs, dag ins, string asm,
1289 list<dag> pattern> :
1290 VINTRPCommon <outs, ins, asm, pattern>,
1291 SIMCInstr<opName, SISubtarget.NONE> {
1295 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1296 string asm, list<dag> pattern> :
1297 VINTRPCommon <outs, ins, asm, pattern>,
1299 SIMCInstr<opName, SISubtarget.SI>;
1301 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1302 string asm, list<dag> pattern> :
1303 VINTRPCommon <outs, ins, asm, pattern>,
1305 SIMCInstr<opName, SISubtarget.VI>;
1307 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1308 string disableEncoding = "", string constraints = "",
1309 list<dag> pattern = []> {
1310 let DisableEncoding = disableEncoding,
1311 Constraints = constraints in {
1312 def "" : VINTRP_Pseudo <opName, outs, ins, asm, pattern>;
1314 def _si : VINTRP_Real_si <op, opName, outs, ins, asm, pattern>;
1316 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm, pattern>;
1320 //===----------------------------------------------------------------------===//
1321 // Vector I/O classes
1322 //===----------------------------------------------------------------------===//
1324 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1325 DS <outs, ins, "", pattern>,
1326 SIMCInstr <opName, SISubtarget.NONE> {
1330 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1331 DS <outs, ins, asm, []>,
1333 SIMCInstr <opName, SISubtarget.SI>;
1335 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1336 DS <outs, ins, asm, []>,
1338 SIMCInstr <opName, SISubtarget.VI>;
1340 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1341 DS <outs, ins, asm, []>,
1343 SIMCInstr <opName, SISubtarget.SI> {
1345 // Single load interpret the 2 i8imm operands as a single i16 offset.
1347 let offset0 = offset{7-0};
1348 let offset1 = offset{15-8};
1351 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1352 DS <outs, ins, asm, []>,
1354 SIMCInstr <opName, SISubtarget.VI> {
1356 // Single load interpret the 2 i8imm operands as a single i16 offset.
1358 let offset0 = offset{7-0};
1359 let offset1 = offset{15-8};
1362 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1364 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1365 def "" : DS_Pseudo <opName, outs, ins, pat>;
1367 let data0 = 0, data1 = 0 in {
1368 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1369 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1374 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1378 (outs regClass:$vdst),
1379 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1380 asm#" $vdst, $addr"#"$offset"#" [M0]",
1383 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1385 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1386 def "" : DS_Pseudo <opName, outs, ins, pat>;
1388 let data0 = 0, data1 = 0 in {
1389 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1390 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1395 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1399 (outs regClass:$vdst),
1400 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1402 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1405 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1406 string asm, list<dag> pat> {
1407 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1408 def "" : DS_Pseudo <opName, outs, ins, pat>;
1410 let data1 = 0, vdst = 0 in {
1411 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1412 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1417 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1422 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1423 asm#" $addr, $data0"#"$offset"#" [M0]",
1426 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1427 string asm, list<dag> pat> {
1428 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1429 def "" : DS_Pseudo <opName, outs, ins, pat>;
1432 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1433 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1438 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1443 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1444 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1445 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1448 class DS_1A_si <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
1449 DS_si <op, outs, ins, asm, pat> {
1452 // Single load interpret the 2 i8imm operands as a single i16 offset.
1453 let offset0 = offset{7-0};
1454 let offset1 = offset{15-8};
1456 let hasSideEffects = 0;
1459 // 1 address, 1 data.
1460 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1463 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1464 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
1465 AtomicNoRet<noRetOp, 1> {
1471 let hasPostISelHook = 1; // Adjusted to no return version.
1474 // 1 address, 2 data.
1475 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1478 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1479 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1481 AtomicNoRet<noRetOp, 1> {
1484 let hasPostISelHook = 1; // Adjusted to no return version.
1487 // 1 address, 2 data.
1488 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1491 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1492 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1494 AtomicNoRet<noRetOp, 0> {
1499 // 1 address, 1 data.
1500 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1503 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1504 asm#" $addr, $data0"#"$offset"#" [M0]",
1506 AtomicNoRet<noRetOp, 0> {
1513 //===----------------------------------------------------------------------===//
1515 //===----------------------------------------------------------------------===//
1517 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1518 MTBUF <outs, ins, "", pattern>,
1519 SIMCInstr<opName, SISubtarget.NONE> {
1523 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1525 MTBUF <outs, ins, asm, []>,
1527 SIMCInstr<opName, SISubtarget.SI>;
1529 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1530 MTBUF <outs, ins, asm, []>,
1532 SIMCInstr <opName, SISubtarget.VI>;
1534 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1535 list<dag> pattern> {
1537 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1539 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1541 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1545 let mayStore = 1, mayLoad = 0 in {
1547 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1548 RegisterClass regClass> : MTBUF_m <
1550 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1551 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1552 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1553 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1554 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1557 } // mayStore = 1, mayLoad = 0
1559 let mayLoad = 1, mayStore = 0 in {
1561 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1562 RegisterClass regClass> : MTBUF_m <
1563 op, opName, (outs regClass:$dst),
1564 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1565 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1566 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1567 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1568 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1571 } // mayLoad = 1, mayStore = 0
1573 //===----------------------------------------------------------------------===//
1575 //===----------------------------------------------------------------------===//
1577 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1578 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1582 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1583 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
1587 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1589 bit IsAddr64 = is_addr64;
1590 string OpName = NAME # suffix;
1593 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1594 : MUBUF_si <op, outs, ins, asm, pattern> {
1604 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1605 : MUBUF_si <op, outs, ins, asm, pattern> {
1615 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1616 ValueType vt, SDPatternOperator atomic> {
1618 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1620 // No return variants
1623 def _ADDR64 : MUBUFAtomicAddr64 <
1625 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1626 mbuf_offset:$offset, slc:$slc),
1627 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1628 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1630 def _OFFSET : MUBUFAtomicOffset <
1632 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1633 SCSrc_32:$soffset, slc:$slc),
1634 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1635 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1638 // Variant that return values
1639 let glc = 1, Constraints = "$vdata = $vdata_in",
1640 DisableEncoding = "$vdata_in" in {
1642 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1643 op, (outs rc:$vdata),
1644 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1645 mbuf_offset:$offset, slc:$slc),
1646 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1648 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1649 i1:$slc), vt:$vdata_in))]
1650 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1652 def _RTN_OFFSET : MUBUFAtomicOffset <
1653 op, (outs rc:$vdata),
1654 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1655 SCSrc_32:$soffset, slc:$slc),
1656 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1658 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1659 i1:$slc), vt:$vdata_in))]
1660 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1664 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1667 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1668 ValueType load_vt = i32,
1669 SDPatternOperator ld = null_frag> {
1671 let mayLoad = 1, mayStore = 0 in {
1675 let offen = 0, idxen = 0, vaddr = 0 in {
1676 def _OFFSET : MUBUF_si <op, (outs regClass:$vdata),
1677 (ins SReg_128:$srsrc,
1678 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1679 slc:$slc, tfe:$tfe),
1680 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1681 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1682 i32:$soffset, i16:$offset,
1683 i1:$glc, i1:$slc, i1:$tfe)))]>,
1684 MUBUFAddr64Table<0>;
1687 let offen = 1, idxen = 0 in {
1688 def _OFFEN : MUBUF_si <op, (outs regClass:$vdata),
1689 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1690 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1692 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1695 let offen = 0, idxen = 1 in {
1696 def _IDXEN : MUBUF_si <op, (outs regClass:$vdata),
1697 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1698 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1699 slc:$slc, tfe:$tfe),
1700 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1703 let offen = 1, idxen = 1 in {
1704 def _BOTHEN : MUBUF_si <op, (outs regClass:$vdata),
1705 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1706 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1707 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1711 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1712 def _ADDR64 : MUBUF_si <op, (outs regClass:$vdata),
1713 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1714 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1715 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1716 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1721 multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
1722 ValueType load_vt = i32,
1723 SDPatternOperator ld = null_frag> {
1725 let lds = 0, mayLoad = 1 in {
1726 let offen = 0, idxen = 0, vaddr = 0 in {
1727 def _OFFSET : MUBUF_vi <op, (outs regClass:$vdata),
1728 (ins SReg_128:$srsrc,
1729 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1730 slc:$slc, tfe:$tfe),
1731 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1732 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1733 i32:$soffset, i16:$offset,
1734 i1:$glc, i1:$slc, i1:$tfe)))]>,
1735 MUBUFAddr64Table<0>;
1738 let offen = 1, idxen = 0 in {
1739 def _OFFEN : MUBUF_vi <op, (outs regClass:$vdata),
1740 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1741 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1743 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1746 let offen = 0, idxen = 1 in {
1747 def _IDXEN : MUBUF_vi <op, (outs regClass:$vdata),
1748 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1749 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1750 slc:$slc, tfe:$tfe),
1751 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1754 let offen = 1, idxen = 1 in {
1755 def _BOTHEN : MUBUF_vi <op, (outs regClass:$vdata),
1756 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1757 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1758 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1763 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1764 ValueType store_vt, SDPatternOperator st> {
1766 let mayLoad = 0, mayStore = 1 in {
1771 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1772 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1774 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1775 "$glc"#"$slc"#"$tfe",
1779 let offen = 0, idxen = 0, vaddr = 0 in {
1780 def _OFFSET : MUBUF_si <
1782 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1783 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1784 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1785 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1786 i16:$offset, i1:$glc, i1:$slc,
1788 >, MUBUFAddr64Table<0>;
1789 } // offen = 0, idxen = 0, vaddr = 0
1791 let offen = 1, idxen = 0 in {
1792 def _OFFEN : MUBUF_si <
1794 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1795 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1796 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1797 "$glc"#"$slc"#"$tfe",
1800 } // end offen = 1, idxen = 0
1804 def _ADDR64 : MUBUF_si <
1806 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1807 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1808 [(st store_vt:$vdata,
1809 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1822 let soffset = 128; // ZERO
1824 } // End mayLoad = 0, mayStore = 1
1827 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1828 FLAT <op, (outs regClass:$data),
1829 (ins VReg_64:$addr),
1830 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1837 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1838 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1839 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1851 class MIMG_Mask <string op, int channels> {
1853 int Channels = channels;
1856 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1857 RegisterClass dst_rc,
1858 RegisterClass src_rc> : MIMG <
1860 (outs dst_rc:$vdata),
1861 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1862 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1864 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1865 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1870 let hasPostISelHook = 1;
1873 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1874 RegisterClass dst_rc,
1876 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1877 MIMG_Mask<asm#"_V1", channels>;
1878 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1879 MIMG_Mask<asm#"_V2", channels>;
1880 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1881 MIMG_Mask<asm#"_V4", channels>;
1884 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1885 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1886 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1887 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1888 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1891 class MIMG_Sampler_Helper <bits<7> op, string asm,
1892 RegisterClass dst_rc,
1893 RegisterClass src_rc> : MIMG <
1895 (outs dst_rc:$vdata),
1896 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1897 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1898 SReg_256:$srsrc, SReg_128:$ssamp),
1899 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1900 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1904 let hasPostISelHook = 1;
1907 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1908 RegisterClass dst_rc,
1910 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32>,
1911 MIMG_Mask<asm#"_V1", channels>;
1912 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1913 MIMG_Mask<asm#"_V2", channels>;
1914 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1915 MIMG_Mask<asm#"_V4", channels>;
1916 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1917 MIMG_Mask<asm#"_V8", channels>;
1918 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1919 MIMG_Mask<asm#"_V16", channels>;
1922 multiclass MIMG_Sampler <bits<7> op, string asm> {
1923 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1>;
1924 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1925 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1926 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1929 class MIMG_Gather_Helper <bits<7> op, string asm,
1930 RegisterClass dst_rc,
1931 RegisterClass src_rc> : MIMG <
1933 (outs dst_rc:$vdata),
1934 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1935 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1936 SReg_256:$srsrc, SReg_128:$ssamp),
1937 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1938 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1943 // DMASK was repurposed for GATHER4. 4 components are always
1944 // returned and DMASK works like a swizzle - it selects
1945 // the component to fetch. The only useful DMASK values are
1946 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1947 // (red,red,red,red) etc.) The ISA document doesn't mention
1949 // Therefore, disable all code which updates DMASK by setting these two:
1951 let hasPostISelHook = 0;
1954 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1955 RegisterClass dst_rc,
1957 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32>,
1958 MIMG_Mask<asm#"_V1", channels>;
1959 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1960 MIMG_Mask<asm#"_V2", channels>;
1961 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1962 MIMG_Mask<asm#"_V4", channels>;
1963 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1964 MIMG_Mask<asm#"_V8", channels>;
1965 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1966 MIMG_Mask<asm#"_V16", channels>;
1969 multiclass MIMG_Gather <bits<7> op, string asm> {
1970 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1>;
1971 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1972 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1973 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1976 //===----------------------------------------------------------------------===//
1977 // Vector instruction mappings
1978 //===----------------------------------------------------------------------===//
1980 // Maps an opcode in e32 form to its e64 equivalent
1981 def getVOPe64 : InstrMapping {
1982 let FilterClass = "VOP";
1983 let RowFields = ["OpName"];
1984 let ColFields = ["Size"];
1986 let ValueCols = [["8"]];
1989 // Maps an opcode in e64 form to its e32 equivalent
1990 def getVOPe32 : InstrMapping {
1991 let FilterClass = "VOP";
1992 let RowFields = ["OpName"];
1993 let ColFields = ["Size"];
1995 let ValueCols = [["4"]];
1998 // Maps an original opcode to its commuted version
1999 def getCommuteRev : InstrMapping {
2000 let FilterClass = "VOP2_REV";
2001 let RowFields = ["RevOp"];
2002 let ColFields = ["IsOrig"];
2004 let ValueCols = [["0"]];
2007 def getMaskedMIMGOp : InstrMapping {
2008 let FilterClass = "MIMG_Mask";
2009 let RowFields = ["Op"];
2010 let ColFields = ["Channels"];
2012 let ValueCols = [["1"], ["2"], ["3"] ];
2015 // Maps an commuted opcode to its original version
2016 def getCommuteOrig : InstrMapping {
2017 let FilterClass = "VOP2_REV";
2018 let RowFields = ["RevOp"];
2019 let ColFields = ["IsOrig"];
2021 let ValueCols = [["1"]];
2024 def getMCOpcodeGen : InstrMapping {
2025 let FilterClass = "SIMCInstr";
2026 let RowFields = ["PseudoInstr"];
2027 let ColFields = ["Subtarget"];
2028 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2029 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2032 def getAddr64Inst : InstrMapping {
2033 let FilterClass = "MUBUFAddr64Table";
2034 let RowFields = ["OpName"];
2035 let ColFields = ["IsAddr64"];
2037 let ValueCols = [["1"]];
2040 // Maps an atomic opcode to its version with a return value.
2041 def getAtomicRetOp : InstrMapping {
2042 let FilterClass = "AtomicNoRet";
2043 let RowFields = ["NoRetOp"];
2044 let ColFields = ["IsRet"];
2046 let ValueCols = [["1"]];
2049 // Maps an atomic opcode to its returnless version.
2050 def getAtomicNoRetOp : InstrMapping {
2051 let FilterClass = "AtomicNoRet";
2052 let RowFields = ["NoRetOp"];
2053 let ColFields = ["IsRet"];
2055 let ValueCols = [["0"]];
2058 include "SIInstructions.td"
2059 include "CIInstructions.td"
2060 include "VIInstructions.td"