1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
215 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
218 const SIRegisterInfo *SIRI =
219 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
220 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
222 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
229 //===----------------------------------------------------------------------===//
231 //===----------------------------------------------------------------------===//
233 def FRAMEri32 : Operand<iPTR> {
234 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
237 def sopp_brtarget : Operand<OtherVT> {
238 let EncoderMethod = "getSOPPBrEncoding";
239 let OperandType = "OPERAND_PCREL";
242 include "SIInstrFormats.td"
243 include "VIInstrFormats.td"
245 let OperandType = "OPERAND_IMMEDIATE" in {
247 def offen : Operand<i1> {
248 let PrintMethod = "printOffen";
250 def idxen : Operand<i1> {
251 let PrintMethod = "printIdxen";
253 def addr64 : Operand<i1> {
254 let PrintMethod = "printAddr64";
256 def mbuf_offset : Operand<i16> {
257 let PrintMethod = "printMBUFOffset";
259 def ds_offset : Operand<i16> {
260 let PrintMethod = "printDSOffset";
262 def ds_offset0 : Operand<i8> {
263 let PrintMethod = "printDSOffset0";
265 def ds_offset1 : Operand<i8> {
266 let PrintMethod = "printDSOffset1";
268 def glc : Operand <i1> {
269 let PrintMethod = "printGLC";
271 def slc : Operand <i1> {
272 let PrintMethod = "printSLC";
274 def tfe : Operand <i1> {
275 let PrintMethod = "printTFE";
278 def omod : Operand <i32> {
279 let PrintMethod = "printOModSI";
282 def ClampMod : Operand <i1> {
283 let PrintMethod = "printClampSI";
286 } // End OperandType = "OPERAND_IMMEDIATE"
288 //===----------------------------------------------------------------------===//
290 //===----------------------------------------------------------------------===//
292 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
293 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
295 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
296 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
297 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
298 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
299 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
300 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
302 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
303 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
304 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
305 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
307 //===----------------------------------------------------------------------===//
308 // SI assembler operands
309 //===----------------------------------------------------------------------===//
329 //===----------------------------------------------------------------------===//
331 // SI Instruction multiclass helpers.
333 // Instructions with _32 take 32-bit operands.
334 // Instructions with _64 take 64-bit operands.
336 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
337 // encoding is the standard encoding, but instruction that make use of
338 // any of the instruction modifiers must use the 64-bit encoding.
340 // Instructions with _e32 use the 32-bit encoding.
341 // Instructions with _e64 use the 64-bit encoding.
343 //===----------------------------------------------------------------------===//
345 class SIMCInstr <string pseudo, int subtarget> {
346 string PseudoInstr = pseudo;
347 int Subtarget = subtarget;
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
354 class EXPCommon : InstSI<
356 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
357 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
358 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
367 let isPseudo = 1 in {
368 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
371 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
373 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
376 //===----------------------------------------------------------------------===//
378 //===----------------------------------------------------------------------===//
380 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
381 SOP1 <outs, ins, "", pattern>,
382 SIMCInstr<opName, SISubtarget.NONE> {
386 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
387 SOP1 <outs, ins, asm, []>,
389 SIMCInstr<opName, SISubtarget.SI>;
391 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
392 SOP1 <outs, ins, asm, []>,
394 SIMCInstr<opName, SISubtarget.VI>;
396 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
397 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
400 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
401 opName#" $dst, $src0">;
403 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
404 opName#" $dst, $src0">;
407 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
408 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
411 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
412 opName#" $dst, $src0">;
414 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
415 opName#" $dst, $src0">;
418 // no input, 64-bit output.
419 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
420 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
422 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
427 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
433 // 64-bit input, 32-bit output.
434 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
435 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
438 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
439 opName#" $dst, $src0">;
441 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
442 opName#" $dst, $src0">;
445 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
446 SOP2<outs, ins, "", pattern>,
447 SIMCInstr<opName, SISubtarget.NONE> {
452 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
453 SOP2<outs, ins, asm, []>,
455 SIMCInstr<opName, SISubtarget.SI>;
457 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
458 SOP2<outs, ins, asm, []>,
460 SIMCInstr<opName, SISubtarget.VI>;
462 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
463 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
464 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
466 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
467 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
468 opName#" $dst, $src0, $src1 [$scc]">;
470 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
471 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
472 opName#" $dst, $src0, $src1 [$scc]">;
475 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
476 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
477 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
479 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
480 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
482 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
483 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
486 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
487 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
488 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
490 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
491 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
493 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
494 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
497 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
498 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
499 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
501 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
502 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
504 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
505 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
509 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
510 string opName, PatLeaf cond> : SOPC <
511 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
512 opName#" $dst, $src0, $src1", []>;
514 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
515 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
517 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
518 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
520 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
521 SOPK <outs, ins, "", pattern>,
522 SIMCInstr<opName, SISubtarget.NONE> {
526 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
527 SOPK <outs, ins, asm, []>,
529 SIMCInstr<opName, SISubtarget.SI>;
531 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
532 SOPK <outs, ins, asm, []>,
534 SIMCInstr<opName, SISubtarget.VI>;
536 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
537 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
540 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
541 opName#" $dst, $src0">;
543 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
544 opName#" $dst, $src0">;
547 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
548 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
549 (ins SReg_32:$src0, u16imm:$src1), pattern>;
551 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
552 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
554 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
555 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
558 //===----------------------------------------------------------------------===//
560 //===----------------------------------------------------------------------===//
562 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
563 SMRD <outs, ins, "", pattern>,
564 SIMCInstr<opName, SISubtarget.NONE> {
568 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
570 SMRD <outs, ins, asm, []>,
572 SIMCInstr<opName, SISubtarget.SI>;
574 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
576 SMRD <outs, ins, asm, []>,
578 SIMCInstr<opName, SISubtarget.VI>;
580 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
581 string asm, list<dag> pattern> {
583 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
585 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
587 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
590 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
591 RegisterClass dstClass> {
593 op, opName#"_IMM", 1, (outs dstClass:$dst),
594 (ins baseClass:$sbase, u32imm:$offset),
595 opName#" $dst, $sbase, $offset", []
598 defm _SGPR : SMRD_m <
599 op, opName#"_SGPR", 0, (outs dstClass:$dst),
600 (ins baseClass:$sbase, SReg_32:$soff),
601 opName#" $dst, $sbase, $soff", []
605 //===----------------------------------------------------------------------===//
606 // Vector ALU classes
607 //===----------------------------------------------------------------------===//
609 // This must always be right before the operand being input modified.
610 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
611 let PrintMethod = "printOperandAndMods";
613 def InputModsNoDefault : Operand <i32> {
614 let PrintMethod = "printOperandAndMods";
617 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
619 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
620 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
624 // Returns the register class to use for the destination of VOP[123C]
625 // instructions for the given VT.
626 class getVALUDstForVT<ValueType VT> {
627 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
628 !if(!eq(VT.Size, 64), VReg_64,
629 SReg_64)); // else VT == i1
632 // Returns the register class to use for source 0 of VOP[12C]
633 // instructions for the given VT.
634 class getVOPSrc0ForVT<ValueType VT> {
635 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
638 // Returns the register class to use for source 1 of VOP[12C] for the
640 class getVOPSrc1ForVT<ValueType VT> {
641 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
644 // Returns the register classes for the source arguments of a VOP[12C]
645 // instruction for the given SrcVTs.
646 class getInRC32 <list<ValueType> SrcVT> {
647 list<DAGOperand> ret = [
648 getVOPSrc0ForVT<SrcVT[0]>.ret,
649 getVOPSrc1ForVT<SrcVT[1]>.ret
653 // Returns the register class to use for sources of VOP3 instructions for the
655 class getVOP3SrcForVT<ValueType VT> {
656 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
659 // Returns the register classes for the source arguments of a VOP3
660 // instruction for the given SrcVTs.
661 class getInRC64 <list<ValueType> SrcVT> {
662 list<DAGOperand> ret = [
663 getVOP3SrcForVT<SrcVT[0]>.ret,
664 getVOP3SrcForVT<SrcVT[1]>.ret,
665 getVOP3SrcForVT<SrcVT[2]>.ret
669 // Returns 1 if the source arguments have modifiers, 0 if they do not.
670 class hasModifiers<ValueType SrcVT> {
671 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
672 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
675 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
676 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
677 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
678 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
682 // Returns the input arguments for VOP3 instructions for the given SrcVT.
683 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
684 RegisterOperand Src2RC, int NumSrcArgs,
688 !if (!eq(NumSrcArgs, 1),
689 !if (!eq(HasModifiers, 1),
690 // VOP1 with modifiers
691 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
692 ClampMod:$clamp, omod:$omod)
694 // VOP1 without modifiers
697 !if (!eq(NumSrcArgs, 2),
698 !if (!eq(HasModifiers, 1),
699 // VOP 2 with modifiers
700 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
701 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
702 ClampMod:$clamp, omod:$omod)
704 // VOP2 without modifiers
705 (ins Src0RC:$src0, Src1RC:$src1)
707 /* NumSrcArgs == 3 */,
708 !if (!eq(HasModifiers, 1),
709 // VOP3 with modifiers
710 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
711 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
712 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
713 ClampMod:$clamp, omod:$omod)
715 // VOP3 without modifiers
716 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
720 // Returns the assembly string for the inputs and outputs of a VOP[12C]
721 // instruction. This does not add the _e32 suffix, so it can be reused
723 class getAsm32 <int NumSrcArgs> {
724 string src1 = ", $src1";
725 string src2 = ", $src2";
726 string ret = " $dst, $src0"#
727 !if(!eq(NumSrcArgs, 1), "", src1)#
728 !if(!eq(NumSrcArgs, 3), src2, "");
731 // Returns the assembly string for the inputs and outputs of a VOP3
733 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
734 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
735 string src1 = !if(!eq(NumSrcArgs, 1), "",
736 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
737 " $src1_modifiers,"));
738 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
740 !if(!eq(HasModifiers, 0),
741 getAsm32<NumSrcArgs>.ret,
742 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
746 class VOPProfile <list<ValueType> _ArgVT> {
748 field list<ValueType> ArgVT = _ArgVT;
750 field ValueType DstVT = ArgVT[0];
751 field ValueType Src0VT = ArgVT[1];
752 field ValueType Src1VT = ArgVT[2];
753 field ValueType Src2VT = ArgVT[3];
754 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
755 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
756 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
757 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
758 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
759 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
761 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
762 field bit HasModifiers = hasModifiers<Src0VT>.ret;
764 field dag Outs = (outs DstRC:$dst);
766 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
767 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
770 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
771 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
774 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
775 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
776 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
777 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
778 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
779 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
780 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
781 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
782 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
784 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
785 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
786 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
787 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
788 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
789 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
790 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
791 let Src0RC32 = VCSrc_32;
794 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
795 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
796 let Asm64 = " $dst, $src0_modifiers, $src1";
799 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
800 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
801 let Asm64 = " $dst, $src0_modifiers, $src1";
804 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
805 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
807 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
808 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
809 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
810 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
813 class VOP <string opName> {
814 string OpName = opName;
817 class VOP2_REV <string revOp, bit isOrig> {
818 string RevOp = revOp;
822 class AtomicNoRet <string noRetOp, bit isRet> {
823 string NoRetOp = noRetOp;
827 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
828 VOP1Common <outs, ins, "", pattern>,
830 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
834 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
836 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
838 def _si : VOP1<op.SI, outs, ins, asm, []>,
839 SIMCInstr <opName#"_e32", SISubtarget.SI>;
840 def _vi : VOP1<op.VI, outs, ins, asm, []>,
841 SIMCInstr <opName#"_e32", SISubtarget.VI>;
844 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
845 VOP2Common <outs, ins, "", pattern>,
847 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
851 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
852 string opName, string revOpSI> {
853 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
854 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
856 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
857 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
858 SIMCInstr <opName#"_e32", SISubtarget.SI>;
861 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
862 string opName, string revOpSI, string revOpVI> {
863 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
864 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
866 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
867 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
868 SIMCInstr <opName#"_e32", SISubtarget.SI>;
869 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
870 VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
871 SIMCInstr <opName#"_e32", SISubtarget.VI>;
874 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
876 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
877 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
878 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
879 bits<2> omod = !if(HasModifiers, ?, 0);
880 bits<1> clamp = !if(HasModifiers, ?, 0);
881 bits<9> src1 = !if(HasSrc1, ?, 0);
882 bits<9> src2 = !if(HasSrc2, ?, 0);
885 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
886 VOP3Common <outs, ins, "", pattern>,
888 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
892 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
893 VOP3Common <outs, ins, asm, []>,
895 SIMCInstr<opName#"_e64", SISubtarget.SI>;
897 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
898 VOP3Common <outs, ins, asm, []>,
900 SIMCInstr <opName#"_e64", SISubtarget.VI>;
902 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
903 string opName, int NumSrcArgs, bit HasMods = 1> {
905 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
907 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
908 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
909 !if(!eq(NumSrcArgs, 2), 0, 1),
911 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
912 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
913 !if(!eq(NumSrcArgs, 2), 0, 1),
917 // VOP3_m without source modifiers
918 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
919 string opName, int NumSrcArgs, bit HasMods = 1> {
921 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
923 let src0_modifiers = 0,
925 src2_modifiers = 0 in {
926 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
927 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
931 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
932 list<dag> pattern, string opName, bit HasMods = 1> {
934 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
936 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
937 VOP3DisableFields<0, 0, HasMods>;
939 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
940 VOP3DisableFields<0, 0, HasMods>;
943 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
944 list<dag> pattern, string opName, string revOpSI, string revOpVI,
945 bit HasMods = 1, bit UseFullOp = 0> {
947 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
948 VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>;
950 def _si : VOP3_Real_si <op.SI3,
951 outs, ins, asm, opName>,
952 VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
953 VOP3DisableFields<1, 0, HasMods>;
955 def _vi : VOP3_Real_vi <op.VI3,
956 outs, ins, asm, opName>,
957 VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
958 VOP3DisableFields<1, 0, HasMods>;
961 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
962 list<dag> pattern, string opName, string revOp,
963 bit HasMods = 1, bit UseFullOp = 0> {
964 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
965 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
967 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
968 // can write it into any SGPR. We currently don't use the carry out,
969 // so for now hardcode it to VCC as well.
970 let sdst = SIOperand.VCC, Defs = [VCC] in {
971 def _si : VOP3b <op.SI3, outs, ins, asm, []>,
972 VOP3DisableFields<1, 0, HasMods>,
973 SIMCInstr<opName#"_e64", SISubtarget.SI>,
974 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
976 // TODO: Do we need this VI variant here?
977 /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, []>,
978 VOP3DisableFields<1, 0, HasMods>,
979 SIMCInstr<opName#"_e64", SISubtarget.VI>,
980 VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
981 } // End sdst = SIOperand.VCC, Defs = [VCC]
984 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
985 list<dag> pattern, string opName,
986 bit HasMods, bit defExec> {
988 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
990 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
991 VOP3DisableFields<1, 0, HasMods> {
992 let Defs = !if(defExec, [EXEC], []);
995 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
996 VOP3DisableFields<1, 0, HasMods> {
997 let Defs = !if(defExec, [EXEC], []);
1001 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1002 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1003 string asm, list<dag> pattern = []> {
1004 let isPseudo = 1 in {
1005 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1006 SIMCInstr<opName, SISubtarget.NONE>;
1009 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1010 SIMCInstr <opName, SISubtarget.SI>;
1012 def _vi : VOP3Common <outs, ins, asm, []>,
1014 VOP3DisableFields <1, 0, 0>,
1015 SIMCInstr <opName, SISubtarget.VI>;
1018 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1019 dag ins32, string asm32, list<dag> pat32,
1020 dag ins64, string asm64, list<dag> pat64,
1023 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1025 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1028 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1029 SDPatternOperator node = null_frag> : VOP1_Helper <
1031 P.Ins32, P.Asm32, [],
1034 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1035 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1036 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1040 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1041 SDPatternOperator node = null_frag> {
1043 def _e32 : VOP1 <op.SI, P.Outs, P.Ins32, opName#P.Asm32, []>,
1046 def _e64 : VOP3Common <P.Outs, P.Ins64, opName#P.Asm64,
1048 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1049 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1050 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])>,
1053 VOP3DisableFields<0, 0, P.HasModifiers>;
1056 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1057 dag ins32, string asm32, list<dag> pat32,
1058 dag ins64, string asm64, list<dag> pat64,
1059 string revOpSI, string revOpVI, bit HasMods> {
1060 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>;
1062 defm _e64 : VOP3_2_m <op,
1063 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods
1067 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1068 SDPatternOperator node = null_frag,
1069 string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper <
1071 P.Ins32, P.Asm32, [],
1075 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1076 i1:$clamp, i32:$omod)),
1077 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1078 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1079 revOpSI, revOpVI, P.HasModifiers
1082 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1083 dag ins32, string asm32, list<dag> pat32,
1084 dag ins64, string asm64, list<dag> pat64,
1085 string revOp, bit HasMods> {
1087 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>;
1089 defm _e64 : VOP3b_2_m <op,
1090 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1094 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1095 SDPatternOperator node = null_frag,
1096 string revOp = opName> : VOP2b_Helper <
1098 P.Ins32, P.Asm32, [],
1102 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1103 i1:$clamp, i32:$omod)),
1104 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1105 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1106 revOp, P.HasModifiers
1109 // A VOP2 instruction that is VOP3-only on VI.
1110 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1111 dag ins32, string asm32, list<dag> pat32,
1112 dag ins64, string asm64, list<dag> pat64,
1113 string revOpSI, string revOpVI, bit HasMods> {
1114 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOpSI>;
1116 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1117 revOpSI, revOpVI, HasMods>;
1120 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1121 SDPatternOperator node = null_frag,
1122 string revOpSI = opName, string revOpVI = revOpSI>
1125 P.Ins32, P.Asm32, [],
1129 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1130 i1:$clamp, i32:$omod)),
1131 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1132 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1133 revOpSI, revOpVI, P.HasModifiers
1136 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1137 VOPCCommon <ins, "", pattern>,
1139 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1143 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1144 string opName, bit DefExec> {
1145 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1147 def _si : VOPC<op.SI, ins, asm, []>,
1148 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1149 let Defs = !if(DefExec, [EXEC], []);
1152 def _vi : VOPC<op.VI, ins, asm, []>,
1153 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1154 let Defs = !if(DefExec, [EXEC], []);
1158 multiclass VOPC_Helper <vopc op, string opName,
1159 dag ins32, string asm32, list<dag> pat32,
1160 dag out64, dag ins64, string asm64, list<dag> pat64,
1161 bit HasMods, bit DefExec> {
1162 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1164 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1165 opName, HasMods, DefExec>;
1168 multiclass VOPCInst <vopc op, string opName,
1169 VOPProfile P, PatLeaf cond = COND_NULL,
1170 bit DefExec = 0> : VOPC_Helper <
1172 P.Ins32, P.Asm32, [],
1173 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1176 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1177 i1:$clamp, i32:$omod)),
1178 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1180 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1181 P.HasModifiers, DefExec
1184 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1185 bit DefExec = 0> : VOPC_Helper <
1187 P.Ins32, P.Asm32, [],
1188 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1191 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1192 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1193 P.HasModifiers, DefExec
1197 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1198 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1200 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1201 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1203 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1204 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1206 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1207 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1210 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1211 PatLeaf cond = COND_NULL>
1212 : VOPCInst <op, opName, P, cond, 1>;
1214 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1215 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1217 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1218 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1220 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1221 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1223 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1224 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1226 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1227 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1228 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1231 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1232 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1234 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1235 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1237 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1238 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1240 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1241 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1243 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1244 SDPatternOperator node = null_frag> : VOP3_Helper <
1245 op, opName, P.Outs, P.Ins64, P.Asm64,
1246 !if(!eq(P.NumSrcArgs, 3),
1249 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1250 i1:$clamp, i32:$omod)),
1251 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1252 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1253 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1255 !if(!eq(P.NumSrcArgs, 2),
1258 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1259 i1:$clamp, i32:$omod)),
1260 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1261 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1262 /* P.NumSrcArgs == 1 */,
1265 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1266 i1:$clamp, i32:$omod))))],
1267 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1268 P.NumSrcArgs, P.HasModifiers
1271 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1272 string opName, list<dag> pattern> :
1274 op, (outs vrc:$vdst, SReg_64:$sdst),
1275 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1276 InputModsNoDefault:$src1_modifiers, arc:$src1,
1277 InputModsNoDefault:$src2_modifiers, arc:$src2,
1278 ClampMod:$clamp, omod:$omod),
1279 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1280 opName, opName, 1, 1
1283 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1284 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1286 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1287 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1290 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1291 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1292 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1293 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1294 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1295 i32:$src1_modifiers, P.Src1VT:$src1,
1296 i32:$src2_modifiers, P.Src2VT:$src2,
1300 //===----------------------------------------------------------------------===//
1301 // Interpolation opcodes
1302 //===----------------------------------------------------------------------===//
1304 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1305 VINTRPCommon <outs, ins, "", pattern>,
1306 SIMCInstr<opName, SISubtarget.NONE> {
1310 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1312 VINTRPCommon <outs, ins, asm, []>,
1314 SIMCInstr<opName, SISubtarget.SI>;
1316 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1318 VINTRPCommon <outs, ins, asm, []>,
1320 SIMCInstr<opName, SISubtarget.VI>;
1322 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1323 string disableEncoding = "", string constraints = "",
1324 list<dag> pattern = []> {
1325 let DisableEncoding = disableEncoding,
1326 Constraints = constraints in {
1327 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1329 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1331 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1335 //===----------------------------------------------------------------------===//
1336 // Vector I/O classes
1337 //===----------------------------------------------------------------------===//
1339 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1340 DS <outs, ins, "", pattern>,
1341 SIMCInstr <opName, SISubtarget.NONE> {
1345 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1346 DS <outs, ins, asm, []>,
1348 SIMCInstr <opName, SISubtarget.SI>;
1350 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1351 DS <outs, ins, asm, []>,
1353 SIMCInstr <opName, SISubtarget.VI>;
1355 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1356 DS <outs, ins, asm, []>,
1358 SIMCInstr <opName, SISubtarget.SI> {
1360 // Single load interpret the 2 i8imm operands as a single i16 offset.
1362 let offset0 = offset{7-0};
1363 let offset1 = offset{15-8};
1366 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1367 DS <outs, ins, asm, []>,
1369 SIMCInstr <opName, SISubtarget.VI> {
1371 // Single load interpret the 2 i8imm operands as a single i16 offset.
1373 let offset0 = offset{7-0};
1374 let offset1 = offset{15-8};
1377 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1379 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1380 def "" : DS_Pseudo <opName, outs, ins, pat>;
1382 let data0 = 0, data1 = 0 in {
1383 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1384 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1389 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1393 (outs regClass:$vdst),
1394 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1395 asm#" $vdst, $addr"#"$offset"#" [M0]",
1398 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1400 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1401 def "" : DS_Pseudo <opName, outs, ins, pat>;
1403 let data0 = 0, data1 = 0 in {
1404 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1405 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1410 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1414 (outs regClass:$vdst),
1415 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1417 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1420 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1421 string asm, list<dag> pat> {
1422 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1423 def "" : DS_Pseudo <opName, outs, ins, pat>;
1425 let data1 = 0, vdst = 0 in {
1426 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1427 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1432 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1437 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1438 asm#" $addr, $data0"#"$offset"#" [M0]",
1441 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1442 string asm, list<dag> pat> {
1443 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1444 def "" : DS_Pseudo <opName, outs, ins, pat>;
1447 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1448 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1453 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1458 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1459 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1460 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1463 // 1 address, 1 data.
1464 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1465 string asm, list<dag> pat, string noRetOp> {
1466 let mayLoad = 1, mayStore = 1,
1467 hasPostISelHook = 1 // Adjusted to no return version.
1469 def "" : DS_Pseudo <opName, outs, ins, pat>,
1470 AtomicNoRet<noRetOp, 1>;
1473 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1474 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1479 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1480 string noRetOp = ""> : DS_1A1D_RET_m <
1483 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1484 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1486 // 1 address, 2 data.
1487 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1488 string asm, list<dag> pat, string noRetOp> {
1489 let mayLoad = 1, mayStore = 1,
1490 hasPostISelHook = 1 // Adjusted to no return version.
1492 def "" : DS_Pseudo <opName, outs, ins, pat>,
1493 AtomicNoRet<noRetOp, 1>;
1495 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1496 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1500 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1501 string noRetOp = ""> : DS_1A2D_RET_m <
1504 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1505 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1508 // 1 address, 2 data.
1509 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1510 string asm, list<dag> pat, string noRetOp> {
1511 let mayLoad = 1, mayStore = 1 in {
1512 def "" : DS_Pseudo <opName, outs, ins, pat>,
1513 AtomicNoRet<noRetOp, 0>;
1515 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1516 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1520 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1521 string noRetOp = asm> : DS_1A2D_NORET_m <
1524 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1525 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1528 // 1 address, 1 data.
1529 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1530 string asm, list<dag> pat, string noRetOp> {
1531 let mayLoad = 1, mayStore = 1 in {
1532 def "" : DS_Pseudo <opName, outs, ins, pat>,
1533 AtomicNoRet<noRetOp, 0>;
1536 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1537 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1542 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1543 string noRetOp = asm> : DS_1A1D_NORET_m <
1546 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1547 asm#" $addr, $data0"#"$offset"#" [M0]",
1550 //===----------------------------------------------------------------------===//
1552 //===----------------------------------------------------------------------===//
1554 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1555 MTBUF <outs, ins, "", pattern>,
1556 SIMCInstr<opName, SISubtarget.NONE> {
1560 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1562 MTBUF <outs, ins, asm, []>,
1564 SIMCInstr<opName, SISubtarget.SI>;
1566 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1567 MTBUF <outs, ins, asm, []>,
1569 SIMCInstr <opName, SISubtarget.VI>;
1571 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1572 list<dag> pattern> {
1574 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1576 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1578 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1582 let mayStore = 1, mayLoad = 0 in {
1584 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1585 RegisterClass regClass> : MTBUF_m <
1587 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1588 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1589 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1590 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1591 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1594 } // mayStore = 1, mayLoad = 0
1596 let mayLoad = 1, mayStore = 0 in {
1598 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1599 RegisterClass regClass> : MTBUF_m <
1600 op, opName, (outs regClass:$dst),
1601 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1602 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1603 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1604 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1605 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1608 } // mayLoad = 1, mayStore = 0
1610 //===----------------------------------------------------------------------===//
1612 //===----------------------------------------------------------------------===//
1614 class mubuf <bits<7> si, bits<7> vi = si> {
1615 field bits<7> SI = si;
1616 field bits<7> VI = vi;
1619 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1620 bit IsAddr64 = is_addr64;
1621 string OpName = NAME # suffix;
1624 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1625 MUBUF <outs, ins, "", pattern>,
1626 SIMCInstr<opName, SISubtarget.NONE> {
1629 // dummy fields, so that we can use let statements around multiclasses
1639 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1641 MUBUF <outs, ins, asm, []>,
1643 SIMCInstr<opName, SISubtarget.SI> {
1647 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1649 MUBUF <outs, ins, asm, []>,
1651 SIMCInstr<opName, SISubtarget.VI> {
1655 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1656 list<dag> pattern> {
1658 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1659 MUBUFAddr64Table <0>;
1662 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1665 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1668 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1669 dag ins, string asm, list<dag> pattern> {
1671 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1672 MUBUFAddr64Table <1>;
1675 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1678 // There is no VI version. If the pseudo is selected, it should be lowered
1679 // for VI appropriately.
1682 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1683 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1687 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1688 string asm, list<dag> pattern, bit is_return> {
1690 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1691 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1692 AtomicNoRet<NAME#"_OFFSET", is_return>;
1694 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1696 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1699 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1703 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1704 string asm, list<dag> pattern, bit is_return> {
1706 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1707 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1708 AtomicNoRet<NAME#"_ADDR64", is_return>;
1710 let offen = 0, idxen = 0, addr64 = 1, tfe = 0, soffset = 128 in {
1711 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1714 // There is no VI version. If the pseudo is selected, it should be lowered
1715 // for VI appropriately.
1718 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1719 ValueType vt, SDPatternOperator atomic> {
1721 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1723 // No return variants
1726 defm _ADDR64 : MUBUFAtomicAddr64_m <
1727 op, name#"_addr64", (outs),
1728 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1729 mbuf_offset:$offset, slc:$slc),
1730 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", [], 0
1733 defm _OFFSET : MUBUFAtomicOffset_m <
1734 op, name#"_offset", (outs),
1735 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1736 SCSrc_32:$soffset, slc:$slc),
1737 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1741 // Variant that return values
1742 let glc = 1, Constraints = "$vdata = $vdata_in",
1743 DisableEncoding = "$vdata_in" in {
1745 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1746 op, name#"_rtn_addr64", (outs rc:$vdata),
1747 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1748 mbuf_offset:$offset, slc:$slc),
1749 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1751 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1752 i1:$slc), vt:$vdata_in))], 1
1755 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1756 op, name#"_rtn_offset", (outs rc:$vdata),
1757 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1758 SCSrc_32:$soffset, slc:$slc),
1759 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1761 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1762 i1:$slc), vt:$vdata_in))], 1
1767 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1770 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1771 ValueType load_vt = i32,
1772 SDPatternOperator ld = null_frag> {
1774 let mayLoad = 1, mayStore = 0 in {
1775 let offen = 0, idxen = 0, vaddr = 0 in {
1776 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1777 (ins SReg_128:$srsrc,
1778 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1779 slc:$slc, tfe:$tfe),
1780 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1781 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1782 i32:$soffset, i16:$offset,
1783 i1:$glc, i1:$slc, i1:$tfe)))]>;
1786 let offen = 1, idxen = 0 in {
1787 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1788 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1789 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1791 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1794 let offen = 0, idxen = 1 in {
1795 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1796 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1797 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1798 slc:$slc, tfe:$tfe),
1799 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1802 let offen = 1, idxen = 1 in {
1803 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1804 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1805 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1806 name#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1809 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1810 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1811 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1812 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1813 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1814 i64:$vaddr, i16:$offset)))]>;
1819 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1820 ValueType store_vt, SDPatternOperator st> {
1821 let mayLoad = 0, mayStore = 1 in {
1822 defm : MUBUF_m <op, name, (outs),
1823 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1824 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1826 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1827 "$glc"#"$slc"#"$tfe", []>;
1829 let offen = 0, idxen = 0, vaddr = 0 in {
1830 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1831 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1832 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1833 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1834 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1835 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1836 } // offen = 0, idxen = 0, vaddr = 0
1838 let offen = 1, idxen = 0 in {
1839 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1840 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1841 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1842 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1843 "$glc"#"$slc"#"$tfe", []>;
1844 } // end offen = 1, idxen = 0
1846 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0,
1847 soffset = 128 /* ZERO */ in {
1848 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1849 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1850 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1851 [(st store_vt:$vdata,
1852 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>;
1854 } // End mayLoad = 0, mayStore = 1
1857 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1858 FLAT <op, (outs regClass:$data),
1859 (ins VReg_64:$addr),
1860 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1867 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1868 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1869 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1881 class MIMG_Mask <string op, int channels> {
1883 int Channels = channels;
1886 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1887 RegisterClass dst_rc,
1888 RegisterClass src_rc> : MIMG <
1890 (outs dst_rc:$vdata),
1891 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1892 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1894 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1895 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1900 let hasPostISelHook = 1;
1903 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1904 RegisterClass dst_rc,
1906 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1907 MIMG_Mask<asm#"_V1", channels>;
1908 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1909 MIMG_Mask<asm#"_V2", channels>;
1910 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1911 MIMG_Mask<asm#"_V4", channels>;
1914 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1915 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1916 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1917 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1918 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1921 class MIMG_Sampler_Helper <bits<7> op, string asm,
1922 RegisterClass dst_rc,
1923 RegisterClass src_rc> : MIMG <
1925 (outs dst_rc:$vdata),
1926 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1927 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1928 SReg_256:$srsrc, SReg_128:$ssamp),
1929 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1930 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1934 let hasPostISelHook = 1;
1937 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1938 RegisterClass dst_rc,
1940 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32>,
1941 MIMG_Mask<asm#"_V1", channels>;
1942 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1943 MIMG_Mask<asm#"_V2", channels>;
1944 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1945 MIMG_Mask<asm#"_V4", channels>;
1946 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1947 MIMG_Mask<asm#"_V8", channels>;
1948 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1949 MIMG_Mask<asm#"_V16", channels>;
1952 multiclass MIMG_Sampler <bits<7> op, string asm> {
1953 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1>;
1954 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1955 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1956 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1959 class MIMG_Gather_Helper <bits<7> op, string asm,
1960 RegisterClass dst_rc,
1961 RegisterClass src_rc> : MIMG <
1963 (outs dst_rc:$vdata),
1964 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1965 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1966 SReg_256:$srsrc, SReg_128:$ssamp),
1967 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1968 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1973 // DMASK was repurposed for GATHER4. 4 components are always
1974 // returned and DMASK works like a swizzle - it selects
1975 // the component to fetch. The only useful DMASK values are
1976 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1977 // (red,red,red,red) etc.) The ISA document doesn't mention
1979 // Therefore, disable all code which updates DMASK by setting these two:
1981 let hasPostISelHook = 0;
1984 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1985 RegisterClass dst_rc,
1987 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32>,
1988 MIMG_Mask<asm#"_V1", channels>;
1989 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1990 MIMG_Mask<asm#"_V2", channels>;
1991 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1992 MIMG_Mask<asm#"_V4", channels>;
1993 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1994 MIMG_Mask<asm#"_V8", channels>;
1995 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1996 MIMG_Mask<asm#"_V16", channels>;
1999 multiclass MIMG_Gather <bits<7> op, string asm> {
2000 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1>;
2001 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
2002 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
2003 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
2006 //===----------------------------------------------------------------------===//
2007 // Vector instruction mappings
2008 //===----------------------------------------------------------------------===//
2010 // Maps an opcode in e32 form to its e64 equivalent
2011 def getVOPe64 : InstrMapping {
2012 let FilterClass = "VOP";
2013 let RowFields = ["OpName"];
2014 let ColFields = ["Size"];
2016 let ValueCols = [["8"]];
2019 // Maps an opcode in e64 form to its e32 equivalent
2020 def getVOPe32 : InstrMapping {
2021 let FilterClass = "VOP";
2022 let RowFields = ["OpName"];
2023 let ColFields = ["Size"];
2025 let ValueCols = [["4"]];
2028 // Maps an original opcode to its commuted version
2029 def getCommuteRev : InstrMapping {
2030 let FilterClass = "VOP2_REV";
2031 let RowFields = ["RevOp"];
2032 let ColFields = ["IsOrig"];
2034 let ValueCols = [["0"]];
2037 def getMaskedMIMGOp : InstrMapping {
2038 let FilterClass = "MIMG_Mask";
2039 let RowFields = ["Op"];
2040 let ColFields = ["Channels"];
2042 let ValueCols = [["1"], ["2"], ["3"] ];
2045 // Maps an commuted opcode to its original version
2046 def getCommuteOrig : InstrMapping {
2047 let FilterClass = "VOP2_REV";
2048 let RowFields = ["RevOp"];
2049 let ColFields = ["IsOrig"];
2051 let ValueCols = [["1"]];
2054 def getMCOpcodeGen : InstrMapping {
2055 let FilterClass = "SIMCInstr";
2056 let RowFields = ["PseudoInstr"];
2057 let ColFields = ["Subtarget"];
2058 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2059 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2062 def getAddr64Inst : InstrMapping {
2063 let FilterClass = "MUBUFAddr64Table";
2064 let RowFields = ["OpName"];
2065 let ColFields = ["IsAddr64"];
2067 let ValueCols = [["1"]];
2070 // Maps an atomic opcode to its version with a return value.
2071 def getAtomicRetOp : InstrMapping {
2072 let FilterClass = "AtomicNoRet";
2073 let RowFields = ["NoRetOp"];
2074 let ColFields = ["IsRet"];
2076 let ValueCols = [["1"]];
2079 // Maps an atomic opcode to its returnless version.
2080 def getAtomicNoRetOp : InstrMapping {
2081 let FilterClass = "AtomicNoRet";
2082 let RowFields = ["NoRetOp"];
2083 let ColFields = ["IsRet"];
2085 let ValueCols = [["0"]];
2088 include "SIInstructions.td"
2089 include "CIInstructions.td"
2090 include "VIInstructions.td"