1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
386 SOP1 <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
391 SOP1 <outs, ins, asm, []>,
393 SIMCInstr<opName, SISubtarget.VI>;
395 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
398 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
400 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
402 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
406 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
407 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
408 opName#" $dst, $src0", pattern
411 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
412 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
413 opName#" $dst, $src0", pattern
416 // no input, 64-bit output.
417 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
418 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
420 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
425 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
431 // 64-bit input, 32-bit output.
432 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
433 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
434 opName#" $dst, $src0", pattern
437 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
438 SOP2<outs, ins, "", pattern>,
439 SIMCInstr<opName, SISubtarget.NONE> {
444 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
445 SOP2<outs, ins, asm, []>,
447 SIMCInstr<opName, SISubtarget.SI>;
449 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
450 SOP2<outs, ins, asm, []>,
452 SIMCInstr<opName, SISubtarget.VI>;
454 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
455 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
456 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
458 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
459 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
460 opName#" $dst, $src0, $src1 [$scc]">;
462 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
463 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
464 opName#" $dst, $src0, $src1 [$scc]">;
467 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
468 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
469 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
471 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
472 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
474 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
475 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
478 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
479 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
480 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
482 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
483 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
485 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
486 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
489 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
490 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
491 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
493 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
494 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
496 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
497 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
501 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
502 string opName, PatLeaf cond> : SOPC <
503 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
504 opName#" $dst, $src0, $src1", []>;
506 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
507 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
509 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
510 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
512 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
513 SOPK <outs, ins, "", pattern>,
514 SIMCInstr<opName, SISubtarget.NONE> {
518 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
519 SOPK <outs, ins, asm, []>,
521 SIMCInstr<opName, SISubtarget.SI>;
523 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
524 SOPK <outs, ins, asm, []>,
526 SIMCInstr<opName, SISubtarget.VI>;
528 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
529 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
532 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
533 opName#" $dst, $src0">;
535 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
536 opName#" $dst, $src0">;
539 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
540 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
541 (ins SReg_32:$src0, u16imm:$src1), pattern>;
543 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
544 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
546 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
547 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
550 //===----------------------------------------------------------------------===//
552 //===----------------------------------------------------------------------===//
554 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
555 SMRD <outs, ins, "", pattern>,
556 SIMCInstr<opName, SISubtarget.NONE> {
560 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
562 SMRD <outs, ins, asm, []>,
564 SIMCInstr<opName, SISubtarget.SI>;
566 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
568 SMRD <outs, ins, asm, []>,
570 SIMCInstr<opName, SISubtarget.VI>;
572 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
573 string asm, list<dag> pattern> {
575 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
577 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
579 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
582 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
583 RegisterClass dstClass> {
585 op, opName#"_IMM", 1, (outs dstClass:$dst),
586 (ins baseClass:$sbase, u32imm:$offset),
587 opName#" $dst, $sbase, $offset", []
590 defm _SGPR : SMRD_m <
591 op, opName#"_SGPR", 0, (outs dstClass:$dst),
592 (ins baseClass:$sbase, SReg_32:$soff),
593 opName#" $dst, $sbase, $soff", []
597 //===----------------------------------------------------------------------===//
598 // Vector ALU classes
599 //===----------------------------------------------------------------------===//
601 // This must always be right before the operand being input modified.
602 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
603 let PrintMethod = "printOperandAndMods";
605 def InputModsNoDefault : Operand <i32> {
606 let PrintMethod = "printOperandAndMods";
609 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
611 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
612 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
616 // Returns the register class to use for the destination of VOP[123C]
617 // instructions for the given VT.
618 class getVALUDstForVT<ValueType VT> {
619 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
620 !if(!eq(VT.Size, 64), VReg_64,
621 SReg_64)); // else VT == i1
624 // Returns the register class to use for source 0 of VOP[12C]
625 // instructions for the given VT.
626 class getVOPSrc0ForVT<ValueType VT> {
627 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
630 // Returns the register class to use for source 1 of VOP[12C] for the
632 class getVOPSrc1ForVT<ValueType VT> {
633 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
636 // Returns the register class to use for sources of VOP3 instructions for the
638 class getVOP3SrcForVT<ValueType VT> {
639 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
642 // Returns 1 if the source arguments have modifiers, 0 if they do not.
643 class hasModifiers<ValueType SrcVT> {
644 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
645 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
648 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
649 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
650 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
651 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
655 // Returns the input arguments for VOP3 instructions for the given SrcVT.
656 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
657 RegisterOperand Src2RC, int NumSrcArgs,
661 !if (!eq(NumSrcArgs, 1),
662 !if (!eq(HasModifiers, 1),
663 // VOP1 with modifiers
664 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
665 ClampMod:$clamp, omod:$omod)
667 // VOP1 without modifiers
670 !if (!eq(NumSrcArgs, 2),
671 !if (!eq(HasModifiers, 1),
672 // VOP 2 with modifiers
673 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
674 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
675 ClampMod:$clamp, omod:$omod)
677 // VOP2 without modifiers
678 (ins Src0RC:$src0, Src1RC:$src1)
680 /* NumSrcArgs == 3 */,
681 !if (!eq(HasModifiers, 1),
682 // VOP3 with modifiers
683 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
684 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
685 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
686 ClampMod:$clamp, omod:$omod)
688 // VOP3 without modifiers
689 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
693 // Returns the assembly string for the inputs and outputs of a VOP[12C]
694 // instruction. This does not add the _e32 suffix, so it can be reused
696 class getAsm32 <int NumSrcArgs> {
697 string src1 = ", $src1";
698 string src2 = ", $src2";
699 string ret = " $dst, $src0"#
700 !if(!eq(NumSrcArgs, 1), "", src1)#
701 !if(!eq(NumSrcArgs, 3), src2, "");
704 // Returns the assembly string for the inputs and outputs of a VOP3
706 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
707 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
708 string src1 = !if(!eq(NumSrcArgs, 1), "",
709 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
710 " $src1_modifiers,"));
711 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
713 !if(!eq(HasModifiers, 0),
714 getAsm32<NumSrcArgs>.ret,
715 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
719 class VOPProfile <list<ValueType> _ArgVT> {
721 field list<ValueType> ArgVT = _ArgVT;
723 field ValueType DstVT = ArgVT[0];
724 field ValueType Src0VT = ArgVT[1];
725 field ValueType Src1VT = ArgVT[2];
726 field ValueType Src2VT = ArgVT[3];
727 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
728 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
729 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
730 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
731 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
732 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
734 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
735 field bit HasModifiers = hasModifiers<Src0VT>.ret;
737 field dag Outs = (outs DstRC:$dst);
739 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
740 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
743 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
744 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
747 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
748 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
749 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
750 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
751 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
752 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
753 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
754 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
755 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
757 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
758 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
759 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
760 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
761 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
762 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
763 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
764 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
765 let Src0RC32 = VCSrc_32;
768 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
769 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
770 let Asm64 = " $dst, $src0_modifiers, $src1";
773 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
774 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
775 let Asm64 = " $dst, $src0_modifiers, $src1";
778 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
779 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
780 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
782 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
783 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
784 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
785 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
788 class VOP <string opName> {
789 string OpName = opName;
792 class VOP2_REV <string revOp, bit isOrig> {
793 string RevOp = revOp;
797 class AtomicNoRet <string noRetOp, bit isRet> {
798 string NoRetOp = noRetOp;
802 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
803 VOP1Common <outs, ins, "", pattern>,
805 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
809 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
811 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
813 def _si : VOP1<op.SI, outs, ins, asm, []>,
814 SIMCInstr <opName#"_e32", SISubtarget.SI>;
815 def _vi : VOP1<op.VI, outs, ins, asm, []>,
816 SIMCInstr <opName#"_e32", SISubtarget.VI>;
819 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
821 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
823 def _si : VOP1<op.SI, outs, ins, asm, []>,
824 SIMCInstr <opName#"_e32", SISubtarget.SI>;
825 // No VI instruction. This class is for SI only.
828 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
829 VOP2Common <outs, ins, "", pattern>,
831 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
835 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
836 string opName, string revOp> {
837 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
838 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
840 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
841 SIMCInstr <opName#"_e32", SISubtarget.SI>;
844 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
845 string opName, string revOp> {
846 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
847 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
849 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
850 SIMCInstr <opName#"_e32", SISubtarget.SI>;
851 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
852 SIMCInstr <opName#"_e32", SISubtarget.VI>;
855 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
857 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
858 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
859 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
860 bits<2> omod = !if(HasModifiers, ?, 0);
861 bits<1> clamp = !if(HasModifiers, ?, 0);
862 bits<9> src1 = !if(HasSrc1, ?, 0);
863 bits<9> src2 = !if(HasSrc2, ?, 0);
866 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
867 VOP3Common <outs, ins, "", pattern>,
869 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
873 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
874 VOP3Common <outs, ins, asm, []>,
876 SIMCInstr<opName#"_e64", SISubtarget.SI>;
878 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
879 VOP3Common <outs, ins, asm, []>,
881 SIMCInstr <opName#"_e64", SISubtarget.VI>;
883 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
884 string opName, int NumSrcArgs, bit HasMods = 1> {
886 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
888 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
889 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
890 !if(!eq(NumSrcArgs, 2), 0, 1),
892 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
893 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
894 !if(!eq(NumSrcArgs, 2), 0, 1),
898 // VOP3_m without source modifiers
899 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
900 string opName, int NumSrcArgs, bit HasMods = 1> {
902 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
904 let src0_modifiers = 0,
906 src2_modifiers = 0 in {
907 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
908 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
912 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
913 list<dag> pattern, string opName, bit HasMods = 1> {
915 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
917 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
918 VOP3DisableFields<0, 0, HasMods>;
920 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
921 VOP3DisableFields<0, 0, HasMods>;
924 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
925 list<dag> pattern, string opName, bit HasMods = 1> {
927 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
929 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
930 VOP3DisableFields<0, 0, HasMods>;
931 // No VI instruction. This class is for SI only.
934 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
935 list<dag> pattern, string opName, string revOp,
936 bit HasMods = 1, bit UseFullOp = 0> {
938 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
939 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
941 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
942 VOP3DisableFields<1, 0, HasMods>;
944 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
945 VOP3DisableFields<1, 0, HasMods>;
948 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
949 list<dag> pattern, string opName, string revOp,
950 bit HasMods = 1, bit UseFullOp = 0> {
952 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
953 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
955 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
956 VOP3DisableFields<1, 0, HasMods>;
958 // No VI instruction. This class is for SI only.
961 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
962 list<dag> pattern, string opName, string revOp,
963 bit HasMods = 1, bit UseFullOp = 0> {
964 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
965 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
967 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
968 // can write it into any SGPR. We currently don't use the carry out,
969 // so for now hardcode it to VCC as well.
970 let sdst = SIOperand.VCC, Defs = [VCC] in {
971 def _si : VOP3b <op.SI3, outs, ins, asm, []>,
972 VOP3DisableFields<1, 0, HasMods>,
973 SIMCInstr<opName#"_e64", SISubtarget.SI>;
975 // TODO: Do we need this VI variant here?
976 /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, []>,
977 VOP3DisableFields<1, 0, HasMods>,
978 SIMCInstr<opName#"_e64", SISubtarget.VI>;*/
979 } // End sdst = SIOperand.VCC, Defs = [VCC]
982 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
983 list<dag> pattern, string opName,
984 bit HasMods, bit defExec> {
986 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
988 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
989 VOP3DisableFields<1, 0, HasMods> {
990 let Defs = !if(defExec, [EXEC], []);
993 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
994 VOP3DisableFields<1, 0, HasMods> {
995 let Defs = !if(defExec, [EXEC], []);
999 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1000 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1001 string asm, list<dag> pattern = []> {
1002 let isPseudo = 1 in {
1003 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1004 SIMCInstr<opName, SISubtarget.NONE>;
1007 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1008 SIMCInstr <opName, SISubtarget.SI>;
1010 def _vi : VOP3Common <outs, ins, asm, []>,
1012 VOP3DisableFields <1, 0, 0>,
1013 SIMCInstr <opName, SISubtarget.VI>;
1016 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1017 dag ins32, string asm32, list<dag> pat32,
1018 dag ins64, string asm64, list<dag> pat64,
1021 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1023 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1026 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1027 SDPatternOperator node = null_frag> : VOP1_Helper <
1029 P.Ins32, P.Asm32, [],
1032 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1033 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1034 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1038 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1039 SDPatternOperator node = null_frag> {
1041 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1043 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1045 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1046 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1047 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1048 opName, P.HasModifiers>;
1051 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1052 dag ins32, string asm32, list<dag> pat32,
1053 dag ins64, string asm64, list<dag> pat64,
1054 string revOp, bit HasMods> {
1055 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1057 defm _e64 : VOP3_2_m <op,
1058 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1062 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1063 SDPatternOperator node = null_frag,
1064 string revOp = opName> : VOP2_Helper <
1066 P.Ins32, P.Asm32, [],
1070 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1071 i1:$clamp, i32:$omod)),
1072 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1073 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1074 revOp, P.HasModifiers
1077 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1078 SDPatternOperator node = null_frag,
1079 string revOp = opName> {
1080 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1082 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1085 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1086 i1:$clamp, i32:$omod)),
1087 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1088 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1089 opName, revOp, P.HasModifiers>;
1092 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1093 dag ins32, string asm32, list<dag> pat32,
1094 dag ins64, string asm64, list<dag> pat64,
1095 string revOp, bit HasMods> {
1097 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1099 defm _e64 : VOP3b_2_m <op,
1100 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1104 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1105 SDPatternOperator node = null_frag,
1106 string revOp = opName> : VOP2b_Helper <
1108 P.Ins32, P.Asm32, [],
1112 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1113 i1:$clamp, i32:$omod)),
1114 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1115 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1116 revOp, P.HasModifiers
1119 // A VOP2 instruction that is VOP3-only on VI.
1120 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1121 dag ins32, string asm32, list<dag> pat32,
1122 dag ins64, string asm64, list<dag> pat64,
1123 string revOp, bit HasMods> {
1124 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1126 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1130 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1131 SDPatternOperator node = null_frag,
1132 string revOp = opName>
1135 P.Ins32, P.Asm32, [],
1139 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1140 i1:$clamp, i32:$omod)),
1141 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1142 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1143 revOp, P.HasModifiers
1146 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1147 VOPCCommon <ins, "", pattern>,
1149 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1153 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1154 string opName, bit DefExec> {
1155 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1157 def _si : VOPC<op.SI, ins, asm, []>,
1158 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1159 let Defs = !if(DefExec, [EXEC], []);
1162 def _vi : VOPC<op.VI, ins, asm, []>,
1163 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1164 let Defs = !if(DefExec, [EXEC], []);
1168 multiclass VOPC_Helper <vopc op, string opName,
1169 dag ins32, string asm32, list<dag> pat32,
1170 dag out64, dag ins64, string asm64, list<dag> pat64,
1171 bit HasMods, bit DefExec> {
1172 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1174 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1175 opName, HasMods, DefExec>;
1178 multiclass VOPCInst <vopc op, string opName,
1179 VOPProfile P, PatLeaf cond = COND_NULL,
1180 bit DefExec = 0> : VOPC_Helper <
1182 P.Ins32, P.Asm32, [],
1183 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1186 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1187 i1:$clamp, i32:$omod)),
1188 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1190 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1191 P.HasModifiers, DefExec
1194 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1195 bit DefExec = 0> : VOPC_Helper <
1197 P.Ins32, P.Asm32, [],
1198 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1201 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1202 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1203 P.HasModifiers, DefExec
1207 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1208 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1210 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1211 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1213 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1214 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1216 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1217 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1220 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1221 PatLeaf cond = COND_NULL>
1222 : VOPCInst <op, opName, P, cond, 1>;
1224 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1225 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1227 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1228 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1230 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1231 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1233 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1234 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1236 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1237 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1238 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1241 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1242 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1244 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1245 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1247 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1248 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1250 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1251 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1253 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1254 SDPatternOperator node = null_frag> : VOP3_Helper <
1255 op, opName, P.Outs, P.Ins64, P.Asm64,
1256 !if(!eq(P.NumSrcArgs, 3),
1259 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1260 i1:$clamp, i32:$omod)),
1261 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1262 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1263 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1265 !if(!eq(P.NumSrcArgs, 2),
1268 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1269 i1:$clamp, i32:$omod)),
1270 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1271 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1272 /* P.NumSrcArgs == 1 */,
1275 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1276 i1:$clamp, i32:$omod))))],
1277 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1278 P.NumSrcArgs, P.HasModifiers
1281 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1282 string opName, list<dag> pattern> :
1284 op, (outs vrc:$vdst, SReg_64:$sdst),
1285 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1286 InputModsNoDefault:$src1_modifiers, arc:$src1,
1287 InputModsNoDefault:$src2_modifiers, arc:$src2,
1288 ClampMod:$clamp, omod:$omod),
1289 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1290 opName, opName, 1, 1
1293 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1294 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1296 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1297 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1300 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1301 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1302 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1303 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1304 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1305 i32:$src1_modifiers, P.Src1VT:$src1,
1306 i32:$src2_modifiers, P.Src2VT:$src2,
1310 //===----------------------------------------------------------------------===//
1311 // Interpolation opcodes
1312 //===----------------------------------------------------------------------===//
1314 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1315 VINTRPCommon <outs, ins, "", pattern>,
1316 SIMCInstr<opName, SISubtarget.NONE> {
1320 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1322 VINTRPCommon <outs, ins, asm, []>,
1324 SIMCInstr<opName, SISubtarget.SI>;
1326 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1328 VINTRPCommon <outs, ins, asm, []>,
1330 SIMCInstr<opName, SISubtarget.VI>;
1332 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1333 string disableEncoding = "", string constraints = "",
1334 list<dag> pattern = []> {
1335 let DisableEncoding = disableEncoding,
1336 Constraints = constraints in {
1337 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1339 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1341 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1345 //===----------------------------------------------------------------------===//
1346 // Vector I/O classes
1347 //===----------------------------------------------------------------------===//
1349 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1350 DS <outs, ins, "", pattern>,
1351 SIMCInstr <opName, SISubtarget.NONE> {
1355 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1356 DS <outs, ins, asm, []>,
1358 SIMCInstr <opName, SISubtarget.SI>;
1360 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1361 DS <outs, ins, asm, []>,
1363 SIMCInstr <opName, SISubtarget.VI>;
1365 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1366 DS <outs, ins, asm, []>,
1368 SIMCInstr <opName, SISubtarget.SI> {
1370 // Single load interpret the 2 i8imm operands as a single i16 offset.
1372 let offset0 = offset{7-0};
1373 let offset1 = offset{15-8};
1376 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1377 DS <outs, ins, asm, []>,
1379 SIMCInstr <opName, SISubtarget.VI> {
1381 // Single load interpret the 2 i8imm operands as a single i16 offset.
1383 let offset0 = offset{7-0};
1384 let offset1 = offset{15-8};
1387 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1389 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1390 def "" : DS_Pseudo <opName, outs, ins, pat>;
1392 let data0 = 0, data1 = 0 in {
1393 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1394 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1399 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1403 (outs regClass:$vdst),
1404 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1405 asm#" $vdst, $addr"#"$offset"#" [M0]",
1408 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1410 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1411 def "" : DS_Pseudo <opName, outs, ins, pat>;
1413 let data0 = 0, data1 = 0 in {
1414 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1415 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1420 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1424 (outs regClass:$vdst),
1425 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1427 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1430 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1431 string asm, list<dag> pat> {
1432 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1433 def "" : DS_Pseudo <opName, outs, ins, pat>;
1435 let data1 = 0, vdst = 0 in {
1436 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1437 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1442 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1447 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1448 asm#" $addr, $data0"#"$offset"#" [M0]",
1451 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1452 string asm, list<dag> pat> {
1453 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1454 def "" : DS_Pseudo <opName, outs, ins, pat>;
1457 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1458 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1463 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1468 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1469 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1470 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1473 // 1 address, 1 data.
1474 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1475 string asm, list<dag> pat, string noRetOp> {
1476 let mayLoad = 1, mayStore = 1,
1477 hasPostISelHook = 1 // Adjusted to no return version.
1479 def "" : DS_Pseudo <opName, outs, ins, pat>,
1480 AtomicNoRet<noRetOp, 1>;
1483 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1484 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1489 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1490 string noRetOp = ""> : DS_1A1D_RET_m <
1493 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1494 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1496 // 1 address, 2 data.
1497 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1498 string asm, list<dag> pat, string noRetOp> {
1499 let mayLoad = 1, mayStore = 1,
1500 hasPostISelHook = 1 // Adjusted to no return version.
1502 def "" : DS_Pseudo <opName, outs, ins, pat>,
1503 AtomicNoRet<noRetOp, 1>;
1505 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1506 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1510 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1511 string noRetOp = ""> : DS_1A2D_RET_m <
1514 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1515 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1518 // 1 address, 2 data.
1519 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1520 string asm, list<dag> pat, string noRetOp> {
1521 let mayLoad = 1, mayStore = 1 in {
1522 def "" : DS_Pseudo <opName, outs, ins, pat>,
1523 AtomicNoRet<noRetOp, 0>;
1525 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1526 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1530 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1531 string noRetOp = asm> : DS_1A2D_NORET_m <
1534 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1535 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1538 // 1 address, 1 data.
1539 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1540 string asm, list<dag> pat, string noRetOp> {
1541 let mayLoad = 1, mayStore = 1 in {
1542 def "" : DS_Pseudo <opName, outs, ins, pat>,
1543 AtomicNoRet<noRetOp, 0>;
1546 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1547 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1552 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1553 string noRetOp = asm> : DS_1A1D_NORET_m <
1556 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1557 asm#" $addr, $data0"#"$offset"#" [M0]",
1560 //===----------------------------------------------------------------------===//
1562 //===----------------------------------------------------------------------===//
1564 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1565 MTBUF <outs, ins, "", pattern>,
1566 SIMCInstr<opName, SISubtarget.NONE> {
1570 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1572 MTBUF <outs, ins, asm, []>,
1574 SIMCInstr<opName, SISubtarget.SI>;
1576 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1577 MTBUF <outs, ins, asm, []>,
1579 SIMCInstr <opName, SISubtarget.VI>;
1581 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1582 list<dag> pattern> {
1584 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1586 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1588 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1592 let mayStore = 1, mayLoad = 0 in {
1594 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1595 RegisterClass regClass> : MTBUF_m <
1597 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1598 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1599 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1600 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1601 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1604 } // mayStore = 1, mayLoad = 0
1606 let mayLoad = 1, mayStore = 0 in {
1608 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1609 RegisterClass regClass> : MTBUF_m <
1610 op, opName, (outs regClass:$dst),
1611 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1612 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1613 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1614 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1615 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1618 } // mayLoad = 1, mayStore = 0
1620 //===----------------------------------------------------------------------===//
1622 //===----------------------------------------------------------------------===//
1624 class mubuf <bits<7> si, bits<7> vi = si> {
1625 field bits<7> SI = si;
1626 field bits<7> VI = vi;
1629 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1630 bit IsAddr64 = is_addr64;
1631 string OpName = NAME # suffix;
1634 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1635 MUBUF <outs, ins, "", pattern>,
1636 SIMCInstr<opName, SISubtarget.NONE> {
1639 // dummy fields, so that we can use let statements around multiclasses
1649 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1651 MUBUF <outs, ins, asm, []>,
1653 SIMCInstr<opName, SISubtarget.SI> {
1657 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1659 MUBUF <outs, ins, asm, []>,
1661 SIMCInstr<opName, SISubtarget.VI> {
1665 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1666 list<dag> pattern> {
1668 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1669 MUBUFAddr64Table <0>;
1672 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1675 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1678 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1679 dag ins, string asm, list<dag> pattern> {
1681 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1682 MUBUFAddr64Table <1>;
1685 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1688 // There is no VI version. If the pseudo is selected, it should be lowered
1689 // for VI appropriately.
1692 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1693 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1697 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1698 string asm, list<dag> pattern, bit is_return> {
1700 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1701 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1702 AtomicNoRet<NAME#"_OFFSET", is_return>;
1704 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1706 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1709 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1713 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1714 string asm, list<dag> pattern, bit is_return> {
1716 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1717 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1718 AtomicNoRet<NAME#"_ADDR64", is_return>;
1720 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1721 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1724 // There is no VI version. If the pseudo is selected, it should be lowered
1725 // for VI appropriately.
1728 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1729 ValueType vt, SDPatternOperator atomic> {
1731 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1733 // No return variants
1736 defm _ADDR64 : MUBUFAtomicAddr64_m <
1737 op, name#"_addr64", (outs),
1738 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1739 mbuf_offset:$offset, slc:$slc),
1740 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", [], 0
1743 defm _OFFSET : MUBUFAtomicOffset_m <
1744 op, name#"_offset", (outs),
1745 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1746 SCSrc_32:$soffset, slc:$slc),
1747 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1751 // Variant that return values
1752 let glc = 1, Constraints = "$vdata = $vdata_in",
1753 DisableEncoding = "$vdata_in" in {
1755 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1756 op, name#"_rtn_addr64", (outs rc:$vdata),
1757 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1758 mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
1759 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1761 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1762 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1765 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1766 op, name#"_rtn_offset", (outs rc:$vdata),
1767 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1768 SCSrc_32:$soffset, slc:$slc),
1769 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1771 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1772 i1:$slc), vt:$vdata_in))], 1
1777 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1780 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1781 ValueType load_vt = i32,
1782 SDPatternOperator ld = null_frag> {
1784 let mayLoad = 1, mayStore = 0 in {
1785 let offen = 0, idxen = 0, vaddr = 0 in {
1786 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1787 (ins SReg_128:$srsrc,
1788 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1789 slc:$slc, tfe:$tfe),
1790 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1791 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1792 i32:$soffset, i16:$offset,
1793 i1:$glc, i1:$slc, i1:$tfe)))]>;
1796 let offen = 1, idxen = 0 in {
1797 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1798 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1799 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1801 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1804 let offen = 0, idxen = 1 in {
1805 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1806 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1807 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1808 slc:$slc, tfe:$tfe),
1809 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1812 let offen = 1, idxen = 1 in {
1813 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1814 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1815 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1816 name#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1819 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1820 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1821 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1822 SCSrc_32:$soffset, mbuf_offset:$offset),
1823 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1824 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1825 i64:$vaddr, i32:$soffset,
1831 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1832 ValueType store_vt, SDPatternOperator st> {
1833 let mayLoad = 0, mayStore = 1 in {
1834 defm : MUBUF_m <op, name, (outs),
1835 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1836 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1838 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1839 "$glc"#"$slc"#"$tfe", []>;
1841 let offen = 0, idxen = 0, vaddr = 0 in {
1842 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1843 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1844 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1845 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1846 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1847 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1848 } // offen = 0, idxen = 0, vaddr = 0
1850 let offen = 1, idxen = 0 in {
1851 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1852 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1853 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1854 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1855 "$glc"#"$slc"#"$tfe", []>;
1856 } // end offen = 1, idxen = 0
1858 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1859 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1860 (ins vdataClass:$vdata, SReg_128:$srsrc,
1861 VReg_64:$vaddr, SCSrc_32:$soffset,
1862 mbuf_offset:$offset),
1863 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1864 [(st store_vt:$vdata,
1865 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1866 i32:$soffset, i16:$offset))]>;
1868 } // End mayLoad = 0, mayStore = 1
1871 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1872 FLAT <op, (outs regClass:$data),
1873 (ins VReg_64:$addr),
1874 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1881 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1882 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1883 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1895 class MIMG_Mask <string op, int channels> {
1897 int Channels = channels;
1900 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1901 RegisterClass dst_rc,
1902 RegisterClass src_rc> : MIMG <
1904 (outs dst_rc:$vdata),
1905 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1906 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1908 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1909 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1914 let hasPostISelHook = 1;
1917 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1918 RegisterClass dst_rc,
1920 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1921 MIMG_Mask<asm#"_V1", channels>;
1922 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1923 MIMG_Mask<asm#"_V2", channels>;
1924 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1925 MIMG_Mask<asm#"_V4", channels>;
1928 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1929 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1930 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1931 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1932 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1935 class MIMG_Sampler_Helper <bits<7> op, string asm,
1936 RegisterClass dst_rc,
1937 RegisterClass src_rc, int wqm> : MIMG <
1939 (outs dst_rc:$vdata),
1940 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1941 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1942 SReg_256:$srsrc, SReg_128:$ssamp),
1943 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1944 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1948 let hasPostISelHook = 1;
1952 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1953 RegisterClass dst_rc,
1954 int channels, int wqm> {
1955 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
1956 MIMG_Mask<asm#"_V1", channels>;
1957 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
1958 MIMG_Mask<asm#"_V2", channels>;
1959 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
1960 MIMG_Mask<asm#"_V4", channels>;
1961 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
1962 MIMG_Mask<asm#"_V8", channels>;
1963 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
1964 MIMG_Mask<asm#"_V16", channels>;
1967 multiclass MIMG_Sampler <bits<7> op, string asm> {
1968 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
1969 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
1970 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
1971 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
1974 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
1975 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
1976 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
1977 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
1978 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
1981 class MIMG_Gather_Helper <bits<7> op, string asm,
1982 RegisterClass dst_rc,
1983 RegisterClass src_rc, int wqm> : MIMG <
1985 (outs dst_rc:$vdata),
1986 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1987 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1988 SReg_256:$srsrc, SReg_128:$ssamp),
1989 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1990 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1995 // DMASK was repurposed for GATHER4. 4 components are always
1996 // returned and DMASK works like a swizzle - it selects
1997 // the component to fetch. The only useful DMASK values are
1998 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1999 // (red,red,red,red) etc.) The ISA document doesn't mention
2001 // Therefore, disable all code which updates DMASK by setting these two:
2003 let hasPostISelHook = 0;
2007 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2008 RegisterClass dst_rc,
2009 int channels, int wqm> {
2010 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2011 MIMG_Mask<asm#"_V1", channels>;
2012 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2013 MIMG_Mask<asm#"_V2", channels>;
2014 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2015 MIMG_Mask<asm#"_V4", channels>;
2016 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2017 MIMG_Mask<asm#"_V8", channels>;
2018 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2019 MIMG_Mask<asm#"_V16", channels>;
2022 multiclass MIMG_Gather <bits<7> op, string asm> {
2023 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2024 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2025 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2026 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2029 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2030 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2031 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2032 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2033 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2036 //===----------------------------------------------------------------------===//
2037 // Vector instruction mappings
2038 //===----------------------------------------------------------------------===//
2040 // Maps an opcode in e32 form to its e64 equivalent
2041 def getVOPe64 : InstrMapping {
2042 let FilterClass = "VOP";
2043 let RowFields = ["OpName"];
2044 let ColFields = ["Size"];
2046 let ValueCols = [["8"]];
2049 // Maps an opcode in e64 form to its e32 equivalent
2050 def getVOPe32 : InstrMapping {
2051 let FilterClass = "VOP";
2052 let RowFields = ["OpName"];
2053 let ColFields = ["Size"];
2055 let ValueCols = [["4"]];
2058 // Maps an original opcode to its commuted version
2059 def getCommuteRev : InstrMapping {
2060 let FilterClass = "VOP2_REV";
2061 let RowFields = ["RevOp"];
2062 let ColFields = ["IsOrig"];
2064 let ValueCols = [["0"]];
2067 def getMaskedMIMGOp : InstrMapping {
2068 let FilterClass = "MIMG_Mask";
2069 let RowFields = ["Op"];
2070 let ColFields = ["Channels"];
2072 let ValueCols = [["1"], ["2"], ["3"] ];
2075 // Maps an commuted opcode to its original version
2076 def getCommuteOrig : InstrMapping {
2077 let FilterClass = "VOP2_REV";
2078 let RowFields = ["RevOp"];
2079 let ColFields = ["IsOrig"];
2081 let ValueCols = [["1"]];
2084 def getMCOpcodeGen : InstrMapping {
2085 let FilterClass = "SIMCInstr";
2086 let RowFields = ["PseudoInstr"];
2087 let ColFields = ["Subtarget"];
2088 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2089 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2092 def getAddr64Inst : InstrMapping {
2093 let FilterClass = "MUBUFAddr64Table";
2094 let RowFields = ["OpName"];
2095 let ColFields = ["IsAddr64"];
2097 let ValueCols = [["1"]];
2100 // Maps an atomic opcode to its version with a return value.
2101 def getAtomicRetOp : InstrMapping {
2102 let FilterClass = "AtomicNoRet";
2103 let RowFields = ["NoRetOp"];
2104 let ColFields = ["IsRet"];
2106 let ValueCols = [["1"]];
2109 // Maps an atomic opcode to its returnless version.
2110 def getAtomicNoRetOp : InstrMapping {
2111 let FilterClass = "AtomicNoRet";
2112 let RowFields = ["NoRetOp"];
2113 let ColFields = ["IsRet"];
2115 let ValueCols = [["0"]];
2118 include "SIInstructions.td"
2119 include "CIInstructions.td"
2120 include "VIInstructions.td"