1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1, isCodeGenOnly = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
383 let isCodeGenOnly = 1;
386 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
387 SOP1 <outs, ins, asm, []>,
389 SIMCInstr<opName, SISubtarget.SI>;
391 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
392 SOP1 <outs, ins, asm, []>,
394 SIMCInstr<opName, SISubtarget.VI>;
396 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
399 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
401 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
403 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
407 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
408 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
409 opName#" $dst, $src0", pattern
412 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
413 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
414 opName#" $dst, $src0", pattern
417 // no input, 64-bit output.
418 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
419 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
421 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
426 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
432 // 64-bit input, no output
433 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
434 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
436 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
441 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
447 // 64-bit input, 32-bit output.
448 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
449 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
450 opName#" $dst, $src0", pattern
453 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
454 SOP2<outs, ins, "", pattern>,
455 SIMCInstr<opName, SISubtarget.NONE> {
457 let isCodeGenOnly = 1;
460 // Pseudo instructions have no encodings, but adding this field here allows
462 // let sdst = xxx in {
463 // for multiclasses that include both real and pseudo instructions.
464 field bits<7> sdst = 0;
467 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
468 SOP2<outs, ins, asm, []>,
470 SIMCInstr<opName, SISubtarget.SI>;
472 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
473 SOP2<outs, ins, asm, []>,
475 SIMCInstr<opName, SISubtarget.VI>;
477 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
478 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
479 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
481 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
482 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
483 opName#" $dst, $src0, $src1 [$scc]">;
485 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
486 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
487 opName#" $dst, $src0, $src1 [$scc]">;
490 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
493 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
495 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
497 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
501 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
502 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
503 opName#" $dst, $src0, $src1", pattern
506 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
507 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
508 opName#" $dst, $src0, $src1", pattern
511 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
512 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
513 opName#" $dst, $src0, $src1", pattern
516 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
517 string opName, PatLeaf cond> : SOPC <
518 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
519 opName#" $dst, $src0, $src1", []>;
521 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
522 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
524 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
525 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
527 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
528 SOPK <outs, ins, "", pattern>,
529 SIMCInstr<opName, SISubtarget.NONE> {
531 let isCodeGenOnly = 1;
534 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
535 SOPK <outs, ins, asm, []>,
537 SIMCInstr<opName, SISubtarget.SI>;
539 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
540 SOPK <outs, ins, asm, []>,
542 SIMCInstr<opName, SISubtarget.VI>;
544 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
545 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
548 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
549 opName#" $dst, $src0">;
551 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
552 opName#" $dst, $src0">;
555 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
556 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
557 (ins SReg_32:$src0, u16imm:$src1), pattern>;
559 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
560 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
562 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
563 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
566 //===----------------------------------------------------------------------===//
568 //===----------------------------------------------------------------------===//
570 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
571 SMRD <outs, ins, "", pattern>,
572 SIMCInstr<opName, SISubtarget.NONE> {
574 let isCodeGenOnly = 1;
577 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
579 SMRD <outs, ins, asm, []>,
581 SIMCInstr<opName, SISubtarget.SI>;
583 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
585 SMRD <outs, ins, asm, []>,
587 SIMCInstr<opName, SISubtarget.VI>;
589 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
590 string asm, list<dag> pattern> {
592 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
594 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
596 // glc is only applicable to scalar stores, which are not yet
599 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
603 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
604 RegisterClass dstClass> {
606 op, opName#"_IMM", 1, (outs dstClass:$dst),
607 (ins baseClass:$sbase, u32imm:$offset),
608 opName#" $dst, $sbase, $offset", []
611 defm _SGPR : SMRD_m <
612 op, opName#"_SGPR", 0, (outs dstClass:$dst),
613 (ins baseClass:$sbase, SReg_32:$soff),
614 opName#" $dst, $sbase, $soff", []
618 //===----------------------------------------------------------------------===//
619 // Vector ALU classes
620 //===----------------------------------------------------------------------===//
622 // This must always be right before the operand being input modified.
623 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
624 let PrintMethod = "printOperandAndMods";
626 def InputModsNoDefault : Operand <i32> {
627 let PrintMethod = "printOperandAndMods";
630 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
632 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
633 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
637 // Returns the register class to use for the destination of VOP[123C]
638 // instructions for the given VT.
639 class getVALUDstForVT<ValueType VT> {
640 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
641 !if(!eq(VT.Size, 64), VReg_64,
642 SReg_64)); // else VT == i1
645 // Returns the register class to use for source 0 of VOP[12C]
646 // instructions for the given VT.
647 class getVOPSrc0ForVT<ValueType VT> {
648 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
651 // Returns the register class to use for source 1 of VOP[12C] for the
653 class getVOPSrc1ForVT<ValueType VT> {
654 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
657 // Returns the register class to use for sources of VOP3 instructions for the
659 class getVOP3SrcForVT<ValueType VT> {
660 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
663 // Returns 1 if the source arguments have modifiers, 0 if they do not.
664 class hasModifiers<ValueType SrcVT> {
665 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
666 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
669 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
670 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
671 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
672 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
676 // Returns the input arguments for VOP3 instructions for the given SrcVT.
677 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
678 RegisterOperand Src2RC, int NumSrcArgs,
682 !if (!eq(NumSrcArgs, 1),
683 !if (!eq(HasModifiers, 1),
684 // VOP1 with modifiers
685 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
686 ClampMod:$clamp, omod:$omod)
688 // VOP1 without modifiers
691 !if (!eq(NumSrcArgs, 2),
692 !if (!eq(HasModifiers, 1),
693 // VOP 2 with modifiers
694 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
695 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
696 ClampMod:$clamp, omod:$omod)
698 // VOP2 without modifiers
699 (ins Src0RC:$src0, Src1RC:$src1)
701 /* NumSrcArgs == 3 */,
702 !if (!eq(HasModifiers, 1),
703 // VOP3 with modifiers
704 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
705 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
706 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
707 ClampMod:$clamp, omod:$omod)
709 // VOP3 without modifiers
710 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
714 // Returns the assembly string for the inputs and outputs of a VOP[12C]
715 // instruction. This does not add the _e32 suffix, so it can be reused
717 class getAsm32 <int NumSrcArgs> {
718 string src1 = ", $src1";
719 string src2 = ", $src2";
720 string ret = " $dst, $src0"#
721 !if(!eq(NumSrcArgs, 1), "", src1)#
722 !if(!eq(NumSrcArgs, 3), src2, "");
725 // Returns the assembly string for the inputs and outputs of a VOP3
727 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
728 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
729 string src1 = !if(!eq(NumSrcArgs, 1), "",
730 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
731 " $src1_modifiers,"));
732 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
734 !if(!eq(HasModifiers, 0),
735 getAsm32<NumSrcArgs>.ret,
736 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
740 class VOPProfile <list<ValueType> _ArgVT> {
742 field list<ValueType> ArgVT = _ArgVT;
744 field ValueType DstVT = ArgVT[0];
745 field ValueType Src0VT = ArgVT[1];
746 field ValueType Src1VT = ArgVT[2];
747 field ValueType Src2VT = ArgVT[3];
748 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
749 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
750 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
751 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
752 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
753 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
755 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
756 field bit HasModifiers = hasModifiers<Src0VT>.ret;
758 field dag Outs = (outs DstRC:$dst);
760 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
761 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
764 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
765 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
768 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
769 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
770 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
771 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
772 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
773 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
774 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
775 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
776 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
778 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
779 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
780 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
781 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
782 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
783 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
784 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
785 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
786 let Src0RC32 = VCSrc_32;
789 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
790 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
791 let Asm64 = " $dst, $src0_modifiers, $src1";
794 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
795 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
796 let Asm64 = " $dst, $src0_modifiers, $src1";
799 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
800 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
801 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
803 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
804 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
805 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
806 field string Asm = " $dst, $src0, $vsrc1, $src2";
808 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
809 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
810 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
813 class VOP <string opName> {
814 string OpName = opName;
817 class VOP2_REV <string revOp, bit isOrig> {
818 string RevOp = revOp;
822 class AtomicNoRet <string noRetOp, bit isRet> {
823 string NoRetOp = noRetOp;
827 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
828 VOP1Common <outs, ins, "", pattern>,
830 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
832 let isCodeGenOnly = 1;
838 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
840 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
842 def _si : VOP1<op.SI, outs, ins, asm, []>,
843 SIMCInstr <opName#"_e32", SISubtarget.SI>;
844 def _vi : VOP1<op.VI, outs, ins, asm, []>,
845 SIMCInstr <opName#"_e32", SISubtarget.VI>;
848 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
850 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
852 def _si : VOP1<op.SI, outs, ins, asm, []>,
853 SIMCInstr <opName#"_e32", SISubtarget.SI>;
854 // No VI instruction. This class is for SI only.
857 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
858 VOP2Common <outs, ins, "", pattern>,
860 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
862 let isCodeGenOnly = 1;
865 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
866 string opName, string revOp> {
867 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
868 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
870 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
871 SIMCInstr <opName#"_e32", SISubtarget.SI>;
874 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
875 string opName, string revOp> {
876 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
877 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
879 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
880 SIMCInstr <opName#"_e32", SISubtarget.SI>;
881 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
882 SIMCInstr <opName#"_e32", SISubtarget.VI>;
885 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
887 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
888 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
889 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
890 bits<2> omod = !if(HasModifiers, ?, 0);
891 bits<1> clamp = !if(HasModifiers, ?, 0);
892 bits<9> src1 = !if(HasSrc1, ?, 0);
893 bits<9> src2 = !if(HasSrc2, ?, 0);
896 class VOP3DisableModFields <bit HasSrc0Mods,
899 bit HasOutputMods = 0> {
900 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
901 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
902 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
903 bits<2> omod = !if(HasOutputMods, ?, 0);
904 bits<1> clamp = !if(HasOutputMods, ?, 0);
907 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
908 VOP3Common <outs, ins, "", pattern>,
910 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
912 let isCodeGenOnly = 1;
915 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
916 VOP3Common <outs, ins, asm, []>,
918 SIMCInstr<opName#"_e64", SISubtarget.SI>;
920 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
921 VOP3Common <outs, ins, asm, []>,
923 SIMCInstr <opName#"_e64", SISubtarget.VI>;
925 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
926 VOP3Common <outs, ins, asm, []>,
928 SIMCInstr<opName#"_e64", SISubtarget.SI>;
930 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
931 VOP3Common <outs, ins, asm, []>,
933 SIMCInstr <opName#"_e64", SISubtarget.VI>;
935 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
936 string opName, int NumSrcArgs, bit HasMods = 1> {
938 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
940 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
941 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
942 !if(!eq(NumSrcArgs, 2), 0, 1),
944 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
945 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
946 !if(!eq(NumSrcArgs, 2), 0, 1),
950 // VOP3_m without source modifiers
951 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
952 string opName, int NumSrcArgs, bit HasMods = 1> {
954 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
956 let src0_modifiers = 0,
961 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
962 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
966 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
967 list<dag> pattern, string opName, bit HasMods = 1> {
969 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
971 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
972 VOP3DisableFields<0, 0, HasMods>;
974 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
975 VOP3DisableFields<0, 0, HasMods>;
978 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
979 list<dag> pattern, string opName, bit HasMods = 1> {
981 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
983 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
984 VOP3DisableFields<0, 0, HasMods>;
985 // No VI instruction. This class is for SI only.
988 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
989 list<dag> pattern, string opName, string revOp,
990 bit HasMods = 1, bit UseFullOp = 0> {
992 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
993 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
995 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
996 VOP3DisableFields<1, 0, HasMods>;
998 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
999 VOP3DisableFields<1, 0, HasMods>;
1002 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1003 list<dag> pattern, string opName, string revOp,
1004 bit HasMods = 1, bit UseFullOp = 0> {
1006 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1007 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1009 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1010 VOP3DisableFields<1, 0, HasMods>;
1012 // No VI instruction. This class is for SI only.
1015 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1016 // option of implicit vcc use?
1017 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1018 list<dag> pattern, string opName, string revOp,
1019 bit HasMods = 1, bit UseFullOp = 0> {
1020 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1021 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1023 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1024 // can write it into any SGPR. We currently don't use the carry out,
1025 // so for now hardcode it to VCC as well.
1026 let sdst = SIOperand.VCC, Defs = [VCC] in {
1027 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1028 VOP3DisableFields<1, 0, HasMods>;
1030 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1031 VOP3DisableFields<1, 0, HasMods>;
1032 } // End sdst = SIOperand.VCC, Defs = [VCC]
1035 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1036 list<dag> pattern, string opName, string revOp,
1037 bit HasMods = 1, bit UseFullOp = 0> {
1038 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1041 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1042 VOP3DisableFields<1, 1, HasMods>;
1044 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1045 VOP3DisableFields<1, 1, HasMods>;
1048 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1049 list<dag> pattern, string opName,
1050 bit HasMods, bit defExec> {
1052 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1054 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1055 VOP3DisableFields<1, 0, HasMods> {
1056 let Defs = !if(defExec, [EXEC], []);
1059 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1060 VOP3DisableFields<1, 0, HasMods> {
1061 let Defs = !if(defExec, [EXEC], []);
1065 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1066 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1067 string asm, list<dag> pattern = []> {
1068 let isPseudo = 1, isCodeGenOnly = 1 in {
1069 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1070 SIMCInstr<opName, SISubtarget.NONE>;
1073 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1074 SIMCInstr <opName, SISubtarget.SI>;
1076 def _vi : VOP3Common <outs, ins, asm, []>,
1078 VOP3DisableFields <1, 0, 0>,
1079 SIMCInstr <opName, SISubtarget.VI>;
1082 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1083 dag ins32, string asm32, list<dag> pat32,
1084 dag ins64, string asm64, list<dag> pat64,
1087 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1089 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1092 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1093 SDPatternOperator node = null_frag> : VOP1_Helper <
1095 P.Ins32, P.Asm32, [],
1098 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1099 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1100 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1104 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1105 SDPatternOperator node = null_frag> {
1107 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1109 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1111 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1112 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1113 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1114 opName, P.HasModifiers>;
1117 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1118 dag ins32, string asm32, list<dag> pat32,
1119 dag ins64, string asm64, list<dag> pat64,
1120 string revOp, bit HasMods> {
1121 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1123 defm _e64 : VOP3_2_m <op,
1124 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1128 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1129 SDPatternOperator node = null_frag,
1130 string revOp = opName> : VOP2_Helper <
1132 P.Ins32, P.Asm32, [],
1136 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1137 i1:$clamp, i32:$omod)),
1138 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1139 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1140 revOp, P.HasModifiers
1143 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1144 SDPatternOperator node = null_frag,
1145 string revOp = opName> {
1146 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1148 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1151 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1152 i1:$clamp, i32:$omod)),
1153 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1154 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1155 opName, revOp, P.HasModifiers>;
1158 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1159 dag ins32, string asm32, list<dag> pat32,
1160 dag ins64, string asm64, list<dag> pat64,
1161 string revOp, bit HasMods> {
1163 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1165 defm _e64 : VOP3b_2_m <op,
1166 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1170 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1171 SDPatternOperator node = null_frag,
1172 string revOp = opName> : VOP2b_Helper <
1174 P.Ins32, P.Asm32, [],
1178 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1179 i1:$clamp, i32:$omod)),
1180 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1181 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1182 revOp, P.HasModifiers
1185 // A VOP2 instruction that is VOP3-only on VI.
1186 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1187 dag ins32, string asm32, list<dag> pat32,
1188 dag ins64, string asm64, list<dag> pat64,
1189 string revOp, bit HasMods> {
1190 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1192 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1196 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1197 SDPatternOperator node = null_frag,
1198 string revOp = opName>
1201 P.Ins32, P.Asm32, [],
1205 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1206 i1:$clamp, i32:$omod)),
1207 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1208 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1209 revOp, P.HasModifiers
1212 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1214 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1216 let isCodeGenOnly = 0 in {
1217 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1218 !strconcat(opName, VOP_MADK.Asm), []>,
1219 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1222 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1223 !strconcat(opName, VOP_MADK.Asm), []>,
1224 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1226 } // End isCodeGenOnly = 0
1229 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1230 VOPCCommon <ins, "", pattern>,
1232 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1234 let isCodeGenOnly = 1;
1237 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1238 string opName, bit DefExec> {
1239 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1241 def _si : VOPC<op.SI, ins, asm, []>,
1242 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1243 let Defs = !if(DefExec, [EXEC], []);
1246 def _vi : VOPC<op.VI, ins, asm, []>,
1247 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1248 let Defs = !if(DefExec, [EXEC], []);
1252 multiclass VOPC_Helper <vopc op, string opName,
1253 dag ins32, string asm32, list<dag> pat32,
1254 dag out64, dag ins64, string asm64, list<dag> pat64,
1255 bit HasMods, bit DefExec> {
1256 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1258 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1259 opName, HasMods, DefExec>;
1262 // Special case for class instructions which only have modifiers on
1263 // the 1st source operand.
1264 multiclass VOPC_Class_Helper <vopc op, string opName,
1265 dag ins32, string asm32, list<dag> pat32,
1266 dag out64, dag ins64, string asm64, list<dag> pat64,
1267 bit HasMods, bit DefExec> {
1268 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1270 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1271 opName, HasMods, DefExec>,
1272 VOP3DisableModFields<1, 0, 0>;
1275 multiclass VOPCInst <vopc op, string opName,
1276 VOPProfile P, PatLeaf cond = COND_NULL,
1277 bit DefExec = 0> : VOPC_Helper <
1279 P.Ins32, P.Asm32, [],
1280 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1283 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1284 i1:$clamp, i32:$omod)),
1285 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1287 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1288 P.HasModifiers, DefExec
1291 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1292 bit DefExec = 0> : VOPC_Class_Helper <
1294 P.Ins32, P.Asm32, [],
1295 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1298 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1299 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1300 P.HasModifiers, DefExec
1304 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1305 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1307 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1308 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1310 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1311 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1313 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1314 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1317 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1318 PatLeaf cond = COND_NULL>
1319 : VOPCInst <op, opName, P, cond, 1>;
1321 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1322 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1324 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1325 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1327 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1328 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1330 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1331 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1333 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1334 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1335 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1338 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1339 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1341 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1342 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1344 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1345 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1347 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1348 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1350 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1351 SDPatternOperator node = null_frag> : VOP3_Helper <
1352 op, opName, P.Outs, P.Ins64, P.Asm64,
1353 !if(!eq(P.NumSrcArgs, 3),
1356 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1357 i1:$clamp, i32:$omod)),
1358 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1359 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1360 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1362 !if(!eq(P.NumSrcArgs, 2),
1365 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1366 i1:$clamp, i32:$omod)),
1367 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1368 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1369 /* P.NumSrcArgs == 1 */,
1372 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1373 i1:$clamp, i32:$omod))))],
1374 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1375 P.NumSrcArgs, P.HasModifiers
1378 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1379 // only VOP instruction that implicitly reads VCC.
1380 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1382 SDPatternOperator node = null_frag> : VOP3_Helper <
1385 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1386 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1387 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1390 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1392 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1393 i1:$clamp, i32:$omod)),
1394 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1395 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1400 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1401 string opName, list<dag> pattern> :
1403 op, (outs vrc:$vdst, SReg_64:$sdst),
1404 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1405 InputModsNoDefault:$src1_modifiers, arc:$src1,
1406 InputModsNoDefault:$src2_modifiers, arc:$src2,
1407 ClampMod:$clamp, omod:$omod),
1408 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1409 opName, opName, 1, 1
1412 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1413 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1415 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1416 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1419 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1420 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1421 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1422 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1423 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1424 i32:$src1_modifiers, P.Src1VT:$src1,
1425 i32:$src2_modifiers, P.Src2VT:$src2,
1429 //===----------------------------------------------------------------------===//
1430 // Interpolation opcodes
1431 //===----------------------------------------------------------------------===//
1433 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1434 VINTRPCommon <outs, ins, "", pattern>,
1435 SIMCInstr<opName, SISubtarget.NONE> {
1437 let isCodeGenOnly = 1;
1440 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1442 VINTRPCommon <outs, ins, asm, []>,
1444 SIMCInstr<opName, SISubtarget.SI>;
1446 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1448 VINTRPCommon <outs, ins, asm, []>,
1450 SIMCInstr<opName, SISubtarget.VI>;
1452 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1453 string disableEncoding = "", string constraints = "",
1454 list<dag> pattern = []> {
1455 let DisableEncoding = disableEncoding,
1456 Constraints = constraints in {
1457 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1459 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1461 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1465 //===----------------------------------------------------------------------===//
1466 // Vector I/O classes
1467 //===----------------------------------------------------------------------===//
1469 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1470 DS <outs, ins, "", pattern>,
1471 SIMCInstr <opName, SISubtarget.NONE> {
1473 let isCodeGenOnly = 1;
1476 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1477 DS <outs, ins, asm, []>,
1479 SIMCInstr <opName, SISubtarget.SI>;
1481 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1482 DS <outs, ins, asm, []>,
1484 SIMCInstr <opName, SISubtarget.VI>;
1486 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1487 DS <outs, ins, asm, []>,
1489 SIMCInstr <opName, SISubtarget.SI> {
1491 // Single load interpret the 2 i8imm operands as a single i16 offset.
1493 let offset0 = offset{7-0};
1494 let offset1 = offset{15-8};
1497 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1498 DS <outs, ins, asm, []>,
1500 SIMCInstr <opName, SISubtarget.VI> {
1502 // Single load interpret the 2 i8imm operands as a single i16 offset.
1504 let offset0 = offset{7-0};
1505 let offset1 = offset{15-8};
1508 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1510 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1511 def "" : DS_Pseudo <opName, outs, ins, pat>;
1513 let data0 = 0, data1 = 0 in {
1514 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1515 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1520 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1524 (outs regClass:$vdst),
1525 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1526 asm#" $vdst, $addr"#"$offset"#" [M0]",
1529 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1531 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1532 def "" : DS_Pseudo <opName, outs, ins, pat>;
1534 let data0 = 0, data1 = 0 in {
1535 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1536 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1541 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1545 (outs regClass:$vdst),
1546 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1548 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1551 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1552 string asm, list<dag> pat> {
1553 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1554 def "" : DS_Pseudo <opName, outs, ins, pat>;
1556 let data1 = 0, vdst = 0 in {
1557 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1558 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1563 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1568 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1569 asm#" $addr, $data0"#"$offset"#" [M0]",
1572 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1573 string asm, list<dag> pat> {
1574 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1575 def "" : DS_Pseudo <opName, outs, ins, pat>;
1578 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1579 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1584 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1589 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1590 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1591 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1594 // 1 address, 1 data.
1595 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1596 string asm, list<dag> pat, string noRetOp> {
1597 let mayLoad = 1, mayStore = 1,
1598 hasPostISelHook = 1 // Adjusted to no return version.
1600 def "" : DS_Pseudo <opName, outs, ins, pat>,
1601 AtomicNoRet<noRetOp, 1>;
1604 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1605 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1610 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1611 string noRetOp = ""> : DS_1A1D_RET_m <
1614 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1615 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1617 // 1 address, 2 data.
1618 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1619 string asm, list<dag> pat, string noRetOp> {
1620 let mayLoad = 1, mayStore = 1,
1621 hasPostISelHook = 1 // Adjusted to no return version.
1623 def "" : DS_Pseudo <opName, outs, ins, pat>,
1624 AtomicNoRet<noRetOp, 1>;
1626 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1627 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1631 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1632 string noRetOp = ""> : DS_1A2D_RET_m <
1635 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1636 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1639 // 1 address, 2 data.
1640 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1641 string asm, list<dag> pat, string noRetOp> {
1642 let mayLoad = 1, mayStore = 1 in {
1643 def "" : DS_Pseudo <opName, outs, ins, pat>,
1644 AtomicNoRet<noRetOp, 0>;
1647 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1648 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1653 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1654 string noRetOp = asm> : DS_1A2D_NORET_m <
1657 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1658 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1661 // 1 address, 1 data.
1662 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1663 string asm, list<dag> pat, string noRetOp> {
1664 let mayLoad = 1, mayStore = 1 in {
1665 def "" : DS_Pseudo <opName, outs, ins, pat>,
1666 AtomicNoRet<noRetOp, 0>;
1668 let data1 = 0, vdst = 0 in {
1669 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1670 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1675 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1676 string noRetOp = asm> : DS_1A1D_NORET_m <
1679 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1680 asm#" $addr, $data0"#"$offset"#" [M0]",
1683 //===----------------------------------------------------------------------===//
1685 //===----------------------------------------------------------------------===//
1687 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1688 MTBUF <outs, ins, "", pattern>,
1689 SIMCInstr<opName, SISubtarget.NONE> {
1691 let isCodeGenOnly = 1;
1694 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1696 MTBUF <outs, ins, asm, []>,
1698 SIMCInstr<opName, SISubtarget.SI>;
1700 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1701 MTBUF <outs, ins, asm, []>,
1703 SIMCInstr <opName, SISubtarget.VI>;
1705 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1706 list<dag> pattern> {
1708 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1710 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1712 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1716 let mayStore = 1, mayLoad = 0 in {
1718 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1719 RegisterClass regClass> : MTBUF_m <
1721 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1722 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1723 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1724 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1725 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1728 } // mayStore = 1, mayLoad = 0
1730 let mayLoad = 1, mayStore = 0 in {
1732 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1733 RegisterClass regClass> : MTBUF_m <
1734 op, opName, (outs regClass:$dst),
1735 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1736 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1737 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1738 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1739 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1742 } // mayLoad = 1, mayStore = 0
1744 //===----------------------------------------------------------------------===//
1746 //===----------------------------------------------------------------------===//
1748 class mubuf <bits<7> si, bits<7> vi = si> {
1749 field bits<7> SI = si;
1750 field bits<7> VI = vi;
1753 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1754 bit IsAddr64 = is_addr64;
1755 string OpName = NAME # suffix;
1758 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1759 MUBUF <outs, ins, "", pattern>,
1760 SIMCInstr<opName, SISubtarget.NONE> {
1762 let isCodeGenOnly = 1;
1764 // dummy fields, so that we can use let statements around multiclasses
1774 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1776 MUBUF <outs, ins, asm, []>,
1778 SIMCInstr<opName, SISubtarget.SI> {
1782 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1784 MUBUF <outs, ins, asm, []>,
1786 SIMCInstr<opName, SISubtarget.VI> {
1790 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1791 list<dag> pattern> {
1793 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1794 MUBUFAddr64Table <0>;
1797 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1800 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1803 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1804 dag ins, string asm, list<dag> pattern> {
1806 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1807 MUBUFAddr64Table <1>;
1810 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1813 // There is no VI version. If the pseudo is selected, it should be lowered
1814 // for VI appropriately.
1817 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1818 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1822 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1823 string asm, list<dag> pattern, bit is_return> {
1825 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1826 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1827 AtomicNoRet<NAME#"_OFFSET", is_return>;
1829 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1831 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1834 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1838 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1839 string asm, list<dag> pattern, bit is_return> {
1841 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1842 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1843 AtomicNoRet<NAME#"_ADDR64", is_return>;
1845 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1846 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1849 // There is no VI version. If the pseudo is selected, it should be lowered
1850 // for VI appropriately.
1853 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1854 ValueType vt, SDPatternOperator atomic> {
1856 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1858 // No return variants
1861 defm _ADDR64 : MUBUFAtomicAddr64_m <
1862 op, name#"_addr64", (outs),
1863 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1864 mbuf_offset:$offset, SCSrc_32:$soffset, slc:$slc),
1865 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1868 defm _OFFSET : MUBUFAtomicOffset_m <
1869 op, name#"_offset", (outs),
1870 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1871 SCSrc_32:$soffset, slc:$slc),
1872 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1876 // Variant that return values
1877 let glc = 1, Constraints = "$vdata = $vdata_in",
1878 DisableEncoding = "$vdata_in" in {
1880 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1881 op, name#"_rtn_addr64", (outs rc:$vdata),
1882 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1883 mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
1884 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1886 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1887 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1890 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1891 op, name#"_rtn_offset", (outs rc:$vdata),
1892 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1893 SCSrc_32:$soffset, slc:$slc),
1894 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1896 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1897 i1:$slc), vt:$vdata_in))], 1
1902 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1905 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1906 ValueType load_vt = i32,
1907 SDPatternOperator ld = null_frag> {
1909 let mayLoad = 1, mayStore = 0 in {
1910 let offen = 0, idxen = 0, vaddr = 0 in {
1911 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1912 (ins SReg_128:$srsrc,
1913 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1914 slc:$slc, tfe:$tfe),
1915 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1916 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1917 i32:$soffset, i16:$offset,
1918 i1:$glc, i1:$slc, i1:$tfe)))]>;
1921 let offen = 1, idxen = 0 in {
1922 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1923 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1924 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1926 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1929 let offen = 0, idxen = 1 in {
1930 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1931 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1932 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1933 slc:$slc, tfe:$tfe),
1934 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1937 let offen = 1, idxen = 1 in {
1938 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1939 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1940 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1941 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1944 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1945 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1946 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1947 SCSrc_32:$soffset, mbuf_offset:$offset),
1948 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1949 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1950 i64:$vaddr, i32:$soffset,
1956 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1957 ValueType store_vt, SDPatternOperator st> {
1958 let mayLoad = 0, mayStore = 1 in {
1959 defm : MUBUF_m <op, name, (outs),
1960 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1961 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1963 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1964 "$glc"#"$slc"#"$tfe", []>;
1966 let offen = 0, idxen = 0, vaddr = 0 in {
1967 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1968 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1969 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1970 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1971 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1972 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1973 } // offen = 0, idxen = 0, vaddr = 0
1975 let offen = 1, idxen = 0 in {
1976 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1977 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1978 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1979 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1980 "$glc"#"$slc"#"$tfe", []>;
1981 } // end offen = 1, idxen = 0
1983 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1984 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1985 (ins vdataClass:$vdata, SReg_128:$srsrc,
1986 VReg_64:$vaddr, SCSrc_32:$soffset,
1987 mbuf_offset:$offset),
1988 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1989 [(st store_vt:$vdata,
1990 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1991 i32:$soffset, i16:$offset))]>;
1993 } // End mayLoad = 0, mayStore = 1
1996 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1997 FLAT <op, (outs regClass:$vdst),
1998 (ins VReg_64:$addr),
1999 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2007 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2008 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2009 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2022 class MIMG_Mask <string op, int channels> {
2024 int Channels = channels;
2027 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2028 RegisterClass dst_rc,
2029 RegisterClass src_rc> : MIMG <
2031 (outs dst_rc:$vdata),
2032 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2033 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2035 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2036 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2041 let hasPostISelHook = 1;
2044 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2045 RegisterClass dst_rc,
2047 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2048 MIMG_Mask<asm#"_V1", channels>;
2049 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2050 MIMG_Mask<asm#"_V2", channels>;
2051 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2052 MIMG_Mask<asm#"_V4", channels>;
2055 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2056 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2057 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2058 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2059 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2062 class MIMG_Sampler_Helper <bits<7> op, string asm,
2063 RegisterClass dst_rc,
2064 RegisterClass src_rc, int wqm> : MIMG <
2066 (outs dst_rc:$vdata),
2067 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2068 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2069 SReg_256:$srsrc, SReg_128:$ssamp),
2070 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2071 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2075 let hasPostISelHook = 1;
2079 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2080 RegisterClass dst_rc,
2081 int channels, int wqm> {
2082 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2083 MIMG_Mask<asm#"_V1", channels>;
2084 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2085 MIMG_Mask<asm#"_V2", channels>;
2086 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2087 MIMG_Mask<asm#"_V4", channels>;
2088 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2089 MIMG_Mask<asm#"_V8", channels>;
2090 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2091 MIMG_Mask<asm#"_V16", channels>;
2094 multiclass MIMG_Sampler <bits<7> op, string asm> {
2095 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2096 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2097 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2098 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2101 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2102 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2103 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2104 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2105 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2108 class MIMG_Gather_Helper <bits<7> op, string asm,
2109 RegisterClass dst_rc,
2110 RegisterClass src_rc, int wqm> : MIMG <
2112 (outs dst_rc:$vdata),
2113 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2114 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2115 SReg_256:$srsrc, SReg_128:$ssamp),
2116 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2117 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2122 // DMASK was repurposed for GATHER4. 4 components are always
2123 // returned and DMASK works like a swizzle - it selects
2124 // the component to fetch. The only useful DMASK values are
2125 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2126 // (red,red,red,red) etc.) The ISA document doesn't mention
2128 // Therefore, disable all code which updates DMASK by setting these two:
2130 let hasPostISelHook = 0;
2134 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2135 RegisterClass dst_rc,
2136 int channels, int wqm> {
2137 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2138 MIMG_Mask<asm#"_V1", channels>;
2139 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2140 MIMG_Mask<asm#"_V2", channels>;
2141 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2142 MIMG_Mask<asm#"_V4", channels>;
2143 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2144 MIMG_Mask<asm#"_V8", channels>;
2145 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2146 MIMG_Mask<asm#"_V16", channels>;
2149 multiclass MIMG_Gather <bits<7> op, string asm> {
2150 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2151 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2152 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2153 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2156 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2157 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2158 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2159 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2160 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2163 //===----------------------------------------------------------------------===//
2164 // Vector instruction mappings
2165 //===----------------------------------------------------------------------===//
2167 // Maps an opcode in e32 form to its e64 equivalent
2168 def getVOPe64 : InstrMapping {
2169 let FilterClass = "VOP";
2170 let RowFields = ["OpName"];
2171 let ColFields = ["Size"];
2173 let ValueCols = [["8"]];
2176 // Maps an opcode in e64 form to its e32 equivalent
2177 def getVOPe32 : InstrMapping {
2178 let FilterClass = "VOP";
2179 let RowFields = ["OpName"];
2180 let ColFields = ["Size"];
2182 let ValueCols = [["4"]];
2185 // Maps an original opcode to its commuted version
2186 def getCommuteRev : InstrMapping {
2187 let FilterClass = "VOP2_REV";
2188 let RowFields = ["RevOp"];
2189 let ColFields = ["IsOrig"];
2191 let ValueCols = [["0"]];
2194 def getMaskedMIMGOp : InstrMapping {
2195 let FilterClass = "MIMG_Mask";
2196 let RowFields = ["Op"];
2197 let ColFields = ["Channels"];
2199 let ValueCols = [["1"], ["2"], ["3"] ];
2202 // Maps an commuted opcode to its original version
2203 def getCommuteOrig : InstrMapping {
2204 let FilterClass = "VOP2_REV";
2205 let RowFields = ["RevOp"];
2206 let ColFields = ["IsOrig"];
2208 let ValueCols = [["1"]];
2211 def getMCOpcodeGen : InstrMapping {
2212 let FilterClass = "SIMCInstr";
2213 let RowFields = ["PseudoInstr"];
2214 let ColFields = ["Subtarget"];
2215 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2216 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2219 def getAddr64Inst : InstrMapping {
2220 let FilterClass = "MUBUFAddr64Table";
2221 let RowFields = ["OpName"];
2222 let ColFields = ["IsAddr64"];
2224 let ValueCols = [["1"]];
2227 // Maps an atomic opcode to its version with a return value.
2228 def getAtomicRetOp : InstrMapping {
2229 let FilterClass = "AtomicNoRet";
2230 let RowFields = ["NoRetOp"];
2231 let ColFields = ["IsRet"];
2233 let ValueCols = [["1"]];
2236 // Maps an atomic opcode to its returnless version.
2237 def getAtomicNoRetOp : InstrMapping {
2238 let FilterClass = "AtomicNoRet";
2239 let RowFields = ["NoRetOp"];
2240 let ColFields = ["IsRet"];
2242 let ValueCols = [["0"]];
2245 include "SIInstructions.td"
2246 include "CIInstructions.td"
2247 include "VIInstructions.td"