1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1, isCodeGenOnly = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
383 let isCodeGenOnly = 1;
386 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
387 SOP1 <outs, ins, asm, []>,
389 SIMCInstr<opName, SISubtarget.SI>;
391 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
392 SOP1 <outs, ins, asm, []>,
394 SIMCInstr<opName, SISubtarget.VI>;
396 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
399 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
401 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
403 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
407 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
408 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
409 opName#" $dst, $src0", pattern
412 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
413 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
414 opName#" $dst, $src0", pattern
417 // no input, 64-bit output.
418 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
419 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
421 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
426 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
432 // 64-bit input, no output
433 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
434 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
436 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
441 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
447 // 64-bit input, 32-bit output.
448 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
449 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
450 opName#" $dst, $src0", pattern
453 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
454 SOP2<outs, ins, "", pattern>,
455 SIMCInstr<opName, SISubtarget.NONE> {
457 let isCodeGenOnly = 1;
460 // Pseudo instructions have no encodings, but adding this field here allows
462 // let sdst = xxx in {
463 // for multiclasses that include both real and pseudo instructions.
464 field bits<7> sdst = 0;
467 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
468 SOP2<outs, ins, asm, []>,
470 SIMCInstr<opName, SISubtarget.SI>;
472 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
473 SOP2<outs, ins, asm, []>,
475 SIMCInstr<opName, SISubtarget.VI>;
477 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
478 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
479 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
481 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
482 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
483 opName#" $dst, $src0, $src1 [$scc]">;
485 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
486 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
487 opName#" $dst, $src0, $src1 [$scc]">;
490 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
493 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
495 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
497 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
501 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
502 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
503 opName#" $dst, $src0, $src1", pattern
506 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
507 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
508 opName#" $dst, $src0, $src1", pattern
511 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
512 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
513 opName#" $dst, $src0, $src1", pattern
516 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
517 string opName, PatLeaf cond> : SOPC <
518 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
519 opName#" $dst, $src0, $src1", []>;
521 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
522 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
524 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
525 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
527 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
528 SOPK <outs, ins, "", pattern>,
529 SIMCInstr<opName, SISubtarget.NONE> {
531 let isCodeGenOnly = 1;
534 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
535 SOPK <outs, ins, asm, []>,
537 SIMCInstr<opName, SISubtarget.SI>;
539 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
540 SOPK <outs, ins, asm, []>,
542 SIMCInstr<opName, SISubtarget.VI>;
544 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
545 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
548 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
549 opName#" $dst, $src0">;
551 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
552 opName#" $dst, $src0">;
555 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
556 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
557 (ins SReg_32:$src0, u16imm:$src1), pattern>;
559 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
560 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
562 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
563 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
566 //===----------------------------------------------------------------------===//
568 //===----------------------------------------------------------------------===//
570 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
571 SMRD <outs, ins, "", pattern>,
572 SIMCInstr<opName, SISubtarget.NONE> {
574 let isCodeGenOnly = 1;
577 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
579 SMRD <outs, ins, asm, []>,
581 SIMCInstr<opName, SISubtarget.SI>;
583 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
585 SMRD <outs, ins, asm, []>,
587 SIMCInstr<opName, SISubtarget.VI>;
589 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
590 string asm, list<dag> pattern> {
592 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
594 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
596 // glc is only applicable to scalar stores, which are not yet
599 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
603 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
604 RegisterClass dstClass> {
606 op, opName#"_IMM", 1, (outs dstClass:$dst),
607 (ins baseClass:$sbase, u32imm:$offset),
608 opName#" $dst, $sbase, $offset", []
611 defm _SGPR : SMRD_m <
612 op, opName#"_SGPR", 0, (outs dstClass:$dst),
613 (ins baseClass:$sbase, SReg_32:$soff),
614 opName#" $dst, $sbase, $soff", []
618 //===----------------------------------------------------------------------===//
619 // Vector ALU classes
620 //===----------------------------------------------------------------------===//
622 // This must always be right before the operand being input modified.
623 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
624 let PrintMethod = "printOperandAndMods";
626 def InputModsNoDefault : Operand <i32> {
627 let PrintMethod = "printOperandAndMods";
630 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
632 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
633 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
637 // Returns the register class to use for the destination of VOP[123C]
638 // instructions for the given VT.
639 class getVALUDstForVT<ValueType VT> {
640 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
641 !if(!eq(VT.Size, 64), VReg_64,
642 SReg_64)); // else VT == i1
645 // Returns the register class to use for source 0 of VOP[12C]
646 // instructions for the given VT.
647 class getVOPSrc0ForVT<ValueType VT> {
648 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
651 // Returns the register class to use for source 1 of VOP[12C] for the
653 class getVOPSrc1ForVT<ValueType VT> {
654 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
657 // Returns the register class to use for sources of VOP3 instructions for the
659 class getVOP3SrcForVT<ValueType VT> {
660 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
663 // Returns 1 if the source arguments have modifiers, 0 if they do not.
664 class hasModifiers<ValueType SrcVT> {
665 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
666 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
669 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
670 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
671 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
672 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
676 // Returns the input arguments for VOP3 instructions for the given SrcVT.
677 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
678 RegisterOperand Src2RC, int NumSrcArgs,
682 !if (!eq(NumSrcArgs, 1),
683 !if (!eq(HasModifiers, 1),
684 // VOP1 with modifiers
685 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
686 ClampMod:$clamp, omod:$omod)
688 // VOP1 without modifiers
691 !if (!eq(NumSrcArgs, 2),
692 !if (!eq(HasModifiers, 1),
693 // VOP 2 with modifiers
694 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
695 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
696 ClampMod:$clamp, omod:$omod)
698 // VOP2 without modifiers
699 (ins Src0RC:$src0, Src1RC:$src1)
701 /* NumSrcArgs == 3 */,
702 !if (!eq(HasModifiers, 1),
703 // VOP3 with modifiers
704 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
705 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
706 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
707 ClampMod:$clamp, omod:$omod)
709 // VOP3 without modifiers
710 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
714 // Returns the assembly string for the inputs and outputs of a VOP[12C]
715 // instruction. This does not add the _e32 suffix, so it can be reused
717 class getAsm32 <int NumSrcArgs> {
718 string src1 = ", $src1";
719 string src2 = ", $src2";
720 string ret = " $dst, $src0"#
721 !if(!eq(NumSrcArgs, 1), "", src1)#
722 !if(!eq(NumSrcArgs, 3), src2, "");
725 // Returns the assembly string for the inputs and outputs of a VOP3
727 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
728 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
729 string src1 = !if(!eq(NumSrcArgs, 1), "",
730 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
731 " $src1_modifiers,"));
732 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
734 !if(!eq(HasModifiers, 0),
735 getAsm32<NumSrcArgs>.ret,
736 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
740 class VOPProfile <list<ValueType> _ArgVT> {
742 field list<ValueType> ArgVT = _ArgVT;
744 field ValueType DstVT = ArgVT[0];
745 field ValueType Src0VT = ArgVT[1];
746 field ValueType Src1VT = ArgVT[2];
747 field ValueType Src2VT = ArgVT[3];
748 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
749 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
750 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
751 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
752 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
753 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
755 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
756 field bit HasModifiers = hasModifiers<Src0VT>.ret;
758 field dag Outs = (outs DstRC:$dst);
760 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
761 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
764 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
765 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
768 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
769 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
770 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
771 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
772 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
773 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
774 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
775 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
776 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
778 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
779 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
780 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
781 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
782 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
783 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
784 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
785 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
786 let Src0RC32 = VCSrc_32;
789 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
790 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
791 let Asm64 = " $dst, $src0_modifiers, $src1";
794 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
795 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
796 let Asm64 = " $dst, $src0_modifiers, $src1";
799 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
800 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
801 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
803 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
804 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
805 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
806 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
809 class VOP <string opName> {
810 string OpName = opName;
813 class VOP2_REV <string revOp, bit isOrig> {
814 string RevOp = revOp;
818 class AtomicNoRet <string noRetOp, bit isRet> {
819 string NoRetOp = noRetOp;
823 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
824 VOP1Common <outs, ins, "", pattern>,
826 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
828 let isCodeGenOnly = 1;
834 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
836 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
838 def _si : VOP1<op.SI, outs, ins, asm, []>,
839 SIMCInstr <opName#"_e32", SISubtarget.SI>;
840 def _vi : VOP1<op.VI, outs, ins, asm, []>,
841 SIMCInstr <opName#"_e32", SISubtarget.VI>;
844 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
846 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
848 def _si : VOP1<op.SI, outs, ins, asm, []>,
849 SIMCInstr <opName#"_e32", SISubtarget.SI>;
850 // No VI instruction. This class is for SI only.
853 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
854 VOP2Common <outs, ins, "", pattern>,
856 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
858 let isCodeGenOnly = 1;
861 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
862 string opName, string revOp> {
863 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
864 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
866 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
867 SIMCInstr <opName#"_e32", SISubtarget.SI>;
870 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
871 string opName, string revOp> {
872 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
873 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
875 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
876 SIMCInstr <opName#"_e32", SISubtarget.SI>;
877 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
878 SIMCInstr <opName#"_e32", SISubtarget.VI>;
881 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
883 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
884 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
885 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
886 bits<2> omod = !if(HasModifiers, ?, 0);
887 bits<1> clamp = !if(HasModifiers, ?, 0);
888 bits<9> src1 = !if(HasSrc1, ?, 0);
889 bits<9> src2 = !if(HasSrc2, ?, 0);
892 class VOP3DisableModFields <bit HasSrc0Mods,
895 bit HasOutputMods = 0> {
896 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
897 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
898 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
899 bits<2> omod = !if(HasOutputMods, ?, 0);
900 bits<1> clamp = !if(HasOutputMods, ?, 0);
903 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
904 VOP3Common <outs, ins, "", pattern>,
906 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
908 let isCodeGenOnly = 1;
911 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
912 VOP3Common <outs, ins, asm, []>,
914 SIMCInstr<opName#"_e64", SISubtarget.SI>;
916 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
917 VOP3Common <outs, ins, asm, []>,
919 SIMCInstr <opName#"_e64", SISubtarget.VI>;
921 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
922 VOP3Common <outs, ins, asm, []>,
924 SIMCInstr<opName#"_e64", SISubtarget.SI>;
926 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
927 VOP3Common <outs, ins, asm, []>,
929 SIMCInstr <opName#"_e64", SISubtarget.VI>;
931 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
932 string opName, int NumSrcArgs, bit HasMods = 1> {
934 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
936 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
937 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
938 !if(!eq(NumSrcArgs, 2), 0, 1),
940 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
941 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
942 !if(!eq(NumSrcArgs, 2), 0, 1),
946 // VOP3_m without source modifiers
947 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
948 string opName, int NumSrcArgs, bit HasMods = 1> {
950 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
952 let src0_modifiers = 0,
957 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
958 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
962 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
963 list<dag> pattern, string opName, bit HasMods = 1> {
965 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
967 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
968 VOP3DisableFields<0, 0, HasMods>;
970 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
971 VOP3DisableFields<0, 0, HasMods>;
974 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
975 list<dag> pattern, string opName, bit HasMods = 1> {
977 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
979 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
980 VOP3DisableFields<0, 0, HasMods>;
981 // No VI instruction. This class is for SI only.
984 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
985 list<dag> pattern, string opName, string revOp,
986 bit HasMods = 1, bit UseFullOp = 0> {
988 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
989 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
991 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
992 VOP3DisableFields<1, 0, HasMods>;
994 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
995 VOP3DisableFields<1, 0, HasMods>;
998 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
999 list<dag> pattern, string opName, string revOp,
1000 bit HasMods = 1, bit UseFullOp = 0> {
1002 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1003 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1005 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1006 VOP3DisableFields<1, 0, HasMods>;
1008 // No VI instruction. This class is for SI only.
1011 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1012 // option of implicit vcc use?
1013 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1014 list<dag> pattern, string opName, string revOp,
1015 bit HasMods = 1, bit UseFullOp = 0> {
1016 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1017 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1019 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1020 // can write it into any SGPR. We currently don't use the carry out,
1021 // so for now hardcode it to VCC as well.
1022 let sdst = SIOperand.VCC, Defs = [VCC] in {
1023 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1024 VOP3DisableFields<1, 0, HasMods>;
1026 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1027 VOP3DisableFields<1, 0, HasMods>;
1028 } // End sdst = SIOperand.VCC, Defs = [VCC]
1031 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1032 list<dag> pattern, string opName, string revOp,
1033 bit HasMods = 1, bit UseFullOp = 0> {
1034 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1037 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1038 VOP3DisableFields<1, 1, HasMods>;
1040 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1041 VOP3DisableFields<1, 1, HasMods>;
1044 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1045 list<dag> pattern, string opName,
1046 bit HasMods, bit defExec> {
1048 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1050 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1051 VOP3DisableFields<1, 0, HasMods> {
1052 let Defs = !if(defExec, [EXEC], []);
1055 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1056 VOP3DisableFields<1, 0, HasMods> {
1057 let Defs = !if(defExec, [EXEC], []);
1061 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1062 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1063 string asm, list<dag> pattern = []> {
1064 let isPseudo = 1, isCodeGenOnly = 1 in {
1065 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1066 SIMCInstr<opName, SISubtarget.NONE>;
1069 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1070 SIMCInstr <opName, SISubtarget.SI>;
1072 def _vi : VOP3Common <outs, ins, asm, []>,
1074 VOP3DisableFields <1, 0, 0>,
1075 SIMCInstr <opName, SISubtarget.VI>;
1078 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1079 dag ins32, string asm32, list<dag> pat32,
1080 dag ins64, string asm64, list<dag> pat64,
1083 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1085 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1088 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1089 SDPatternOperator node = null_frag> : VOP1_Helper <
1091 P.Ins32, P.Asm32, [],
1094 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1095 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1096 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1100 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1101 SDPatternOperator node = null_frag> {
1103 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1105 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1107 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1108 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1109 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1110 opName, P.HasModifiers>;
1113 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1114 dag ins32, string asm32, list<dag> pat32,
1115 dag ins64, string asm64, list<dag> pat64,
1116 string revOp, bit HasMods> {
1117 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1119 defm _e64 : VOP3_2_m <op,
1120 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1124 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1125 SDPatternOperator node = null_frag,
1126 string revOp = opName> : VOP2_Helper <
1128 P.Ins32, P.Asm32, [],
1132 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1133 i1:$clamp, i32:$omod)),
1134 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1135 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1136 revOp, P.HasModifiers
1139 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1140 SDPatternOperator node = null_frag,
1141 string revOp = opName> {
1142 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1144 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1147 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1148 i1:$clamp, i32:$omod)),
1149 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1150 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1151 opName, revOp, P.HasModifiers>;
1154 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1155 dag ins32, string asm32, list<dag> pat32,
1156 dag ins64, string asm64, list<dag> pat64,
1157 string revOp, bit HasMods> {
1159 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1161 defm _e64 : VOP3b_2_m <op,
1162 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1166 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1167 SDPatternOperator node = null_frag,
1168 string revOp = opName> : VOP2b_Helper <
1170 P.Ins32, P.Asm32, [],
1174 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1175 i1:$clamp, i32:$omod)),
1176 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1177 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1178 revOp, P.HasModifiers
1181 // A VOP2 instruction that is VOP3-only on VI.
1182 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1183 dag ins32, string asm32, list<dag> pat32,
1184 dag ins64, string asm64, list<dag> pat64,
1185 string revOp, bit HasMods> {
1186 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1188 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1192 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1193 SDPatternOperator node = null_frag,
1194 string revOp = opName>
1197 P.Ins32, P.Asm32, [],
1201 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1202 i1:$clamp, i32:$omod)),
1203 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1204 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1205 revOp, P.HasModifiers
1208 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1209 VOPCCommon <ins, "", pattern>,
1211 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1213 let isCodeGenOnly = 1;
1216 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1217 string opName, bit DefExec> {
1218 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1220 def _si : VOPC<op.SI, ins, asm, []>,
1221 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1222 let Defs = !if(DefExec, [EXEC], []);
1225 def _vi : VOPC<op.VI, ins, asm, []>,
1226 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1227 let Defs = !if(DefExec, [EXEC], []);
1231 multiclass VOPC_Helper <vopc op, string opName,
1232 dag ins32, string asm32, list<dag> pat32,
1233 dag out64, dag ins64, string asm64, list<dag> pat64,
1234 bit HasMods, bit DefExec> {
1235 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1237 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1238 opName, HasMods, DefExec>;
1241 // Special case for class instructions which only have modifiers on
1242 // the 1st source operand.
1243 multiclass VOPC_Class_Helper <vopc op, string opName,
1244 dag ins32, string asm32, list<dag> pat32,
1245 dag out64, dag ins64, string asm64, list<dag> pat64,
1246 bit HasMods, bit DefExec> {
1247 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1249 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1250 opName, HasMods, DefExec>,
1251 VOP3DisableModFields<1, 0, 0>;
1254 multiclass VOPCInst <vopc op, string opName,
1255 VOPProfile P, PatLeaf cond = COND_NULL,
1256 bit DefExec = 0> : VOPC_Helper <
1258 P.Ins32, P.Asm32, [],
1259 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1262 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1263 i1:$clamp, i32:$omod)),
1264 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1266 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1267 P.HasModifiers, DefExec
1270 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1271 bit DefExec = 0> : VOPC_Class_Helper <
1273 P.Ins32, P.Asm32, [],
1274 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1277 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1278 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1279 P.HasModifiers, DefExec
1283 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1284 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1286 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1287 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1289 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1290 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1292 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1293 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1296 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1297 PatLeaf cond = COND_NULL>
1298 : VOPCInst <op, opName, P, cond, 1>;
1300 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1301 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1303 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1304 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1306 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1307 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1309 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1310 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1312 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1313 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1314 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1317 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1318 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1320 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1321 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1323 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1324 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1326 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1327 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1329 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1330 SDPatternOperator node = null_frag> : VOP3_Helper <
1331 op, opName, P.Outs, P.Ins64, P.Asm64,
1332 !if(!eq(P.NumSrcArgs, 3),
1335 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1336 i1:$clamp, i32:$omod)),
1337 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1338 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1339 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1341 !if(!eq(P.NumSrcArgs, 2),
1344 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1345 i1:$clamp, i32:$omod)),
1346 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1347 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1348 /* P.NumSrcArgs == 1 */,
1351 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1352 i1:$clamp, i32:$omod))))],
1353 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1354 P.NumSrcArgs, P.HasModifiers
1357 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1358 // only VOP instruction that implicitly reads VCC.
1359 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1361 SDPatternOperator node = null_frag> : VOP3_Helper <
1364 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1365 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1366 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1369 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1371 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1372 i1:$clamp, i32:$omod)),
1373 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1374 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1379 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1380 string opName, list<dag> pattern> :
1382 op, (outs vrc:$vdst, SReg_64:$sdst),
1383 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1384 InputModsNoDefault:$src1_modifiers, arc:$src1,
1385 InputModsNoDefault:$src2_modifiers, arc:$src2,
1386 ClampMod:$clamp, omod:$omod),
1387 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1388 opName, opName, 1, 1
1391 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1392 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1394 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1395 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1398 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1399 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1400 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1401 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1402 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1403 i32:$src1_modifiers, P.Src1VT:$src1,
1404 i32:$src2_modifiers, P.Src2VT:$src2,
1408 //===----------------------------------------------------------------------===//
1409 // Interpolation opcodes
1410 //===----------------------------------------------------------------------===//
1412 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1413 VINTRPCommon <outs, ins, "", pattern>,
1414 SIMCInstr<opName, SISubtarget.NONE> {
1416 let isCodeGenOnly = 1;
1419 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1421 VINTRPCommon <outs, ins, asm, []>,
1423 SIMCInstr<opName, SISubtarget.SI>;
1425 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1427 VINTRPCommon <outs, ins, asm, []>,
1429 SIMCInstr<opName, SISubtarget.VI>;
1431 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1432 string disableEncoding = "", string constraints = "",
1433 list<dag> pattern = []> {
1434 let DisableEncoding = disableEncoding,
1435 Constraints = constraints in {
1436 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1438 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1440 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1444 //===----------------------------------------------------------------------===//
1445 // Vector I/O classes
1446 //===----------------------------------------------------------------------===//
1448 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1449 DS <outs, ins, "", pattern>,
1450 SIMCInstr <opName, SISubtarget.NONE> {
1452 let isCodeGenOnly = 1;
1455 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1456 DS <outs, ins, asm, []>,
1458 SIMCInstr <opName, SISubtarget.SI>;
1460 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1461 DS <outs, ins, asm, []>,
1463 SIMCInstr <opName, SISubtarget.VI>;
1465 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1466 DS <outs, ins, asm, []>,
1468 SIMCInstr <opName, SISubtarget.SI> {
1470 // Single load interpret the 2 i8imm operands as a single i16 offset.
1472 let offset0 = offset{7-0};
1473 let offset1 = offset{15-8};
1476 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1477 DS <outs, ins, asm, []>,
1479 SIMCInstr <opName, SISubtarget.VI> {
1481 // Single load interpret the 2 i8imm operands as a single i16 offset.
1483 let offset0 = offset{7-0};
1484 let offset1 = offset{15-8};
1487 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1489 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1490 def "" : DS_Pseudo <opName, outs, ins, pat>;
1492 let data0 = 0, data1 = 0 in {
1493 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1494 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1499 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1503 (outs regClass:$vdst),
1504 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1505 asm#" $vdst, $addr"#"$offset"#" [M0]",
1508 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1510 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1511 def "" : DS_Pseudo <opName, outs, ins, pat>;
1513 let data0 = 0, data1 = 0 in {
1514 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1515 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1520 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1524 (outs regClass:$vdst),
1525 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1527 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1530 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1531 string asm, list<dag> pat> {
1532 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1533 def "" : DS_Pseudo <opName, outs, ins, pat>;
1535 let data1 = 0, vdst = 0 in {
1536 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1537 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1542 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1547 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1548 asm#" $addr, $data0"#"$offset"#" [M0]",
1551 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1552 string asm, list<dag> pat> {
1553 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1554 def "" : DS_Pseudo <opName, outs, ins, pat>;
1557 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1558 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1563 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1568 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1569 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1570 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1573 // 1 address, 1 data.
1574 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1575 string asm, list<dag> pat, string noRetOp> {
1576 let mayLoad = 1, mayStore = 1,
1577 hasPostISelHook = 1 // Adjusted to no return version.
1579 def "" : DS_Pseudo <opName, outs, ins, pat>,
1580 AtomicNoRet<noRetOp, 1>;
1583 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1584 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1589 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1590 string noRetOp = ""> : DS_1A1D_RET_m <
1593 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1594 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1596 // 1 address, 2 data.
1597 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1598 string asm, list<dag> pat, string noRetOp> {
1599 let mayLoad = 1, mayStore = 1,
1600 hasPostISelHook = 1 // Adjusted to no return version.
1602 def "" : DS_Pseudo <opName, outs, ins, pat>,
1603 AtomicNoRet<noRetOp, 1>;
1605 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1606 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1610 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1611 string noRetOp = ""> : DS_1A2D_RET_m <
1614 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1615 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1618 // 1 address, 2 data.
1619 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1620 string asm, list<dag> pat, string noRetOp> {
1621 let mayLoad = 1, mayStore = 1 in {
1622 def "" : DS_Pseudo <opName, outs, ins, pat>,
1623 AtomicNoRet<noRetOp, 0>;
1626 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1627 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1632 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1633 string noRetOp = asm> : DS_1A2D_NORET_m <
1636 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1637 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1640 // 1 address, 1 data.
1641 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1642 string asm, list<dag> pat, string noRetOp> {
1643 let mayLoad = 1, mayStore = 1 in {
1644 def "" : DS_Pseudo <opName, outs, ins, pat>,
1645 AtomicNoRet<noRetOp, 0>;
1647 let data1 = 0, vdst = 0 in {
1648 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1649 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1654 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1655 string noRetOp = asm> : DS_1A1D_NORET_m <
1658 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1659 asm#" $addr, $data0"#"$offset"#" [M0]",
1662 //===----------------------------------------------------------------------===//
1664 //===----------------------------------------------------------------------===//
1666 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1667 MTBUF <outs, ins, "", pattern>,
1668 SIMCInstr<opName, SISubtarget.NONE> {
1670 let isCodeGenOnly = 1;
1673 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1675 MTBUF <outs, ins, asm, []>,
1677 SIMCInstr<opName, SISubtarget.SI>;
1679 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1680 MTBUF <outs, ins, asm, []>,
1682 SIMCInstr <opName, SISubtarget.VI>;
1684 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1685 list<dag> pattern> {
1687 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1689 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1691 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1695 let mayStore = 1, mayLoad = 0 in {
1697 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1698 RegisterClass regClass> : MTBUF_m <
1700 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1701 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1702 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1703 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1704 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1707 } // mayStore = 1, mayLoad = 0
1709 let mayLoad = 1, mayStore = 0 in {
1711 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1712 RegisterClass regClass> : MTBUF_m <
1713 op, opName, (outs regClass:$dst),
1714 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1715 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1716 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1717 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1718 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1721 } // mayLoad = 1, mayStore = 0
1723 //===----------------------------------------------------------------------===//
1725 //===----------------------------------------------------------------------===//
1727 class mubuf <bits<7> si, bits<7> vi = si> {
1728 field bits<7> SI = si;
1729 field bits<7> VI = vi;
1732 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1733 bit IsAddr64 = is_addr64;
1734 string OpName = NAME # suffix;
1737 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1738 MUBUF <outs, ins, "", pattern>,
1739 SIMCInstr<opName, SISubtarget.NONE> {
1741 let isCodeGenOnly = 1;
1743 // dummy fields, so that we can use let statements around multiclasses
1753 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1755 MUBUF <outs, ins, asm, []>,
1757 SIMCInstr<opName, SISubtarget.SI> {
1761 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1763 MUBUF <outs, ins, asm, []>,
1765 SIMCInstr<opName, SISubtarget.VI> {
1769 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1770 list<dag> pattern> {
1772 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1773 MUBUFAddr64Table <0>;
1776 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1779 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1782 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1783 dag ins, string asm, list<dag> pattern> {
1785 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1786 MUBUFAddr64Table <1>;
1789 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1792 // There is no VI version. If the pseudo is selected, it should be lowered
1793 // for VI appropriately.
1796 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1797 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1801 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1802 string asm, list<dag> pattern, bit is_return> {
1804 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1805 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1806 AtomicNoRet<NAME#"_OFFSET", is_return>;
1808 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1810 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1813 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1817 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1818 string asm, list<dag> pattern, bit is_return> {
1820 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1821 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1822 AtomicNoRet<NAME#"_ADDR64", is_return>;
1824 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1825 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1828 // There is no VI version. If the pseudo is selected, it should be lowered
1829 // for VI appropriately.
1832 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1833 ValueType vt, SDPatternOperator atomic> {
1835 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1837 // No return variants
1840 defm _ADDR64 : MUBUFAtomicAddr64_m <
1841 op, name#"_addr64", (outs),
1842 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1843 mbuf_offset:$offset, SCSrc_32:$soffset, slc:$slc),
1844 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1847 defm _OFFSET : MUBUFAtomicOffset_m <
1848 op, name#"_offset", (outs),
1849 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1850 SCSrc_32:$soffset, slc:$slc),
1851 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1855 // Variant that return values
1856 let glc = 1, Constraints = "$vdata = $vdata_in",
1857 DisableEncoding = "$vdata_in" in {
1859 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1860 op, name#"_rtn_addr64", (outs rc:$vdata),
1861 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1862 mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
1863 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1865 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1866 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1869 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1870 op, name#"_rtn_offset", (outs rc:$vdata),
1871 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1872 SCSrc_32:$soffset, slc:$slc),
1873 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1875 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1876 i1:$slc), vt:$vdata_in))], 1
1881 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1884 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1885 ValueType load_vt = i32,
1886 SDPatternOperator ld = null_frag> {
1888 let mayLoad = 1, mayStore = 0 in {
1889 let offen = 0, idxen = 0, vaddr = 0 in {
1890 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1891 (ins SReg_128:$srsrc,
1892 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1893 slc:$slc, tfe:$tfe),
1894 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1895 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1896 i32:$soffset, i16:$offset,
1897 i1:$glc, i1:$slc, i1:$tfe)))]>;
1900 let offen = 1, idxen = 0 in {
1901 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1902 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1903 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1905 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1908 let offen = 0, idxen = 1 in {
1909 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1910 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1911 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1912 slc:$slc, tfe:$tfe),
1913 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1916 let offen = 1, idxen = 1 in {
1917 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1918 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1919 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1920 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1923 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1924 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1925 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1926 SCSrc_32:$soffset, mbuf_offset:$offset),
1927 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1928 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1929 i64:$vaddr, i32:$soffset,
1935 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1936 ValueType store_vt, SDPatternOperator st> {
1937 let mayLoad = 0, mayStore = 1 in {
1938 defm : MUBUF_m <op, name, (outs),
1939 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1940 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1942 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1943 "$glc"#"$slc"#"$tfe", []>;
1945 let offen = 0, idxen = 0, vaddr = 0 in {
1946 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1947 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1948 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1949 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1950 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1951 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1952 } // offen = 0, idxen = 0, vaddr = 0
1954 let offen = 1, idxen = 0 in {
1955 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1956 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1957 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1958 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1959 "$glc"#"$slc"#"$tfe", []>;
1960 } // end offen = 1, idxen = 0
1962 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1963 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1964 (ins vdataClass:$vdata, SReg_128:$srsrc,
1965 VReg_64:$vaddr, SCSrc_32:$soffset,
1966 mbuf_offset:$offset),
1967 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1968 [(st store_vt:$vdata,
1969 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1970 i32:$soffset, i16:$offset))]>;
1972 } // End mayLoad = 0, mayStore = 1
1975 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1976 FLAT <op, (outs regClass:$vdst),
1977 (ins VReg_64:$addr),
1978 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
1986 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1987 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1988 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2001 class MIMG_Mask <string op, int channels> {
2003 int Channels = channels;
2006 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2007 RegisterClass dst_rc,
2008 RegisterClass src_rc> : MIMG <
2010 (outs dst_rc:$vdata),
2011 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2012 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2014 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2015 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2020 let hasPostISelHook = 1;
2023 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2024 RegisterClass dst_rc,
2026 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2027 MIMG_Mask<asm#"_V1", channels>;
2028 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2029 MIMG_Mask<asm#"_V2", channels>;
2030 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2031 MIMG_Mask<asm#"_V4", channels>;
2034 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2035 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2036 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2037 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2038 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2041 class MIMG_Sampler_Helper <bits<7> op, string asm,
2042 RegisterClass dst_rc,
2043 RegisterClass src_rc, int wqm> : MIMG <
2045 (outs dst_rc:$vdata),
2046 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2047 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2048 SReg_256:$srsrc, SReg_128:$ssamp),
2049 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2050 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2054 let hasPostISelHook = 1;
2058 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2059 RegisterClass dst_rc,
2060 int channels, int wqm> {
2061 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2062 MIMG_Mask<asm#"_V1", channels>;
2063 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2064 MIMG_Mask<asm#"_V2", channels>;
2065 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2066 MIMG_Mask<asm#"_V4", channels>;
2067 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2068 MIMG_Mask<asm#"_V8", channels>;
2069 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2070 MIMG_Mask<asm#"_V16", channels>;
2073 multiclass MIMG_Sampler <bits<7> op, string asm> {
2074 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2075 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2076 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2077 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2080 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2081 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2082 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2083 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2084 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2087 class MIMG_Gather_Helper <bits<7> op, string asm,
2088 RegisterClass dst_rc,
2089 RegisterClass src_rc, int wqm> : MIMG <
2091 (outs dst_rc:$vdata),
2092 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2093 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2094 SReg_256:$srsrc, SReg_128:$ssamp),
2095 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2096 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2101 // DMASK was repurposed for GATHER4. 4 components are always
2102 // returned and DMASK works like a swizzle - it selects
2103 // the component to fetch. The only useful DMASK values are
2104 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2105 // (red,red,red,red) etc.) The ISA document doesn't mention
2107 // Therefore, disable all code which updates DMASK by setting these two:
2109 let hasPostISelHook = 0;
2113 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2114 RegisterClass dst_rc,
2115 int channels, int wqm> {
2116 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2117 MIMG_Mask<asm#"_V1", channels>;
2118 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2119 MIMG_Mask<asm#"_V2", channels>;
2120 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2121 MIMG_Mask<asm#"_V4", channels>;
2122 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2123 MIMG_Mask<asm#"_V8", channels>;
2124 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2125 MIMG_Mask<asm#"_V16", channels>;
2128 multiclass MIMG_Gather <bits<7> op, string asm> {
2129 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2130 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2131 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2132 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2135 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2136 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2137 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2138 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2139 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2142 //===----------------------------------------------------------------------===//
2143 // Vector instruction mappings
2144 //===----------------------------------------------------------------------===//
2146 // Maps an opcode in e32 form to its e64 equivalent
2147 def getVOPe64 : InstrMapping {
2148 let FilterClass = "VOP";
2149 let RowFields = ["OpName"];
2150 let ColFields = ["Size"];
2152 let ValueCols = [["8"]];
2155 // Maps an opcode in e64 form to its e32 equivalent
2156 def getVOPe32 : InstrMapping {
2157 let FilterClass = "VOP";
2158 let RowFields = ["OpName"];
2159 let ColFields = ["Size"];
2161 let ValueCols = [["4"]];
2164 // Maps an original opcode to its commuted version
2165 def getCommuteRev : InstrMapping {
2166 let FilterClass = "VOP2_REV";
2167 let RowFields = ["RevOp"];
2168 let ColFields = ["IsOrig"];
2170 let ValueCols = [["0"]];
2173 def getMaskedMIMGOp : InstrMapping {
2174 let FilterClass = "MIMG_Mask";
2175 let RowFields = ["Op"];
2176 let ColFields = ["Channels"];
2178 let ValueCols = [["1"], ["2"], ["3"] ];
2181 // Maps an commuted opcode to its original version
2182 def getCommuteOrig : InstrMapping {
2183 let FilterClass = "VOP2_REV";
2184 let RowFields = ["RevOp"];
2185 let ColFields = ["IsOrig"];
2187 let ValueCols = [["1"]];
2190 def getMCOpcodeGen : InstrMapping {
2191 let FilterClass = "SIMCInstr";
2192 let RowFields = ["PseudoInstr"];
2193 let ColFields = ["Subtarget"];
2194 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2195 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2198 def getAddr64Inst : InstrMapping {
2199 let FilterClass = "MUBUFAddr64Table";
2200 let RowFields = ["OpName"];
2201 let ColFields = ["IsAddr64"];
2203 let ValueCols = [["1"]];
2206 // Maps an atomic opcode to its version with a return value.
2207 def getAtomicRetOp : InstrMapping {
2208 let FilterClass = "AtomicNoRet";
2209 let RowFields = ["NoRetOp"];
2210 let ColFields = ["IsRet"];
2212 let ValueCols = [["1"]];
2215 // Maps an atomic opcode to its returnless version.
2216 def getAtomicNoRetOp : InstrMapping {
2217 let FilterClass = "AtomicNoRet";
2218 let RowFields = ["NoRetOp"];
2219 let ColFields = ["IsRet"];
2221 let ValueCols = [["0"]];
2224 include "SIInstructions.td"
2225 include "CIInstructions.td"
2226 include "VIInstructions.td"