1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 } // End OperandType = "OPERAND_IMMEDIATE"
190 //===----------------------------------------------------------------------===//
192 //===----------------------------------------------------------------------===//
194 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
195 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
197 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
198 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
199 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
200 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
202 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
203 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
205 //===----------------------------------------------------------------------===//
206 // SI assembler operands
207 //===----------------------------------------------------------------------===//
227 //===----------------------------------------------------------------------===//
229 // SI Instruction multiclass helpers.
231 // Instructions with _32 take 32-bit operands.
232 // Instructions with _64 take 64-bit operands.
234 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
235 // encoding is the standard encoding, but instruction that make use of
236 // any of the instruction modifiers must use the 64-bit encoding.
238 // Instructions with _e32 use the 32-bit encoding.
239 // Instructions with _e64 use the 64-bit encoding.
241 //===----------------------------------------------------------------------===//
243 //===----------------------------------------------------------------------===//
245 //===----------------------------------------------------------------------===//
247 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
248 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
249 opName#" $dst, $src0", pattern
252 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
253 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
254 opName#" $dst, $src0", pattern
257 // 64-bit input, 32-bit output.
258 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
259 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
260 opName#" $dst, $src0", pattern
263 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
264 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
265 opName#" $dst, $src0, $src1", pattern
268 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
269 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
270 opName#" $dst, $src0, $src1", pattern
273 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
274 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
275 opName#" $dst, $src0, $src1", pattern
279 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
280 string opName, PatLeaf cond> : SOPC <
281 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
282 opName#" $dst, $src0, $src1", []>;
284 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
285 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
287 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
288 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
290 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
291 op, (outs SReg_32:$dst), (ins i16imm:$src0),
292 opName#" $dst, $src0", pattern
295 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
296 op, (outs SReg_64:$dst), (ins i16imm:$src0),
297 opName#" $dst, $src0", pattern
300 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
301 RegisterClass dstClass> {
303 op, 1, (outs dstClass:$dst),
304 (ins baseClass:$sbase, u32imm:$offset),
305 asm#" $dst, $sbase, $offset", []
309 op, 0, (outs dstClass:$dst),
310 (ins baseClass:$sbase, SReg_32:$soff),
311 asm#" $dst, $sbase, $soff", []
315 //===----------------------------------------------------------------------===//
316 // Vector ALU classes
317 //===----------------------------------------------------------------------===//
319 // This must always be right before the operand being input modified.
320 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
321 let PrintMethod = "printOperandAndMods";
323 def InputModsNoDefault : Operand <i32> {
324 let PrintMethod = "printOperandAndMods";
327 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
329 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
330 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
334 // Returns the register class to use for the destination of VOP[123C]
335 // instructions for the given VT.
336 class getVALUDstForVT<ValueType VT> {
337 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
340 // Returns the register class to use for source 0 of VOP[12C]
341 // instructions for the given VT.
342 class getVOPSrc0ForVT<ValueType VT> {
343 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
346 // Returns the register class to use for source 1 of VOP[12C] for the
348 class getVOPSrc1ForVT<ValueType VT> {
349 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
352 // Returns the register classes for the source arguments of a VOP[12C]
353 // instruction for the given SrcVTs.
354 class getInRC32 <list<ValueType> SrcVT> {
355 list<RegisterClass> ret = [
356 getVOPSrc0ForVT<SrcVT[0]>.ret,
357 getVOPSrc1ForVT<SrcVT[1]>.ret
361 // Returns the register class to use for sources of VOP3 instructions for the
363 class getVOP3SrcForVT<ValueType VT> {
364 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
367 // Returns the register classes for the source arguments of a VOP3
368 // instruction for the given SrcVTs.
369 class getInRC64 <list<ValueType> SrcVT> {
370 list<RegisterClass> ret = [
371 getVOP3SrcForVT<SrcVT[0]>.ret,
372 getVOP3SrcForVT<SrcVT[1]>.ret,
373 getVOP3SrcForVT<SrcVT[2]>.ret
377 // Returns 1 if the source arguments have modifiers, 0 if they do not.
378 class hasModifiers<ValueType SrcVT> {
379 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
380 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
383 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
384 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
385 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
386 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
390 // Returns the input arguments for VOP3 instructions for the given SrcVT.
391 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
392 RegisterClass Src2RC, int NumSrcArgs,
396 !if (!eq(NumSrcArgs, 1),
397 !if (!eq(HasModifiers, 1),
398 // VOP1 with modifiers
399 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
400 i32imm:$clamp, i32imm:$omod)
402 // VOP1 without modifiers
405 !if (!eq(NumSrcArgs, 2),
406 !if (!eq(HasModifiers, 1),
407 // VOP 2 with modifiers
408 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
409 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
410 i32imm:$clamp, i32imm:$omod)
412 // VOP2 without modifiers
413 (ins Src0RC:$src0, Src1RC:$src1)
415 /* NumSrcArgs == 3 */,
416 !if (!eq(HasModifiers, 1),
417 // VOP3 with modifiers
418 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
419 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
420 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
421 i32imm:$clamp, i32imm:$omod)
423 // VOP3 without modifiers
424 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
428 // Returns the assembly string for the inputs and outputs of a VOP[12C]
429 // instruction. This does not add the _e32 suffix, so it can be reused
431 class getAsm32 <int NumSrcArgs> {
432 string src1 = ", $src1";
433 string src2 = ", $src2";
434 string ret = " $dst, $src0"#
435 !if(!eq(NumSrcArgs, 1), "", src1)#
436 !if(!eq(NumSrcArgs, 3), src2, "");
439 // Returns the assembly string for the inputs and outputs of a VOP3
441 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
442 string src0 = "$src0_modifiers,";
443 string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
444 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
446 !if(!eq(HasModifiers, 0),
447 getAsm32<NumSrcArgs>.ret,
448 " $dst, "#src0#src1#src2#" $clamp, $omod");
452 class VOPProfile <list<ValueType> _ArgVT> {
454 field list<ValueType> ArgVT = _ArgVT;
456 field ValueType DstVT = ArgVT[0];
457 field ValueType Src0VT = ArgVT[1];
458 field ValueType Src1VT = ArgVT[2];
459 field ValueType Src2VT = ArgVT[3];
460 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
461 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
462 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
463 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
464 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
465 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
467 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
468 field bit HasModifiers = hasModifiers<Src0VT>.ret;
470 field dag Outs = (outs DstRC:$dst);
472 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
473 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
476 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
477 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
480 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
481 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
482 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
483 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
484 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
485 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
486 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
487 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
488 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
490 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
491 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
492 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
493 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
494 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
495 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
496 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
497 let Src0RC32 = VCSrc_32;
499 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
500 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
502 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
503 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
504 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
505 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
508 class VOP <string opName> {
509 string OpName = opName;
512 class VOP2_REV <string revOp, bit isOrig> {
513 string RevOp = revOp;
517 class AtomicNoRet <string noRetOp, bit isRet> {
518 string NoRetOp = noRetOp;
522 class SIMCInstr <string pseudo, int subtarget> {
523 string PseudoInstr = pseudo;
524 int Subtarget = subtarget;
527 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
529 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
530 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
531 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
532 bits<2> omod = !if(HasModifiers, ?, 0);
533 bits<1> clamp = !if(HasModifiers, ?, 0);
534 bits<9> src1 = !if(HasSrc1, ?, 0);
535 bits<9> src2 = !if(HasSrc2, ?, 0);
538 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
539 VOP3Common <outs, ins, "", pattern>,
541 SIMCInstr<opName, SISubtarget.NONE> {
545 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
546 VOP3 <op, outs, ins, asm, []>,
547 SIMCInstr<opName, SISubtarget.SI>;
549 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
550 string opName, int NumSrcArgs, bit HasMods = 1> {
552 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
554 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
555 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
556 !if(!eq(NumSrcArgs, 2), 0, 1),
561 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
562 list<dag> pattern, string opName, bit HasMods = 1> {
564 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
566 def _si : VOP3_Real_si <
567 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
568 outs, ins, asm, opName>,
569 VOP3DisableFields<0, 0, HasMods>;
572 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
573 list<dag> pattern, string opName, string revOp,
574 bit HasMods = 1, bit UseFullOp = 0> {
576 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
577 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
579 def _si : VOP3_Real_si <op,
580 outs, ins, asm, opName>,
581 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
582 VOP3DisableFields<1, 0, HasMods>;
585 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
586 list<dag> pattern, string opName, string revOp,
587 bit HasMods = 1, bit UseFullOp = 0> {
588 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
589 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
591 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
592 // can write it into any SGPR. We currently don't use the carry out,
593 // so for now hardcode it to VCC as well.
594 let sdst = SIOperand.VCC, Defs = [VCC] in {
595 def _si : VOP3b <op, outs, ins, asm, pattern>,
596 VOP3DisableFields<1, 0, HasMods>,
597 SIMCInstr<opName, SISubtarget.SI>,
598 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
599 } // End sdst = SIOperand.VCC, Defs = [VCC]
602 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
603 list<dag> pattern, string opName,
604 bit HasMods, bit defExec> {
606 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
608 def _si : VOP3_Real_si <
609 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
610 outs, ins, asm, opName>,
611 VOP3DisableFields<1, 0, HasMods> {
612 let Defs = !if(defExec, [EXEC], []);
616 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
617 dag ins32, string asm32, list<dag> pat32,
618 dag ins64, string asm64, list<dag> pat64,
621 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
623 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
626 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
627 SDPatternOperator node = null_frag> : VOP1_Helper <
629 P.Ins32, P.Asm32, [],
632 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
633 i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
634 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
638 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
639 list<dag> pattern, string revOp> :
640 VOP2 <op, outs, ins, opName#asm, pattern>,
642 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
644 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
645 dag ins32, string asm32, list<dag> pat32,
646 dag ins64, string asm64, list<dag> pat64,
647 string revOp, bit HasMods> {
648 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
650 defm _e64 : VOP3_2_m <
651 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
652 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
656 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
657 SDPatternOperator node = null_frag,
658 string revOp = opName> : VOP2_Helper <
660 P.Ins32, P.Asm32, [],
664 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
665 i32:$clamp, i32:$omod)),
666 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
667 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
668 revOp, P.HasModifiers
671 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
672 dag ins32, string asm32, list<dag> pat32,
673 dag ins64, string asm64, list<dag> pat64,
674 string revOp, bit HasMods> {
676 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
678 defm _e64 : VOP3b_2_m <
679 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
680 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
684 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
685 SDPatternOperator node = null_frag,
686 string revOp = opName> : VOP2b_Helper <
688 P.Ins32, P.Asm32, [],
692 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
693 i32:$clamp, i32:$omod)),
694 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
695 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
696 revOp, P.HasModifiers
699 multiclass VOPC_Helper <bits<8> op, string opName,
700 dag ins32, string asm32, list<dag> pat32,
701 dag out64, dag ins64, string asm64, list<dag> pat64,
702 bit HasMods, bit DefExec> {
703 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
704 let Defs = !if(DefExec, [EXEC], []);
707 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
711 multiclass VOPCInst <bits<8> op, string opName,
712 VOPProfile P, PatLeaf cond = COND_NULL,
713 bit DefExec = 0> : VOPC_Helper <
715 P.Ins32, P.Asm32, [],
716 (outs SReg_64:$dst), P.Ins64, P.Asm64,
719 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
720 i32:$clamp, i32:$omod)),
721 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
723 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
724 P.HasModifiers, DefExec
727 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
728 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
730 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
731 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
733 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
734 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
736 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
737 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
740 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
741 PatLeaf cond = COND_NULL>
742 : VOPCInst <op, opName, P, cond, 1>;
744 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
745 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
747 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
748 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
750 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
751 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
753 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
754 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
756 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
757 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
758 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
761 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
762 SDPatternOperator node = null_frag> : VOP3_Helper <
763 op, opName, P.Outs, P.Ins64, P.Asm64,
764 !if(!eq(P.NumSrcArgs, 3),
767 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
768 i32:$clamp, i32:$omod)),
769 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
770 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
771 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
773 !if(!eq(P.NumSrcArgs, 2),
776 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
777 i32:$clamp, i32:$omod)),
778 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
779 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
780 /* P.NumSrcArgs == 1 */,
783 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
784 i32:$clamp, i32:$omod))))],
785 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
786 P.NumSrcArgs, P.HasModifiers
789 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
790 string opName, list<dag> pattern> :
792 op, (outs vrc:$dst0, SReg_64:$dst1),
793 (ins arc:$src0, arc:$src1, arc:$src2,
794 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
795 opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern,
799 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
800 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
802 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
803 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
806 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
807 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i32:$clamp, i32:$omod)),
808 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
809 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
810 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
811 i32:$src1_modifiers, P.Src1VT:$src1,
812 i32:$src2_modifiers, P.Src2VT:$src2,
816 //===----------------------------------------------------------------------===//
817 // Vector I/O classes
818 //===----------------------------------------------------------------------===//
820 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
821 DS <op, outs, ins, asm, pat> {
824 // Single load interpret the 2 i8imm operands as a single i16 offset.
825 let offset0 = offset{7-0};
826 let offset1 = offset{15-8};
829 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
831 (outs regClass:$vdst),
832 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
833 asm#" $vdst, $addr, $offset, [M0]",
841 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
843 (outs regClass:$vdst),
844 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
845 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
853 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
856 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
857 asm#" $addr, $data0, $offset [M0]",
865 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
868 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
869 u8imm:$offset0, u8imm:$offset1),
870 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
877 // 1 address, 1 data.
878 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
881 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
882 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
883 AtomicNoRet<noRetOp, 1> {
889 let hasPostISelHook = 1; // Adjusted to no return version.
892 // 1 address, 2 data.
893 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
896 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
897 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
899 AtomicNoRet<noRetOp, 1> {
903 let hasPostISelHook = 1; // Adjusted to no return version.
906 // 1 address, 2 data.
907 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
910 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
911 asm#" $addr, $data0, $data1, $offset, [M0]",
913 AtomicNoRet<noRetOp, 0> {
918 // 1 address, 1 data.
919 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
922 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
923 asm#" $addr, $data0, $offset, [M0]",
925 AtomicNoRet<noRetOp, 0> {
932 class MUBUFAddr64Table <bit is_addr64> {
934 bit IsAddr64 = is_addr64;
937 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
940 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
941 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
942 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
943 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
944 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
950 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
951 ValueType load_vt = i32,
952 SDPatternOperator ld = null_frag> {
954 let lds = 0, mayLoad = 1 in {
958 let offen = 0, idxen = 0, vaddr = 0 in {
959 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
960 (ins SReg_128:$srsrc,
961 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
963 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
964 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
965 i32:$soffset, i16:$offset,
966 i1:$glc, i1:$slc, i1:$tfe)))]>,
970 let offen = 1, idxen = 0 in {
971 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
972 (ins SReg_128:$srsrc, VReg_32:$vaddr,
973 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
975 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
978 let offen = 0, idxen = 1 in {
979 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
980 (ins SReg_128:$srsrc, VReg_32:$vaddr,
981 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
983 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
986 let offen = 1, idxen = 1 in {
987 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
988 (ins SReg_128:$srsrc, VReg_64:$vaddr,
989 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
990 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
994 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
995 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
996 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
997 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
998 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
999 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1004 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1005 ValueType store_vt, SDPatternOperator st> {
1007 let addr64 = 0, lds = 0 in {
1011 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1012 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1014 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1015 "$glc"#"$slc"#"$tfe",
1019 let offen = 0, idxen = 0, vaddr = 0 in {
1020 def _OFFSET : MUBUF <
1022 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1023 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1024 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1025 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1026 i16:$offset, i1:$glc, i1:$slc,
1028 >, MUBUFAddr64Table<0>;
1029 } // offen = 0, idxen = 0, vaddr = 0
1031 let offen = 1, idxen = 0 in {
1032 def _OFFEN : MUBUF <
1034 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1035 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1036 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1037 "$glc"#"$slc"#"$tfe",
1040 } // end offen = 1, idxen = 0
1042 } // End addr64 = 0, lds = 0
1044 def _ADDR64 : MUBUF <
1046 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1047 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1048 [(st store_vt:$vdata,
1049 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1063 let soffset = 128; // ZERO
1067 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1068 FLAT <op, (outs regClass:$data),
1069 (ins VReg_64:$addr),
1070 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1077 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1078 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1079 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1091 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
1093 (outs regClass:$dst),
1094 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1095 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1096 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1097 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1098 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
1104 class MIMG_Mask <string op, int channels> {
1106 int Channels = channels;
1109 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1110 RegisterClass dst_rc,
1111 RegisterClass src_rc> : MIMG <
1113 (outs dst_rc:$vdata),
1114 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1115 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1117 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1118 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1123 let hasPostISelHook = 1;
1126 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1127 RegisterClass dst_rc,
1129 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1130 MIMG_Mask<asm#"_V1", channels>;
1131 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1132 MIMG_Mask<asm#"_V2", channels>;
1133 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1134 MIMG_Mask<asm#"_V4", channels>;
1137 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1138 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1139 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1140 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1141 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1144 class MIMG_Sampler_Helper <bits<7> op, string asm,
1145 RegisterClass dst_rc,
1146 RegisterClass src_rc> : MIMG <
1148 (outs dst_rc:$vdata),
1149 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1150 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1151 SReg_256:$srsrc, SReg_128:$ssamp),
1152 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1153 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1157 let hasPostISelHook = 1;
1160 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1161 RegisterClass dst_rc,
1163 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1164 MIMG_Mask<asm#"_V1", channels>;
1165 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1166 MIMG_Mask<asm#"_V2", channels>;
1167 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1168 MIMG_Mask<asm#"_V4", channels>;
1169 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1170 MIMG_Mask<asm#"_V8", channels>;
1171 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1172 MIMG_Mask<asm#"_V16", channels>;
1175 multiclass MIMG_Sampler <bits<7> op, string asm> {
1176 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1177 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1178 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1179 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1182 class MIMG_Gather_Helper <bits<7> op, string asm,
1183 RegisterClass dst_rc,
1184 RegisterClass src_rc> : MIMG <
1186 (outs dst_rc:$vdata),
1187 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1188 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1189 SReg_256:$srsrc, SReg_128:$ssamp),
1190 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1191 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1196 // DMASK was repurposed for GATHER4. 4 components are always
1197 // returned and DMASK works like a swizzle - it selects
1198 // the component to fetch. The only useful DMASK values are
1199 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1200 // (red,red,red,red) etc.) The ISA document doesn't mention
1202 // Therefore, disable all code which updates DMASK by setting these two:
1204 let hasPostISelHook = 0;
1207 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1208 RegisterClass dst_rc,
1210 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1211 MIMG_Mask<asm#"_V1", channels>;
1212 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1213 MIMG_Mask<asm#"_V2", channels>;
1214 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1215 MIMG_Mask<asm#"_V4", channels>;
1216 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1217 MIMG_Mask<asm#"_V8", channels>;
1218 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1219 MIMG_Mask<asm#"_V16", channels>;
1222 multiclass MIMG_Gather <bits<7> op, string asm> {
1223 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1224 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1225 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1226 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1229 //===----------------------------------------------------------------------===//
1230 // Vector instruction mappings
1231 //===----------------------------------------------------------------------===//
1233 // Maps an opcode in e32 form to its e64 equivalent
1234 def getVOPe64 : InstrMapping {
1235 let FilterClass = "VOP";
1236 let RowFields = ["OpName"];
1237 let ColFields = ["Size"];
1239 let ValueCols = [["8"]];
1242 // Maps an opcode in e64 form to its e32 equivalent
1243 def getVOPe32 : InstrMapping {
1244 let FilterClass = "VOP";
1245 let RowFields = ["OpName"];
1246 let ColFields = ["Size"];
1248 let ValueCols = [["4"]];
1251 // Maps an original opcode to its commuted version
1252 def getCommuteRev : InstrMapping {
1253 let FilterClass = "VOP2_REV";
1254 let RowFields = ["RevOp"];
1255 let ColFields = ["IsOrig"];
1257 let ValueCols = [["0"]];
1260 def getMaskedMIMGOp : InstrMapping {
1261 let FilterClass = "MIMG_Mask";
1262 let RowFields = ["Op"];
1263 let ColFields = ["Channels"];
1265 let ValueCols = [["1"], ["2"], ["3"] ];
1268 // Maps an commuted opcode to its original version
1269 def getCommuteOrig : InstrMapping {
1270 let FilterClass = "VOP2_REV";
1271 let RowFields = ["RevOp"];
1272 let ColFields = ["IsOrig"];
1274 let ValueCols = [["1"]];
1277 def isDS : InstrMapping {
1278 let FilterClass = "DS";
1279 let RowFields = ["Inst"];
1280 let ColFields = ["Size"];
1282 let ValueCols = [["8"]];
1285 def getMCOpcode : InstrMapping {
1286 let FilterClass = "SIMCInstr";
1287 let RowFields = ["PseudoInstr"];
1288 let ColFields = ["Subtarget"];
1289 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1290 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1293 def getAddr64Inst : InstrMapping {
1294 let FilterClass = "MUBUFAddr64Table";
1295 let RowFields = ["NAME"];
1296 let ColFields = ["IsAddr64"];
1298 let ValueCols = [["1"]];
1301 // Maps an atomic opcode to its version with a return value.
1302 def getAtomicRetOp : InstrMapping {
1303 let FilterClass = "AtomicNoRet";
1304 let RowFields = ["NoRetOp"];
1305 let ColFields = ["IsRet"];
1307 let ValueCols = [["1"]];
1310 // Maps an atomic opcode to its returnless version.
1311 def getAtomicNoRetOp : InstrMapping {
1312 let FilterClass = "AtomicNoRet";
1313 let RowFields = ["NoRetOp"];
1314 let ColFields = ["IsRet"];
1316 let ValueCols = [["0"]];
1319 include "SIInstructions.td"