1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
14 class vopc <bits<8> si> : vop {
15 field bits<8> SI = si;
17 field bits<9> SI3 = {0, si{7-0}};
20 class vop1 <bits<8> si> : vop {
21 field bits<8> SI = si;
23 field bits<9> SI3 = {1, 1, si{6-0}};
26 class vop2 <bits<6> si> : vop {
27 field bits<6> SI = si;
29 field bits<9> SI3 = {1, 0, 0, si{5-0}};
32 class vop3 <bits<9> si> : vop {
33 field bits<9> SI3 = si;
36 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
37 // in AMDGPUMCInstLower.h
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
47 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
48 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
49 [SDNPMayLoad, SDNPMemOperand]
52 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
54 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
55 SDTCisVT<1, iAny>, // vdata(VGPR)
56 SDTCisVT<2, i32>, // num_channels(imm)
57 SDTCisVT<3, i32>, // vaddr(VGPR)
58 SDTCisVT<4, i32>, // soffset(SGPR)
59 SDTCisVT<5, i32>, // inst_offset(imm)
60 SDTCisVT<6, i32>, // dfmt(imm)
61 SDTCisVT<7, i32>, // nfmt(imm)
62 SDTCisVT<8, i32>, // offen(imm)
63 SDTCisVT<9, i32>, // idxen(imm)
64 SDTCisVT<10, i32>, // glc(imm)
65 SDTCisVT<11, i32>, // slc(imm)
66 SDTCisVT<12, i32> // tfe(imm)
68 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
71 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
72 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
76 class SDSample<string opcode> : SDNode <opcode,
77 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
78 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
81 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
82 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
83 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
84 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
86 def SIconstdata_ptr : SDNode<
87 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
90 // Transformation function, extract the lower 32bit of a 64bit immediate
91 def LO32 : SDNodeXForm<imm, [{
92 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
95 def LO32f : SDNodeXForm<fpimm, [{
96 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
97 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
100 // Transformation function, extract the upper 32bit of a 64bit immediate
101 def HI32 : SDNodeXForm<imm, [{
102 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
105 def HI32f : SDNodeXForm<fpimm, [{
106 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
107 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
110 def IMM8bitDWORD : PatLeaf <(imm),
111 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
114 def as_dword_i32imm : SDNodeXForm<imm, [{
115 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
118 def as_i1imm : SDNodeXForm<imm, [{
119 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
122 def as_i8imm : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
126 def as_i16imm : SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
130 def as_i32imm: SDNodeXForm<imm, [{
131 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
134 def IMM8bit : PatLeaf <(imm),
135 [{return isUInt<8>(N->getZExtValue());}]
138 def IMM12bit : PatLeaf <(imm),
139 [{return isUInt<12>(N->getZExtValue());}]
142 def IMM16bit : PatLeaf <(imm),
143 [{return isUInt<16>(N->getZExtValue());}]
146 def IMM32bit : PatLeaf <(imm),
147 [{return isUInt<32>(N->getZExtValue());}]
150 def mubuf_vaddr_offset : PatFrag<
151 (ops node:$ptr, node:$offset, node:$imm_offset),
152 (add (add node:$ptr, node:$offset), node:$imm_offset)
155 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
156 return isInlineImmediate(N);
159 class SGPRImm <dag frag> : PatLeaf<frag, [{
160 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
161 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
164 const SIRegisterInfo *SIRI =
165 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
166 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
168 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
175 //===----------------------------------------------------------------------===//
177 //===----------------------------------------------------------------------===//
179 def FRAMEri32 : Operand<iPTR> {
180 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
183 def sopp_brtarget : Operand<OtherVT> {
184 let EncoderMethod = "getSOPPBrEncoding";
185 let OperandType = "OPERAND_PCREL";
188 include "SIInstrFormats.td"
190 let OperandType = "OPERAND_IMMEDIATE" in {
192 def offen : Operand<i1> {
193 let PrintMethod = "printOffen";
195 def idxen : Operand<i1> {
196 let PrintMethod = "printIdxen";
198 def addr64 : Operand<i1> {
199 let PrintMethod = "printAddr64";
201 def mbuf_offset : Operand<i16> {
202 let PrintMethod = "printMBUFOffset";
204 def ds_offset : Operand<i16> {
205 let PrintMethod = "printDSOffset";
207 def ds_offset0 : Operand<i8> {
208 let PrintMethod = "printDSOffset0";
210 def ds_offset1 : Operand<i8> {
211 let PrintMethod = "printDSOffset1";
213 def glc : Operand <i1> {
214 let PrintMethod = "printGLC";
216 def slc : Operand <i1> {
217 let PrintMethod = "printSLC";
219 def tfe : Operand <i1> {
220 let PrintMethod = "printTFE";
223 def omod : Operand <i32> {
224 let PrintMethod = "printOModSI";
227 def ClampMod : Operand <i1> {
228 let PrintMethod = "printClampSI";
231 } // End OperandType = "OPERAND_IMMEDIATE"
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
237 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
238 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
240 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
241 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
242 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
243 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
244 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
245 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
247 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
248 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
250 //===----------------------------------------------------------------------===//
251 // SI assembler operands
252 //===----------------------------------------------------------------------===//
272 //===----------------------------------------------------------------------===//
274 // SI Instruction multiclass helpers.
276 // Instructions with _32 take 32-bit operands.
277 // Instructions with _64 take 64-bit operands.
279 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
280 // encoding is the standard encoding, but instruction that make use of
281 // any of the instruction modifiers must use the 64-bit encoding.
283 // Instructions with _e32 use the 32-bit encoding.
284 // Instructions with _e64 use the 64-bit encoding.
286 //===----------------------------------------------------------------------===//
288 class SIMCInstr <string pseudo, int subtarget> {
289 string PseudoInstr = pseudo;
290 int Subtarget = subtarget;
293 //===----------------------------------------------------------------------===//
295 //===----------------------------------------------------------------------===//
297 class EXPCommon : InstSI<
299 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
300 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
301 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
310 let isPseudo = 1 in {
311 def "" : EXPCommon, SIMCInstr <"EXP", SISubtarget.NONE> ;
314 def _si : EXPCommon, SIMCInstr <"EXP", SISubtarget.SI>, EXPe;
317 //===----------------------------------------------------------------------===//
319 //===----------------------------------------------------------------------===//
321 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
322 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
323 opName#" $dst, $src0", pattern
326 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
327 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
328 opName#" $dst, $src0", pattern
331 // 64-bit input, 32-bit output.
332 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
333 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
334 opName#" $dst, $src0", pattern
337 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
338 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
339 opName#" $dst, $src0, $src1", pattern
342 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
343 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
344 opName#" $dst, $src0, $src1", pattern
347 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
348 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
349 opName#" $dst, $src0, $src1", pattern
353 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
354 string opName, PatLeaf cond> : SOPC <
355 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
356 opName#" $dst, $src0, $src1", []>;
358 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
359 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
361 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
362 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
364 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
365 op, (outs SReg_32:$dst), (ins i16imm:$src0),
366 opName#" $dst, $src0", pattern
369 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
370 op, (outs SReg_64:$dst), (ins i16imm:$src0),
371 opName#" $dst, $src0", pattern
374 //===----------------------------------------------------------------------===//
376 //===----------------------------------------------------------------------===//
378 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
379 SMRD <outs, ins, "", pattern>,
380 SIMCInstr<opName, SISubtarget.NONE> {
384 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
386 SMRD <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
391 string asm, list<dag> pattern> {
393 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
395 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
399 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
400 RegisterClass dstClass> {
402 op, opName#"_IMM", 1, (outs dstClass:$dst),
403 (ins baseClass:$sbase, u32imm:$offset),
404 opName#" $dst, $sbase, $offset", []
407 defm _SGPR : SMRD_m <
408 op, opName#"_SGPR", 0, (outs dstClass:$dst),
409 (ins baseClass:$sbase, SReg_32:$soff),
410 opName#" $dst, $sbase, $soff", []
414 //===----------------------------------------------------------------------===//
415 // Vector ALU classes
416 //===----------------------------------------------------------------------===//
418 // This must always be right before the operand being input modified.
419 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
420 let PrintMethod = "printOperandAndMods";
422 def InputModsNoDefault : Operand <i32> {
423 let PrintMethod = "printOperandAndMods";
426 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
428 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
429 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
433 // Returns the register class to use for the destination of VOP[123C]
434 // instructions for the given VT.
435 class getVALUDstForVT<ValueType VT> {
436 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
439 // Returns the register class to use for source 0 of VOP[12C]
440 // instructions for the given VT.
441 class getVOPSrc0ForVT<ValueType VT> {
442 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
445 // Returns the register class to use for source 1 of VOP[12C] for the
447 class getVOPSrc1ForVT<ValueType VT> {
448 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
451 // Returns the register classes for the source arguments of a VOP[12C]
452 // instruction for the given SrcVTs.
453 class getInRC32 <list<ValueType> SrcVT> {
454 list<RegisterClass> ret = [
455 getVOPSrc0ForVT<SrcVT[0]>.ret,
456 getVOPSrc1ForVT<SrcVT[1]>.ret
460 // Returns the register class to use for sources of VOP3 instructions for the
462 class getVOP3SrcForVT<ValueType VT> {
463 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
466 // Returns the register classes for the source arguments of a VOP3
467 // instruction for the given SrcVTs.
468 class getInRC64 <list<ValueType> SrcVT> {
469 list<RegisterClass> ret = [
470 getVOP3SrcForVT<SrcVT[0]>.ret,
471 getVOP3SrcForVT<SrcVT[1]>.ret,
472 getVOP3SrcForVT<SrcVT[2]>.ret
476 // Returns 1 if the source arguments have modifiers, 0 if they do not.
477 class hasModifiers<ValueType SrcVT> {
478 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
479 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
482 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
483 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
484 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
485 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
489 // Returns the input arguments for VOP3 instructions for the given SrcVT.
490 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
491 RegisterClass Src2RC, int NumSrcArgs,
495 !if (!eq(NumSrcArgs, 1),
496 !if (!eq(HasModifiers, 1),
497 // VOP1 with modifiers
498 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
499 ClampMod:$clamp, omod:$omod)
501 // VOP1 without modifiers
504 !if (!eq(NumSrcArgs, 2),
505 !if (!eq(HasModifiers, 1),
506 // VOP 2 with modifiers
507 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
508 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
509 ClampMod:$clamp, omod:$omod)
511 // VOP2 without modifiers
512 (ins Src0RC:$src0, Src1RC:$src1)
514 /* NumSrcArgs == 3 */,
515 !if (!eq(HasModifiers, 1),
516 // VOP3 with modifiers
517 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
518 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
519 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
520 ClampMod:$clamp, omod:$omod)
522 // VOP3 without modifiers
523 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
527 // Returns the assembly string for the inputs and outputs of a VOP[12C]
528 // instruction. This does not add the _e32 suffix, so it can be reused
530 class getAsm32 <int NumSrcArgs> {
531 string src1 = ", $src1";
532 string src2 = ", $src2";
533 string ret = " $dst, $src0"#
534 !if(!eq(NumSrcArgs, 1), "", src1)#
535 !if(!eq(NumSrcArgs, 3), src2, "");
538 // Returns the assembly string for the inputs and outputs of a VOP3
540 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
541 string src0 = "$src0_modifiers,";
542 string src1 = !if(!eq(NumSrcArgs, 1), "",
543 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
544 " $src1_modifiers,"));
545 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
547 !if(!eq(HasModifiers, 0),
548 getAsm32<NumSrcArgs>.ret,
549 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
553 class VOPProfile <list<ValueType> _ArgVT> {
555 field list<ValueType> ArgVT = _ArgVT;
557 field ValueType DstVT = ArgVT[0];
558 field ValueType Src0VT = ArgVT[1];
559 field ValueType Src1VT = ArgVT[2];
560 field ValueType Src2VT = ArgVT[3];
561 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
562 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
563 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
564 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
565 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
566 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
568 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
569 field bit HasModifiers = hasModifiers<Src0VT>.ret;
571 field dag Outs = (outs DstRC:$dst);
573 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
574 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
577 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
578 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
581 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
582 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
583 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
584 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
585 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
586 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
587 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
588 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
589 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
591 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
592 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
593 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
594 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
595 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
596 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
597 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
598 let Src0RC32 = VCSrc_32;
600 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
601 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
603 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
604 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
605 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
606 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
609 class VOP <string opName> {
610 string OpName = opName;
613 class VOP2_REV <string revOp, bit isOrig> {
614 string RevOp = revOp;
618 class AtomicNoRet <string noRetOp, bit isRet> {
619 string NoRetOp = noRetOp;
623 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
624 VOP1Common <outs, ins, "", pattern>,
625 SIMCInstr<opName, SISubtarget.NONE> {
629 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
631 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
633 def _si : VOP1<op.SI, outs, ins, asm, []>,
634 SIMCInstr <opName, SISubtarget.SI>;
637 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
639 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
640 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
641 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
642 bits<2> omod = !if(HasModifiers, ?, 0);
643 bits<1> clamp = !if(HasModifiers, ?, 0);
644 bits<9> src1 = !if(HasSrc1, ?, 0);
645 bits<9> src2 = !if(HasSrc2, ?, 0);
648 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
649 VOP3Common <outs, ins, "", pattern>,
651 SIMCInstr<opName, SISubtarget.NONE> {
655 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
656 VOP3 <op, outs, ins, asm, []>,
657 SIMCInstr<opName, SISubtarget.SI>;
659 multiclass VOP3_m <vop3 op, dag outs, dag ins, string asm, list<dag> pattern,
660 string opName, int NumSrcArgs, bit HasMods = 1> {
662 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
664 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
665 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
666 !if(!eq(NumSrcArgs, 2), 0, 1),
671 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
672 list<dag> pattern, string opName, bit HasMods = 1> {
674 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
676 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
677 VOP3DisableFields<0, 0, HasMods>;
680 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
681 list<dag> pattern, string opName, string revOp,
682 bit HasMods = 1, bit UseFullOp = 0> {
684 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
685 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
687 def _si : VOP3_Real_si <op.SI3,
688 outs, ins, asm, opName>,
689 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
690 VOP3DisableFields<1, 0, HasMods>;
693 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
694 list<dag> pattern, string opName, string revOp,
695 bit HasMods = 1, bit UseFullOp = 0> {
696 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
697 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
699 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
700 // can write it into any SGPR. We currently don't use the carry out,
701 // so for now hardcode it to VCC as well.
702 let sdst = SIOperand.VCC, Defs = [VCC] in {
703 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
704 VOP3DisableFields<1, 0, HasMods>,
705 SIMCInstr<opName, SISubtarget.SI>,
706 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
707 } // End sdst = SIOperand.VCC, Defs = [VCC]
710 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
711 list<dag> pattern, string opName,
712 bit HasMods, bit defExec> {
714 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
716 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
717 VOP3DisableFields<1, 0, HasMods> {
718 let Defs = !if(defExec, [EXEC], []);
722 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
723 dag ins32, string asm32, list<dag> pat32,
724 dag ins64, string asm64, list<dag> pat64,
727 def _e32 : VOP1 <op.SI, outs, ins32, opName#asm32, pat32>, VOP<opName>;
729 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
732 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
733 SDPatternOperator node = null_frag> : VOP1_Helper <
735 P.Ins32, P.Asm32, [],
738 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
739 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
740 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
744 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
745 list<dag> pattern, string revOp> :
746 VOP2 <op, outs, ins, opName#asm, pattern>,
748 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
750 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
751 dag ins32, string asm32, list<dag> pat32,
752 dag ins64, string asm64, list<dag> pat64,
753 string revOp, bit HasMods> {
754 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
756 defm _e64 : VOP3_2_m <op,
757 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
761 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
762 SDPatternOperator node = null_frag,
763 string revOp = opName> : VOP2_Helper <
765 P.Ins32, P.Asm32, [],
769 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
770 i1:$clamp, i32:$omod)),
771 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
772 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
773 revOp, P.HasModifiers
776 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
777 dag ins32, string asm32, list<dag> pat32,
778 dag ins64, string asm64, list<dag> pat64,
779 string revOp, bit HasMods> {
781 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
783 defm _e64 : VOP3b_2_m <op,
784 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
788 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
789 SDPatternOperator node = null_frag,
790 string revOp = opName> : VOP2b_Helper <
792 P.Ins32, P.Asm32, [],
796 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
797 i1:$clamp, i32:$omod)),
798 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
799 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
800 revOp, P.HasModifiers
803 multiclass VOPC_Helper <vopc op, string opName,
804 dag ins32, string asm32, list<dag> pat32,
805 dag out64, dag ins64, string asm64, list<dag> pat64,
806 bit HasMods, bit DefExec> {
807 def _e32 : VOPC <op.SI, ins32, opName#asm32, pat32>, VOP <opName> {
808 let Defs = !if(DefExec, [EXEC], []);
811 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
815 multiclass VOPCInst <vopc op, string opName,
816 VOPProfile P, PatLeaf cond = COND_NULL,
817 bit DefExec = 0> : VOPC_Helper <
819 P.Ins32, P.Asm32, [],
820 (outs SReg_64:$dst), P.Ins64, P.Asm64,
823 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
824 i1:$clamp, i32:$omod)),
825 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
827 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
828 P.HasModifiers, DefExec
831 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
832 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
834 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
835 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
837 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
838 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
840 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
841 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
844 multiclass VOPCX <vopc op, string opName, VOPProfile P,
845 PatLeaf cond = COND_NULL>
846 : VOPCInst <op, opName, P, cond, 1>;
848 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
849 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
851 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
852 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
854 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
855 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
857 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
858 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
860 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
861 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
862 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
865 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
866 SDPatternOperator node = null_frag> : VOP3_Helper <
867 op, opName, P.Outs, P.Ins64, P.Asm64,
868 !if(!eq(P.NumSrcArgs, 3),
871 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
872 i1:$clamp, i32:$omod)),
873 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
874 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
875 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
877 !if(!eq(P.NumSrcArgs, 2),
880 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
881 i1:$clamp, i32:$omod)),
882 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
883 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
884 /* P.NumSrcArgs == 1 */,
887 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
888 i1:$clamp, i32:$omod))))],
889 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
890 P.NumSrcArgs, P.HasModifiers
893 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterClass arc,
894 string opName, list<dag> pattern> :
896 op, (outs vrc:$dst0, SReg_64:$dst1),
897 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
898 InputModsNoDefault:$src1_modifiers, arc:$src1,
899 InputModsNoDefault:$src2_modifiers, arc:$src2,
900 ClampMod:$clamp, i32imm:$omod),
901 opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
905 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
906 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
908 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
909 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
912 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
913 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
914 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
915 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
916 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
917 i32:$src1_modifiers, P.Src1VT:$src1,
918 i32:$src2_modifiers, P.Src2VT:$src2,
922 //===----------------------------------------------------------------------===//
923 // Vector I/O classes
924 //===----------------------------------------------------------------------===//
926 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
927 DS <op, outs, ins, asm, pat> {
930 // Single load interpret the 2 i8imm operands as a single i16 offset.
931 let offset0 = offset{7-0};
932 let offset1 = offset{15-8};
935 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
937 (outs regClass:$vdst),
938 (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset),
939 asm#" $vdst, $addr"#"$offset"#" [M0]",
947 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
949 (outs regClass:$vdst),
950 (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1),
951 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
959 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
962 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset),
963 asm#" $addr, $data0"#"$offset"#" [M0]",
971 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
974 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
975 ds_offset0:$offset0, ds_offset1:$offset1),
976 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
983 // 1 address, 1 data.
984 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
987 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),
988 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
989 AtomicNoRet<noRetOp, 1> {
995 let hasPostISelHook = 1; // Adjusted to no return version.
998 // 1 address, 2 data.
999 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
1002 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),
1003 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1005 AtomicNoRet<noRetOp, 1> {
1009 let hasPostISelHook = 1; // Adjusted to no return version.
1012 // 1 address, 2 data.
1013 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1016 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),
1017 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1019 AtomicNoRet<noRetOp, 0> {
1024 // 1 address, 1 data.
1025 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1028 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),
1029 asm#" $addr, $data0"#"$offset"#" [M0]",
1031 AtomicNoRet<noRetOp, 0> {
1038 //===----------------------------------------------------------------------===//
1040 //===----------------------------------------------------------------------===//
1042 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1043 MTBUF <outs, ins, "", pattern>,
1044 SIMCInstr<opName, SISubtarget.NONE> {
1048 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1050 MTBUF <outs, ins, asm, []>,
1052 SIMCInstr<opName, SISubtarget.SI>;
1054 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1055 list<dag> pattern> {
1057 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1059 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1063 let mayStore = 1, mayLoad = 0 in {
1065 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1066 RegisterClass regClass> : MTBUF_m <
1068 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1069 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1070 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1071 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1072 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1075 } // mayStore = 1, mayLoad = 0
1077 let mayLoad = 1, mayStore = 0 in {
1079 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1080 RegisterClass regClass> : MTBUF_m <
1081 op, opName, (outs regClass:$dst),
1082 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1083 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1084 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1085 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1086 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1089 } // mayLoad = 1, mayStore = 0
1091 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1093 bit IsAddr64 = is_addr64;
1094 string OpName = NAME # suffix;
1097 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1098 : MUBUF <op, outs, ins, asm, pattern> {
1108 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1109 : MUBUF <op, outs, ins, asm, pattern> {
1119 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1120 ValueType vt, SDPatternOperator atomic> {
1122 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1124 // No return variants
1127 def _ADDR64 : MUBUFAtomicAddr64 <
1129 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1130 mbuf_offset:$offset, slc:$slc),
1131 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1132 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1134 def _OFFSET : MUBUFAtomicOffset <
1136 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1137 SSrc_32:$soffset, slc:$slc),
1138 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1139 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1142 // Variant that return values
1143 let glc = 1, Constraints = "$vdata = $vdata_in",
1144 DisableEncoding = "$vdata_in" in {
1146 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1147 op, (outs rc:$vdata),
1148 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1149 mbuf_offset:$offset, slc:$slc),
1150 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1152 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1153 i1:$slc), vt:$vdata_in))]
1154 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1156 def _RTN_OFFSET : MUBUFAtomicOffset <
1157 op, (outs rc:$vdata),
1158 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1159 SSrc_32:$soffset, slc:$slc),
1160 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1162 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1163 i1:$slc), vt:$vdata_in))]
1164 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1168 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1171 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1172 ValueType load_vt = i32,
1173 SDPatternOperator ld = null_frag> {
1175 let lds = 0, mayLoad = 1 in {
1179 let offen = 0, idxen = 0, vaddr = 0 in {
1180 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1181 (ins SReg_128:$srsrc,
1182 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1183 slc:$slc, tfe:$tfe),
1184 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1185 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1186 i32:$soffset, i16:$offset,
1187 i1:$glc, i1:$slc, i1:$tfe)))]>,
1188 MUBUFAddr64Table<0>;
1191 let offen = 1, idxen = 0 in {
1192 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1193 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1194 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1196 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1199 let offen = 0, idxen = 1 in {
1200 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1201 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1202 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1203 slc:$slc, tfe:$tfe),
1204 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1207 let offen = 1, idxen = 1 in {
1208 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1209 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1210 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1211 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1215 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1216 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1217 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1218 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1219 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1220 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1225 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1226 ValueType store_vt, SDPatternOperator st> {
1228 let addr64 = 0, lds = 0 in {
1232 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1233 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1235 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1236 "$glc"#"$slc"#"$tfe",
1240 let offen = 0, idxen = 0, vaddr = 0 in {
1241 def _OFFSET : MUBUF <
1243 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1244 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1245 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1246 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1247 i16:$offset, i1:$glc, i1:$slc,
1249 >, MUBUFAddr64Table<0>;
1250 } // offen = 0, idxen = 0, vaddr = 0
1252 let offen = 1, idxen = 0 in {
1253 def _OFFEN : MUBUF <
1255 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1256 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1257 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1258 "$glc"#"$slc"#"$tfe",
1261 } // end offen = 1, idxen = 0
1263 } // End addr64 = 0, lds = 0
1265 def _ADDR64 : MUBUF <
1267 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1268 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1269 [(st store_vt:$vdata,
1270 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1284 let soffset = 128; // ZERO
1288 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1289 FLAT <op, (outs regClass:$data),
1290 (ins VReg_64:$addr),
1291 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1298 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1299 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1300 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1312 class MIMG_Mask <string op, int channels> {
1314 int Channels = channels;
1317 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1318 RegisterClass dst_rc,
1319 RegisterClass src_rc> : MIMG <
1321 (outs dst_rc:$vdata),
1322 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1323 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1325 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1326 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1331 let hasPostISelHook = 1;
1334 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1335 RegisterClass dst_rc,
1337 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1338 MIMG_Mask<asm#"_V1", channels>;
1339 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1340 MIMG_Mask<asm#"_V2", channels>;
1341 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1342 MIMG_Mask<asm#"_V4", channels>;
1345 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1346 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1347 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1348 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1349 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1352 class MIMG_Sampler_Helper <bits<7> op, string asm,
1353 RegisterClass dst_rc,
1354 RegisterClass src_rc> : MIMG <
1356 (outs dst_rc:$vdata),
1357 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1358 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1359 SReg_256:$srsrc, SReg_128:$ssamp),
1360 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1361 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1365 let hasPostISelHook = 1;
1368 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1369 RegisterClass dst_rc,
1371 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1372 MIMG_Mask<asm#"_V1", channels>;
1373 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1374 MIMG_Mask<asm#"_V2", channels>;
1375 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1376 MIMG_Mask<asm#"_V4", channels>;
1377 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1378 MIMG_Mask<asm#"_V8", channels>;
1379 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1380 MIMG_Mask<asm#"_V16", channels>;
1383 multiclass MIMG_Sampler <bits<7> op, string asm> {
1384 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1385 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1386 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1387 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1390 class MIMG_Gather_Helper <bits<7> op, string asm,
1391 RegisterClass dst_rc,
1392 RegisterClass src_rc> : MIMG <
1394 (outs dst_rc:$vdata),
1395 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1396 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1397 SReg_256:$srsrc, SReg_128:$ssamp),
1398 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1399 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1404 // DMASK was repurposed for GATHER4. 4 components are always
1405 // returned and DMASK works like a swizzle - it selects
1406 // the component to fetch. The only useful DMASK values are
1407 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1408 // (red,red,red,red) etc.) The ISA document doesn't mention
1410 // Therefore, disable all code which updates DMASK by setting these two:
1412 let hasPostISelHook = 0;
1415 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1416 RegisterClass dst_rc,
1418 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1419 MIMG_Mask<asm#"_V1", channels>;
1420 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1421 MIMG_Mask<asm#"_V2", channels>;
1422 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1423 MIMG_Mask<asm#"_V4", channels>;
1424 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1425 MIMG_Mask<asm#"_V8", channels>;
1426 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1427 MIMG_Mask<asm#"_V16", channels>;
1430 multiclass MIMG_Gather <bits<7> op, string asm> {
1431 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1432 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1433 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1434 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1437 //===----------------------------------------------------------------------===//
1438 // Vector instruction mappings
1439 //===----------------------------------------------------------------------===//
1441 // Maps an opcode in e32 form to its e64 equivalent
1442 def getVOPe64 : InstrMapping {
1443 let FilterClass = "VOP";
1444 let RowFields = ["OpName"];
1445 let ColFields = ["Size"];
1447 let ValueCols = [["8"]];
1450 // Maps an opcode in e64 form to its e32 equivalent
1451 def getVOPe32 : InstrMapping {
1452 let FilterClass = "VOP";
1453 let RowFields = ["OpName"];
1454 let ColFields = ["Size"];
1456 let ValueCols = [["4"]];
1459 // Maps an original opcode to its commuted version
1460 def getCommuteRev : InstrMapping {
1461 let FilterClass = "VOP2_REV";
1462 let RowFields = ["RevOp"];
1463 let ColFields = ["IsOrig"];
1465 let ValueCols = [["0"]];
1468 def getMaskedMIMGOp : InstrMapping {
1469 let FilterClass = "MIMG_Mask";
1470 let RowFields = ["Op"];
1471 let ColFields = ["Channels"];
1473 let ValueCols = [["1"], ["2"], ["3"] ];
1476 // Maps an commuted opcode to its original version
1477 def getCommuteOrig : InstrMapping {
1478 let FilterClass = "VOP2_REV";
1479 let RowFields = ["RevOp"];
1480 let ColFields = ["IsOrig"];
1482 let ValueCols = [["1"]];
1485 def isDS : InstrMapping {
1486 let FilterClass = "DS";
1487 let RowFields = ["Inst"];
1488 let ColFields = ["Size"];
1490 let ValueCols = [["8"]];
1493 def getMCOpcode : InstrMapping {
1494 let FilterClass = "SIMCInstr";
1495 let RowFields = ["PseudoInstr"];
1496 let ColFields = ["Subtarget"];
1497 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1498 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1501 def getAddr64Inst : InstrMapping {
1502 let FilterClass = "MUBUFAddr64Table";
1503 let RowFields = ["OpName"];
1504 let ColFields = ["IsAddr64"];
1506 let ValueCols = [["1"]];
1509 // Maps an atomic opcode to its version with a return value.
1510 def getAtomicRetOp : InstrMapping {
1511 let FilterClass = "AtomicNoRet";
1512 let RowFields = ["NoRetOp"];
1513 let ColFields = ["IsRet"];
1515 let ValueCols = [["1"]];
1518 // Maps an atomic opcode to its returnless version.
1519 def getAtomicNoRetOp : InstrMapping {
1520 let FilterClass = "AtomicNoRet";
1521 let RowFields = ["NoRetOp"];
1522 let ColFields = ["IsRet"];
1524 let ValueCols = [["0"]];
1527 include "SIInstructions.td"