1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 } // End OperandType = "OPERAND_IMMEDIATE"
190 //===----------------------------------------------------------------------===//
192 //===----------------------------------------------------------------------===//
194 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
195 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
197 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
198 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
199 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
200 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
201 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
202 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
204 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
205 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
207 //===----------------------------------------------------------------------===//
208 // SI assembler operands
209 //===----------------------------------------------------------------------===//
229 //===----------------------------------------------------------------------===//
231 // SI Instruction multiclass helpers.
233 // Instructions with _32 take 32-bit operands.
234 // Instructions with _64 take 64-bit operands.
236 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
237 // encoding is the standard encoding, but instruction that make use of
238 // any of the instruction modifiers must use the 64-bit encoding.
240 // Instructions with _e32 use the 32-bit encoding.
241 // Instructions with _e64 use the 64-bit encoding.
243 //===----------------------------------------------------------------------===//
245 //===----------------------------------------------------------------------===//
247 //===----------------------------------------------------------------------===//
249 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
250 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
251 opName#" $dst, $src0", pattern
254 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
255 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
256 opName#" $dst, $src0", pattern
259 // 64-bit input, 32-bit output.
260 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
261 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
262 opName#" $dst, $src0", pattern
265 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
266 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
267 opName#" $dst, $src0, $src1", pattern
270 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
271 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
272 opName#" $dst, $src0, $src1", pattern
275 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
276 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
277 opName#" $dst, $src0, $src1", pattern
281 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
282 string opName, PatLeaf cond> : SOPC <
283 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
284 opName#" $dst, $src0, $src1", []>;
286 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
287 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
289 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
290 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
292 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
293 op, (outs SReg_32:$dst), (ins i16imm:$src0),
294 opName#" $dst, $src0", pattern
297 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
298 op, (outs SReg_64:$dst), (ins i16imm:$src0),
299 opName#" $dst, $src0", pattern
302 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
303 RegisterClass dstClass> {
305 op, 1, (outs dstClass:$dst),
306 (ins baseClass:$sbase, u32imm:$offset),
307 asm#" $dst, $sbase, $offset", []
311 op, 0, (outs dstClass:$dst),
312 (ins baseClass:$sbase, SReg_32:$soff),
313 asm#" $dst, $sbase, $soff", []
317 //===----------------------------------------------------------------------===//
318 // Vector ALU classes
319 //===----------------------------------------------------------------------===//
321 // This must always be right before the operand being input modified.
322 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
323 let PrintMethod = "printOperandAndMods";
325 def InputModsNoDefault : Operand <i32> {
326 let PrintMethod = "printOperandAndMods";
329 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
331 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
332 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
336 // Returns the register class to use for the destination of VOP[123C]
337 // instructions for the given VT.
338 class getVALUDstForVT<ValueType VT> {
339 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
342 // Returns the register class to use for source 0 of VOP[12C]
343 // instructions for the given VT.
344 class getVOPSrc0ForVT<ValueType VT> {
345 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
348 // Returns the register class to use for source 1 of VOP[12C] for the
350 class getVOPSrc1ForVT<ValueType VT> {
351 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
354 // Returns the register classes for the source arguments of a VOP[12C]
355 // instruction for the given SrcVTs.
356 class getInRC32 <list<ValueType> SrcVT> {
357 list<RegisterClass> ret = [
358 getVOPSrc0ForVT<SrcVT[0]>.ret,
359 getVOPSrc1ForVT<SrcVT[1]>.ret
363 // Returns the register class to use for sources of VOP3 instructions for the
365 class getVOP3SrcForVT<ValueType VT> {
366 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
369 // Returns the register classes for the source arguments of a VOP3
370 // instruction for the given SrcVTs.
371 class getInRC64 <list<ValueType> SrcVT> {
372 list<RegisterClass> ret = [
373 getVOP3SrcForVT<SrcVT[0]>.ret,
374 getVOP3SrcForVT<SrcVT[1]>.ret,
375 getVOP3SrcForVT<SrcVT[2]>.ret
379 // Returns 1 if the source arguments have modifiers, 0 if they do not.
380 class hasModifiers<ValueType SrcVT> {
381 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
382 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
385 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
386 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
387 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
388 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
392 // Returns the input arguments for VOP3 instructions for the given SrcVT.
393 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
394 RegisterClass Src2RC, int NumSrcArgs,
398 !if (!eq(NumSrcArgs, 1),
399 !if (!eq(HasModifiers, 1),
400 // VOP1 with modifiers
401 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
402 i32imm:$clamp, i32imm:$omod)
404 // VOP1 without modifiers
407 !if (!eq(NumSrcArgs, 2),
408 !if (!eq(HasModifiers, 1),
409 // VOP 2 with modifiers
410 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
411 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
412 i32imm:$clamp, i32imm:$omod)
414 // VOP2 without modifiers
415 (ins Src0RC:$src0, Src1RC:$src1)
417 /* NumSrcArgs == 3 */,
418 !if (!eq(HasModifiers, 1),
419 // VOP3 with modifiers
420 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
421 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
422 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
423 i32imm:$clamp, i32imm:$omod)
425 // VOP3 without modifiers
426 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
430 // Returns the assembly string for the inputs and outputs of a VOP[12C]
431 // instruction. This does not add the _e32 suffix, so it can be reused
433 class getAsm32 <int NumSrcArgs> {
434 string src1 = ", $src1";
435 string src2 = ", $src2";
436 string ret = " $dst, $src0"#
437 !if(!eq(NumSrcArgs, 1), "", src1)#
438 !if(!eq(NumSrcArgs, 3), src2, "");
441 // Returns the assembly string for the inputs and outputs of a VOP3
443 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
444 string src0 = "$src0_modifiers,";
445 string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
446 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
448 !if(!eq(HasModifiers, 0),
449 getAsm32<NumSrcArgs>.ret,
450 " $dst, "#src0#src1#src2#" $clamp, $omod");
454 class VOPProfile <list<ValueType> _ArgVT> {
456 field list<ValueType> ArgVT = _ArgVT;
458 field ValueType DstVT = ArgVT[0];
459 field ValueType Src0VT = ArgVT[1];
460 field ValueType Src1VT = ArgVT[2];
461 field ValueType Src2VT = ArgVT[3];
462 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
463 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
464 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
465 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
466 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
467 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
469 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
470 field bit HasModifiers = hasModifiers<Src0VT>.ret;
472 field dag Outs = (outs DstRC:$dst);
474 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
475 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
478 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
479 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
482 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
483 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
484 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
485 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
486 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
487 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
488 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
489 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
490 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
492 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
493 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
494 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
495 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
496 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
497 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
498 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
499 let Src0RC32 = VCSrc_32;
501 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
502 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
504 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
505 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
506 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
507 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
510 class VOP <string opName> {
511 string OpName = opName;
514 class VOP2_REV <string revOp, bit isOrig> {
515 string RevOp = revOp;
519 class AtomicNoRet <string noRetOp, bit isRet> {
520 string NoRetOp = noRetOp;
524 class SIMCInstr <string pseudo, int subtarget> {
525 string PseudoInstr = pseudo;
526 int Subtarget = subtarget;
529 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
531 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
532 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
533 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
534 bits<2> omod = !if(HasModifiers, ?, 0);
535 bits<1> clamp = !if(HasModifiers, ?, 0);
536 bits<9> src1 = !if(HasSrc1, ?, 0);
537 bits<9> src2 = !if(HasSrc2, ?, 0);
540 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
541 VOP3Common <outs, ins, "", pattern>,
543 SIMCInstr<opName, SISubtarget.NONE> {
547 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
548 VOP3 <op, outs, ins, asm, []>,
549 SIMCInstr<opName, SISubtarget.SI>;
551 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
552 string opName, int NumSrcArgs, bit HasMods = 1> {
554 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
556 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
557 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
558 !if(!eq(NumSrcArgs, 2), 0, 1),
563 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
564 list<dag> pattern, string opName, bit HasMods = 1> {
566 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
568 def _si : VOP3_Real_si <
569 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
570 outs, ins, asm, opName>,
571 VOP3DisableFields<0, 0, HasMods>;
574 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
575 list<dag> pattern, string opName, string revOp,
576 bit HasMods = 1, bit UseFullOp = 0> {
578 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
579 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
581 def _si : VOP3_Real_si <op,
582 outs, ins, asm, opName>,
583 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
584 VOP3DisableFields<1, 0, HasMods>;
587 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
588 list<dag> pattern, string opName, string revOp,
589 bit HasMods = 1, bit UseFullOp = 0> {
590 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
591 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
593 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
594 // can write it into any SGPR. We currently don't use the carry out,
595 // so for now hardcode it to VCC as well.
596 let sdst = SIOperand.VCC, Defs = [VCC] in {
597 def _si : VOP3b <op, outs, ins, asm, pattern>,
598 VOP3DisableFields<1, 0, HasMods>,
599 SIMCInstr<opName, SISubtarget.SI>,
600 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
601 } // End sdst = SIOperand.VCC, Defs = [VCC]
604 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
605 list<dag> pattern, string opName,
606 bit HasMods, bit defExec> {
608 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
610 def _si : VOP3_Real_si <
611 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
612 outs, ins, asm, opName>,
613 VOP3DisableFields<1, 0, HasMods> {
614 let Defs = !if(defExec, [EXEC], []);
618 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
619 dag ins32, string asm32, list<dag> pat32,
620 dag ins64, string asm64, list<dag> pat64,
623 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
625 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
628 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
629 SDPatternOperator node = null_frag> : VOP1_Helper <
631 P.Ins32, P.Asm32, [],
634 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
635 i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
636 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
640 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
641 list<dag> pattern, string revOp> :
642 VOP2 <op, outs, ins, opName#asm, pattern>,
644 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
646 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
647 dag ins32, string asm32, list<dag> pat32,
648 dag ins64, string asm64, list<dag> pat64,
649 string revOp, bit HasMods> {
650 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
652 defm _e64 : VOP3_2_m <
653 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
654 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
658 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
659 SDPatternOperator node = null_frag,
660 string revOp = opName> : VOP2_Helper <
662 P.Ins32, P.Asm32, [],
666 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
667 i32:$clamp, i32:$omod)),
668 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
669 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
670 revOp, P.HasModifiers
673 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
674 dag ins32, string asm32, list<dag> pat32,
675 dag ins64, string asm64, list<dag> pat64,
676 string revOp, bit HasMods> {
678 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
680 defm _e64 : VOP3b_2_m <
681 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
682 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
686 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
687 SDPatternOperator node = null_frag,
688 string revOp = opName> : VOP2b_Helper <
690 P.Ins32, P.Asm32, [],
694 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
695 i32:$clamp, i32:$omod)),
696 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
697 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
698 revOp, P.HasModifiers
701 multiclass VOPC_Helper <bits<8> op, string opName,
702 dag ins32, string asm32, list<dag> pat32,
703 dag out64, dag ins64, string asm64, list<dag> pat64,
704 bit HasMods, bit DefExec> {
705 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
706 let Defs = !if(DefExec, [EXEC], []);
709 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
713 multiclass VOPCInst <bits<8> op, string opName,
714 VOPProfile P, PatLeaf cond = COND_NULL,
715 bit DefExec = 0> : VOPC_Helper <
717 P.Ins32, P.Asm32, [],
718 (outs SReg_64:$dst), P.Ins64, P.Asm64,
721 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
722 i32:$clamp, i32:$omod)),
723 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
725 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
726 P.HasModifiers, DefExec
729 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
730 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
732 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
733 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
735 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
736 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
738 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
739 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
742 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
743 PatLeaf cond = COND_NULL>
744 : VOPCInst <op, opName, P, cond, 1>;
746 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
747 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
749 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
750 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
752 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
753 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
755 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
756 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
758 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
759 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
760 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
763 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
764 SDPatternOperator node = null_frag> : VOP3_Helper <
765 op, opName, P.Outs, P.Ins64, P.Asm64,
766 !if(!eq(P.NumSrcArgs, 3),
769 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
770 i32:$clamp, i32:$omod)),
771 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
772 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
773 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
775 !if(!eq(P.NumSrcArgs, 2),
778 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
779 i32:$clamp, i32:$omod)),
780 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
781 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
782 /* P.NumSrcArgs == 1 */,
785 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
786 i32:$clamp, i32:$omod))))],
787 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
788 P.NumSrcArgs, P.HasModifiers
791 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
792 string opName, list<dag> pattern> :
794 op, (outs vrc:$dst0, SReg_64:$dst1),
795 (ins arc:$src0, arc:$src1, arc:$src2,
796 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
797 opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern,
801 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
802 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
804 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
805 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
808 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
809 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i32:$clamp, i32:$omod)),
810 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
811 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
812 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
813 i32:$src1_modifiers, P.Src1VT:$src1,
814 i32:$src2_modifiers, P.Src2VT:$src2,
818 //===----------------------------------------------------------------------===//
819 // Vector I/O classes
820 //===----------------------------------------------------------------------===//
822 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
823 DS <op, outs, ins, asm, pat> {
826 // Single load interpret the 2 i8imm operands as a single i16 offset.
827 let offset0 = offset{7-0};
828 let offset1 = offset{15-8};
831 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
833 (outs regClass:$vdst),
834 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
835 asm#" $vdst, $addr, $offset, [M0]",
843 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
845 (outs regClass:$vdst),
846 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
847 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
855 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
858 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
859 asm#" $addr, $data0, $offset [M0]",
867 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
870 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
871 u8imm:$offset0, u8imm:$offset1),
872 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
879 // 1 address, 1 data.
880 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
883 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
884 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
885 AtomicNoRet<noRetOp, 1> {
891 let hasPostISelHook = 1; // Adjusted to no return version.
894 // 1 address, 2 data.
895 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
898 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
899 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
901 AtomicNoRet<noRetOp, 1> {
905 let hasPostISelHook = 1; // Adjusted to no return version.
908 // 1 address, 2 data.
909 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
912 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
913 asm#" $addr, $data0, $data1, $offset, [M0]",
915 AtomicNoRet<noRetOp, 0> {
920 // 1 address, 1 data.
921 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
924 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
925 asm#" $addr, $data0, $offset, [M0]",
927 AtomicNoRet<noRetOp, 0> {
934 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
936 bit IsAddr64 = is_addr64;
937 string OpName = NAME # suffix;
940 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
943 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
944 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
945 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
946 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
947 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
953 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
954 : MUBUF <op, outs, ins, asm, pattern> {
964 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
965 : MUBUF <op, outs, ins, asm, pattern> {
975 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
976 ValueType vt, SDPatternOperator atomic> {
978 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
980 // No return variants
983 def _ADDR64 : MUBUFAtomicAddr64 <
985 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
986 mbuf_offset:$offset, slc:$slc),
987 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
988 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
990 def _OFFSET : MUBUFAtomicOffset <
992 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
993 SSrc_32:$soffset, slc:$slc),
994 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
995 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
998 // Variant that return values
999 let glc = 1, Constraints = "$vdata = $vdata_in",
1000 DisableEncoding = "$vdata_in" in {
1002 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1003 op, (outs rc:$vdata),
1004 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1005 mbuf_offset:$offset, slc:$slc),
1006 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1008 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1009 i1:$slc), vt:$vdata_in))]
1010 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1012 def _RTN_OFFSET : MUBUFAtomicOffset <
1013 op, (outs rc:$vdata),
1014 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1015 SSrc_32:$soffset, slc:$slc),
1016 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1018 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1019 i1:$slc), vt:$vdata_in))]
1020 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1024 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1027 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1028 ValueType load_vt = i32,
1029 SDPatternOperator ld = null_frag> {
1031 let lds = 0, mayLoad = 1 in {
1035 let offen = 0, idxen = 0, vaddr = 0 in {
1036 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1037 (ins SReg_128:$srsrc,
1038 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1039 slc:$slc, tfe:$tfe),
1040 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1041 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1042 i32:$soffset, i16:$offset,
1043 i1:$glc, i1:$slc, i1:$tfe)))]>,
1044 MUBUFAddr64Table<0>;
1047 let offen = 1, idxen = 0 in {
1048 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1049 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1050 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1052 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1055 let offen = 0, idxen = 1 in {
1056 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1057 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1058 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1059 slc:$slc, tfe:$tfe),
1060 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1063 let offen = 1, idxen = 1 in {
1064 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1065 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1066 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1067 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1071 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1072 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1073 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1074 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1075 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1076 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1081 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1082 ValueType store_vt, SDPatternOperator st> {
1084 let addr64 = 0, lds = 0 in {
1088 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1089 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1091 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1092 "$glc"#"$slc"#"$tfe",
1096 let offen = 0, idxen = 0, vaddr = 0 in {
1097 def _OFFSET : MUBUF <
1099 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1100 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1101 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1102 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1103 i16:$offset, i1:$glc, i1:$slc,
1105 >, MUBUFAddr64Table<0>;
1106 } // offen = 0, idxen = 0, vaddr = 0
1108 let offen = 1, idxen = 0 in {
1109 def _OFFEN : MUBUF <
1111 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1112 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1113 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1114 "$glc"#"$slc"#"$tfe",
1117 } // end offen = 1, idxen = 0
1119 } // End addr64 = 0, lds = 0
1121 def _ADDR64 : MUBUF <
1123 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1124 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1125 [(st store_vt:$vdata,
1126 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1140 let soffset = 128; // ZERO
1144 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1145 FLAT <op, (outs regClass:$data),
1146 (ins VReg_64:$addr),
1147 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1154 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1155 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1156 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1168 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
1170 (outs regClass:$dst),
1171 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1172 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1173 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1174 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1175 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
1181 class MIMG_Mask <string op, int channels> {
1183 int Channels = channels;
1186 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1187 RegisterClass dst_rc,
1188 RegisterClass src_rc> : MIMG <
1190 (outs dst_rc:$vdata),
1191 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1192 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1194 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1195 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1200 let hasPostISelHook = 1;
1203 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1204 RegisterClass dst_rc,
1206 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1207 MIMG_Mask<asm#"_V1", channels>;
1208 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1209 MIMG_Mask<asm#"_V2", channels>;
1210 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1211 MIMG_Mask<asm#"_V4", channels>;
1214 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1215 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1216 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1217 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1218 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1221 class MIMG_Sampler_Helper <bits<7> op, string asm,
1222 RegisterClass dst_rc,
1223 RegisterClass src_rc> : MIMG <
1225 (outs dst_rc:$vdata),
1226 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1227 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1228 SReg_256:$srsrc, SReg_128:$ssamp),
1229 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1230 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1234 let hasPostISelHook = 1;
1237 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1238 RegisterClass dst_rc,
1240 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1241 MIMG_Mask<asm#"_V1", channels>;
1242 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1243 MIMG_Mask<asm#"_V2", channels>;
1244 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1245 MIMG_Mask<asm#"_V4", channels>;
1246 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1247 MIMG_Mask<asm#"_V8", channels>;
1248 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1249 MIMG_Mask<asm#"_V16", channels>;
1252 multiclass MIMG_Sampler <bits<7> op, string asm> {
1253 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1254 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1255 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1256 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1259 class MIMG_Gather_Helper <bits<7> op, string asm,
1260 RegisterClass dst_rc,
1261 RegisterClass src_rc> : MIMG <
1263 (outs dst_rc:$vdata),
1264 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1265 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1266 SReg_256:$srsrc, SReg_128:$ssamp),
1267 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1268 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1273 // DMASK was repurposed for GATHER4. 4 components are always
1274 // returned and DMASK works like a swizzle - it selects
1275 // the component to fetch. The only useful DMASK values are
1276 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1277 // (red,red,red,red) etc.) The ISA document doesn't mention
1279 // Therefore, disable all code which updates DMASK by setting these two:
1281 let hasPostISelHook = 0;
1284 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1285 RegisterClass dst_rc,
1287 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1288 MIMG_Mask<asm#"_V1", channels>;
1289 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1290 MIMG_Mask<asm#"_V2", channels>;
1291 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1292 MIMG_Mask<asm#"_V4", channels>;
1293 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1294 MIMG_Mask<asm#"_V8", channels>;
1295 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1296 MIMG_Mask<asm#"_V16", channels>;
1299 multiclass MIMG_Gather <bits<7> op, string asm> {
1300 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1301 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1302 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1303 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1306 //===----------------------------------------------------------------------===//
1307 // Vector instruction mappings
1308 //===----------------------------------------------------------------------===//
1310 // Maps an opcode in e32 form to its e64 equivalent
1311 def getVOPe64 : InstrMapping {
1312 let FilterClass = "VOP";
1313 let RowFields = ["OpName"];
1314 let ColFields = ["Size"];
1316 let ValueCols = [["8"]];
1319 // Maps an opcode in e64 form to its e32 equivalent
1320 def getVOPe32 : InstrMapping {
1321 let FilterClass = "VOP";
1322 let RowFields = ["OpName"];
1323 let ColFields = ["Size"];
1325 let ValueCols = [["4"]];
1328 // Maps an original opcode to its commuted version
1329 def getCommuteRev : InstrMapping {
1330 let FilterClass = "VOP2_REV";
1331 let RowFields = ["RevOp"];
1332 let ColFields = ["IsOrig"];
1334 let ValueCols = [["0"]];
1337 def getMaskedMIMGOp : InstrMapping {
1338 let FilterClass = "MIMG_Mask";
1339 let RowFields = ["Op"];
1340 let ColFields = ["Channels"];
1342 let ValueCols = [["1"], ["2"], ["3"] ];
1345 // Maps an commuted opcode to its original version
1346 def getCommuteOrig : InstrMapping {
1347 let FilterClass = "VOP2_REV";
1348 let RowFields = ["RevOp"];
1349 let ColFields = ["IsOrig"];
1351 let ValueCols = [["1"]];
1354 def isDS : InstrMapping {
1355 let FilterClass = "DS";
1356 let RowFields = ["Inst"];
1357 let ColFields = ["Size"];
1359 let ValueCols = [["8"]];
1362 def getMCOpcode : InstrMapping {
1363 let FilterClass = "SIMCInstr";
1364 let RowFields = ["PseudoInstr"];
1365 let ColFields = ["Subtarget"];
1366 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1367 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1370 def getAddr64Inst : InstrMapping {
1371 let FilterClass = "MUBUFAddr64Table";
1372 let RowFields = ["OpName"];
1373 let ColFields = ["IsAddr64"];
1375 let ValueCols = [["1"]];
1378 // Maps an atomic opcode to its version with a return value.
1379 def getAtomicRetOp : InstrMapping {
1380 let FilterClass = "AtomicNoRet";
1381 let RowFields = ["NoRetOp"];
1382 let ColFields = ["IsRet"];
1384 let ValueCols = [["1"]];
1387 // Maps an atomic opcode to its returnless version.
1388 def getAtomicNoRetOp : InstrMapping {
1389 let FilterClass = "AtomicNoRet";
1390 let RowFields = ["NoRetOp"];
1391 let ColFields = ["IsRet"];
1393 let ValueCols = [["0"]];
1396 include "SIInstructions.td"