1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def gds : Operand <i1> {
268 let PrintMethod = "printGDS";
270 def glc : Operand <i1> {
271 let PrintMethod = "printGLC";
273 def slc : Operand <i1> {
274 let PrintMethod = "printSLC";
276 def tfe : Operand <i1> {
277 let PrintMethod = "printTFE";
280 def omod : Operand <i32> {
281 let PrintMethod = "printOModSI";
284 def ClampMod : Operand <i1> {
285 let PrintMethod = "printClampSI";
288 } // End OperandType = "OPERAND_IMMEDIATE"
290 def VOPDstS64 : VOPDstOperand <SReg_64>;
292 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
296 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
297 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
299 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
300 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
301 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
302 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
303 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
304 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
306 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
307 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
308 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
309 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
311 //===----------------------------------------------------------------------===//
312 // SI assembler operands
313 //===----------------------------------------------------------------------===//
334 //===----------------------------------------------------------------------===//
336 // SI Instruction multiclass helpers.
338 // Instructions with _32 take 32-bit operands.
339 // Instructions with _64 take 64-bit operands.
341 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
342 // encoding is the standard encoding, but instruction that make use of
343 // any of the instruction modifiers must use the 64-bit encoding.
345 // Instructions with _e32 use the 32-bit encoding.
346 // Instructions with _e64 use the 64-bit encoding.
348 //===----------------------------------------------------------------------===//
350 class SIMCInstr <string pseudo, int subtarget> {
351 string PseudoInstr = pseudo;
352 int Subtarget = subtarget;
355 //===----------------------------------------------------------------------===//
357 //===----------------------------------------------------------------------===//
359 class EXPCommon : InstSI<
361 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
362 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
363 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
372 let isPseudo = 1, isCodeGenOnly = 1 in {
373 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
376 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
378 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
381 //===----------------------------------------------------------------------===//
383 //===----------------------------------------------------------------------===//
385 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
386 SOP1 <outs, ins, "", pattern>,
387 SIMCInstr<opName, SISubtarget.NONE> {
389 let isCodeGenOnly = 1;
392 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
393 SOP1 <outs, ins, asm, []>,
395 SIMCInstr<opName, SISubtarget.SI>;
397 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
398 SOP1 <outs, ins, asm, []>,
400 SIMCInstr<opName, SISubtarget.VI>;
402 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
405 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
407 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
409 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
413 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
414 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
415 opName#" $dst, $src0", pattern
418 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
419 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
420 opName#" $dst, $src0", pattern
423 // no input, 64-bit output.
424 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
425 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
427 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
432 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
438 // 64-bit input, no output
439 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
440 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
442 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
447 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
453 // 64-bit input, 32-bit output.
454 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
455 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
456 opName#" $dst, $src0", pattern
459 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
460 SOP2<outs, ins, "", pattern>,
461 SIMCInstr<opName, SISubtarget.NONE> {
463 let isCodeGenOnly = 1;
466 // Pseudo instructions have no encodings, but adding this field here allows
468 // let sdst = xxx in {
469 // for multiclasses that include both real and pseudo instructions.
470 field bits<7> sdst = 0;
473 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
474 SOP2<outs, ins, asm, []>,
476 SIMCInstr<opName, SISubtarget.SI>;
478 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
479 SOP2<outs, ins, asm, []>,
481 SIMCInstr<opName, SISubtarget.VI>;
483 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
484 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
485 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
487 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
488 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
489 opName#" $dst, $src0, $src1 [$scc]">;
491 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
492 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
493 opName#" $dst, $src0, $src1 [$scc]">;
496 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
499 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
501 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
503 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
507 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
508 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
509 opName#" $dst, $src0, $src1", pattern
512 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
513 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
514 opName#" $dst, $src0, $src1", pattern
517 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
518 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
519 opName#" $dst, $src0, $src1", pattern
522 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
523 string opName, PatLeaf cond> : SOPC <
524 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
525 opName#" $src0, $src1", []>;
527 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
528 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
530 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
531 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
533 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
534 SOPK <outs, ins, "", pattern>,
535 SIMCInstr<opName, SISubtarget.NONE> {
537 let isCodeGenOnly = 1;
540 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
541 SOPK <outs, ins, asm, []>,
543 SIMCInstr<opName, SISubtarget.SI>;
545 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
546 SOPK <outs, ins, asm, []>,
548 SIMCInstr<opName, SISubtarget.VI>;
550 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
551 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
554 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
555 opName#" $dst, $src0">;
557 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
558 opName#" $dst, $src0">;
561 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
562 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
563 (ins SReg_32:$src0, u16imm:$src1), pattern>;
565 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
566 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
568 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
569 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
572 //===----------------------------------------------------------------------===//
574 //===----------------------------------------------------------------------===//
576 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
577 SMRD <outs, ins, "", pattern>,
578 SIMCInstr<opName, SISubtarget.NONE> {
580 let isCodeGenOnly = 1;
583 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
585 SMRD <outs, ins, asm, []>,
587 SIMCInstr<opName, SISubtarget.SI>;
589 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
591 SMRD <outs, ins, asm, []>,
593 SIMCInstr<opName, SISubtarget.VI>;
595 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
596 string asm, list<dag> pattern> {
598 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
600 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
602 // glc is only applicable to scalar stores, which are not yet
605 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
609 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
610 RegisterClass dstClass> {
612 op, opName#"_IMM", 1, (outs dstClass:$dst),
613 (ins baseClass:$sbase, u32imm:$offset),
614 opName#" $dst, $sbase, $offset", []
617 defm _SGPR : SMRD_m <
618 op, opName#"_SGPR", 0, (outs dstClass:$dst),
619 (ins baseClass:$sbase, SReg_32:$soff),
620 opName#" $dst, $sbase, $soff", []
624 //===----------------------------------------------------------------------===//
625 // Vector ALU classes
626 //===----------------------------------------------------------------------===//
628 // This must always be right before the operand being input modified.
629 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
630 let PrintMethod = "printOperandAndMods";
632 def InputModsNoDefault : Operand <i32> {
633 let PrintMethod = "printOperandAndMods";
636 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
638 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
639 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
643 // Returns the register class to use for the destination of VOP[123C]
644 // instructions for the given VT.
645 class getVALUDstForVT<ValueType VT> {
646 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
647 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
648 VOPDstOperand<SReg_64>)); // else VT == i1
651 // Returns the register class to use for source 0 of VOP[12C]
652 // instructions for the given VT.
653 class getVOPSrc0ForVT<ValueType VT> {
654 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
657 // Returns the register class to use for source 1 of VOP[12C] for the
659 class getVOPSrc1ForVT<ValueType VT> {
660 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
663 // Returns the register class to use for sources of VOP3 instructions for the
665 class getVOP3SrcForVT<ValueType VT> {
666 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
669 // Returns 1 if the source arguments have modifiers, 0 if they do not.
670 class hasModifiers<ValueType SrcVT> {
671 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
672 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
675 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
676 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
677 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
678 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
682 // Returns the input arguments for VOP3 instructions for the given SrcVT.
683 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
684 RegisterOperand Src2RC, int NumSrcArgs,
688 !if (!eq(NumSrcArgs, 1),
689 !if (!eq(HasModifiers, 1),
690 // VOP1 with modifiers
691 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
692 ClampMod:$clamp, omod:$omod)
694 // VOP1 without modifiers
697 !if (!eq(NumSrcArgs, 2),
698 !if (!eq(HasModifiers, 1),
699 // VOP 2 with modifiers
700 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
701 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
702 ClampMod:$clamp, omod:$omod)
704 // VOP2 without modifiers
705 (ins Src0RC:$src0, Src1RC:$src1)
707 /* NumSrcArgs == 3 */,
708 !if (!eq(HasModifiers, 1),
709 // VOP3 with modifiers
710 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
711 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
712 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
713 ClampMod:$clamp, omod:$omod)
715 // VOP3 without modifiers
716 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
720 // Returns the assembly string for the inputs and outputs of a VOP[12C]
721 // instruction. This does not add the _e32 suffix, so it can be reused
723 class getAsm32 <int NumSrcArgs> {
724 string src1 = ", $src1";
725 string src2 = ", $src2";
726 string ret = "$dst, $src0"#
727 !if(!eq(NumSrcArgs, 1), "", src1)#
728 !if(!eq(NumSrcArgs, 3), src2, "");
731 // Returns the assembly string for the inputs and outputs of a VOP3
733 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
734 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
735 string src1 = !if(!eq(NumSrcArgs, 1), "",
736 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
737 " $src1_modifiers,"));
738 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
740 !if(!eq(HasModifiers, 0),
741 getAsm32<NumSrcArgs>.ret,
742 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
746 class VOPProfile <list<ValueType> _ArgVT> {
748 field list<ValueType> ArgVT = _ArgVT;
750 field ValueType DstVT = ArgVT[0];
751 field ValueType Src0VT = ArgVT[1];
752 field ValueType Src1VT = ArgVT[2];
753 field ValueType Src2VT = ArgVT[3];
754 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
755 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
756 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
757 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
758 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
759 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
761 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
762 field bit HasModifiers = hasModifiers<Src0VT>.ret;
764 field dag Outs = (outs DstRC:$dst);
766 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
767 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
770 field string Asm32 = getAsm32<NumSrcArgs>.ret;
771 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
774 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
775 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
776 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
777 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
778 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
779 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
780 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
781 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
782 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
784 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
785 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
786 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
787 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
788 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
789 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
790 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
791 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
792 let Src0RC32 = VCSrc_32;
795 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
796 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
797 let Asm64 = "$dst, $src0_modifiers, $src1";
800 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
801 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
802 let Asm64 = "$dst, $src0_modifiers, $src1";
805 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
806 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
807 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
808 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
809 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
810 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
811 let Asm64 = "$dst, $src0, $src1, $src2";
814 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
815 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
816 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
817 field string Asm = "$dst, $src0, $vsrc1, $src2";
819 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
820 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
821 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
824 class VOP <string opName> {
825 string OpName = opName;
828 class VOP2_REV <string revOp, bit isOrig> {
829 string RevOp = revOp;
833 class AtomicNoRet <string noRetOp, bit isRet> {
834 string NoRetOp = noRetOp;
838 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
839 VOP1Common <outs, ins, "", pattern>,
841 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
843 let isCodeGenOnly = 1;
849 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
850 VOP1<op.SI, outs, ins, asm, []>,
851 SIMCInstr <opName#"_e32", SISubtarget.SI>;
853 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
854 VOP1<op.VI, outs, ins, asm, []>,
855 SIMCInstr <opName#"_e32", SISubtarget.VI>;
857 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
859 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
861 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
863 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
866 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
868 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
870 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
873 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
874 VOP2Common <outs, ins, "", pattern>,
876 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
878 let isCodeGenOnly = 1;
881 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
882 VOP2 <op.SI, outs, ins, opName#asm, []>,
883 SIMCInstr <opName#"_e32", SISubtarget.SI>;
885 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
886 VOP2 <op.SI, outs, ins, opName#asm, []>,
887 SIMCInstr <opName#"_e32", SISubtarget.VI>;
889 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
890 string opName, string revOp> {
891 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
892 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
894 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
897 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
898 string opName, string revOp> {
899 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
900 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
902 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
904 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
908 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
910 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
911 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
912 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
913 bits<2> omod = !if(HasModifiers, ?, 0);
914 bits<1> clamp = !if(HasModifiers, ?, 0);
915 bits<9> src1 = !if(HasSrc1, ?, 0);
916 bits<9> src2 = !if(HasSrc2, ?, 0);
919 class VOP3DisableModFields <bit HasSrc0Mods,
922 bit HasOutputMods = 0> {
923 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
924 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
925 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
926 bits<2> omod = !if(HasOutputMods, ?, 0);
927 bits<1> clamp = !if(HasOutputMods, ?, 0);
930 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
931 VOP3Common <outs, ins, "", pattern>,
933 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
935 let isCodeGenOnly = 1;
938 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
939 VOP3Common <outs, ins, asm, []>,
941 SIMCInstr<opName#"_e64", SISubtarget.SI>;
943 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
944 VOP3Common <outs, ins, asm, []>,
946 SIMCInstr <opName#"_e64", SISubtarget.VI>;
948 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
949 VOP3Common <outs, ins, asm, []>,
951 SIMCInstr<opName#"_e64", SISubtarget.SI>;
953 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
954 VOP3Common <outs, ins, asm, []>,
956 SIMCInstr <opName#"_e64", SISubtarget.VI>;
958 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
959 string opName, int NumSrcArgs, bit HasMods = 1> {
961 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
963 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
964 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
965 !if(!eq(NumSrcArgs, 2), 0, 1),
967 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
968 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
969 !if(!eq(NumSrcArgs, 2), 0, 1),
973 // VOP3_m without source modifiers
974 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
975 string opName, int NumSrcArgs, bit HasMods = 1> {
977 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
979 let src0_modifiers = 0,
984 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
985 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
989 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
990 list<dag> pattern, string opName, bit HasMods = 1> {
992 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
994 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
995 VOP3DisableFields<0, 0, HasMods>;
997 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
998 VOP3DisableFields<0, 0, HasMods>;
1001 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1002 list<dag> pattern, string opName, bit HasMods = 1> {
1004 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1006 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1007 VOP3DisableFields<0, 0, HasMods>;
1008 // No VI instruction. This class is for SI only.
1011 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1012 list<dag> pattern, string opName, string revOp,
1013 bit HasMods = 1, bit UseFullOp = 0> {
1015 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1016 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1018 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1019 VOP3DisableFields<1, 0, HasMods>;
1021 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1022 VOP3DisableFields<1, 0, HasMods>;
1025 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1026 list<dag> pattern, string opName, string revOp,
1027 bit HasMods = 1, bit UseFullOp = 0> {
1029 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1030 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1032 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1033 VOP3DisableFields<1, 0, HasMods>;
1035 // No VI instruction. This class is for SI only.
1038 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1039 // option of implicit vcc use?
1040 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1041 list<dag> pattern, string opName, string revOp,
1042 bit HasMods = 1, bit UseFullOp = 0> {
1043 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1044 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1046 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1047 // can write it into any SGPR. We currently don't use the carry out,
1048 // so for now hardcode it to VCC as well.
1049 let sdst = SIOperand.VCC, Defs = [VCC] in {
1050 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1051 VOP3DisableFields<1, 0, HasMods>;
1053 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1054 VOP3DisableFields<1, 0, HasMods>;
1055 } // End sdst = SIOperand.VCC, Defs = [VCC]
1058 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1059 list<dag> pattern, string opName, string revOp,
1060 bit HasMods = 1, bit UseFullOp = 0> {
1061 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1064 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1065 VOP3DisableFields<1, 1, HasMods>;
1067 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1068 VOP3DisableFields<1, 1, HasMods>;
1071 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1072 list<dag> pattern, string opName,
1073 bit HasMods, bit defExec, string revOp> {
1075 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1076 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1078 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1079 VOP3DisableFields<1, 0, HasMods> {
1080 let Defs = !if(defExec, [EXEC], []);
1083 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1084 VOP3DisableFields<1, 0, HasMods> {
1085 let Defs = !if(defExec, [EXEC], []);
1089 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1090 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1091 string asm, list<dag> pattern = []> {
1092 let isPseudo = 1, isCodeGenOnly = 1 in {
1093 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1094 SIMCInstr<opName, SISubtarget.NONE>;
1097 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1098 SIMCInstr <opName, SISubtarget.SI>;
1100 def _vi : VOP3Common <outs, ins, asm, []>,
1102 VOP3DisableFields <1, 0, 0>,
1103 SIMCInstr <opName, SISubtarget.VI>;
1106 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1107 dag ins32, string asm32, list<dag> pat32,
1108 dag ins64, string asm64, list<dag> pat64,
1111 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1113 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1116 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1117 SDPatternOperator node = null_frag> : VOP1_Helper <
1119 P.Ins32, P.Asm32, [],
1122 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1123 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1124 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1128 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1129 SDPatternOperator node = null_frag> {
1131 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1133 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1135 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1136 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1137 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1138 opName, P.HasModifiers>;
1141 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1142 dag ins32, string asm32, list<dag> pat32,
1143 dag ins64, string asm64, list<dag> pat64,
1144 string revOp, bit HasMods> {
1145 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1147 defm _e64 : VOP3_2_m <op,
1148 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1152 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1153 SDPatternOperator node = null_frag,
1154 string revOp = opName> : VOP2_Helper <
1156 P.Ins32, P.Asm32, [],
1160 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1161 i1:$clamp, i32:$omod)),
1162 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1163 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1164 revOp, P.HasModifiers
1167 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1168 SDPatternOperator node = null_frag,
1169 string revOp = opName> {
1170 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1172 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1175 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1176 i1:$clamp, i32:$omod)),
1177 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1178 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1179 opName, revOp, P.HasModifiers>;
1182 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1183 dag ins32, string asm32, list<dag> pat32,
1184 dag ins64, string asm64, list<dag> pat64,
1185 string revOp, bit HasMods> {
1187 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1189 defm _e64 : VOP3b_2_m <op,
1190 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1194 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1195 SDPatternOperator node = null_frag,
1196 string revOp = opName> : VOP2b_Helper <
1198 P.Ins32, P.Asm32, [],
1202 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1203 i1:$clamp, i32:$omod)),
1204 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1205 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1206 revOp, P.HasModifiers
1209 // A VOP2 instruction that is VOP3-only on VI.
1210 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1211 dag ins32, string asm32, list<dag> pat32,
1212 dag ins64, string asm64, list<dag> pat64,
1213 string revOp, bit HasMods> {
1214 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1216 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1220 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1221 SDPatternOperator node = null_frag,
1222 string revOp = opName>
1225 P.Ins32, P.Asm32, [],
1229 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1230 i1:$clamp, i32:$omod)),
1231 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1232 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1233 revOp, P.HasModifiers
1236 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1238 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1240 let isCodeGenOnly = 0 in {
1241 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1242 !strconcat(opName, VOP_MADK.Asm), []>,
1243 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1246 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1247 !strconcat(opName, VOP_MADK.Asm), []>,
1248 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1250 } // End isCodeGenOnly = 0
1253 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1254 VOPCCommon <ins, "", pattern>,
1256 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1258 let isCodeGenOnly = 1;
1261 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1262 string opName, bit DefExec, string revOpName = ""> {
1263 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1265 def _si : VOPC<op.SI, ins, asm, []>,
1266 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1267 let Defs = !if(DefExec, [EXEC], []);
1268 let hasSideEffects = DefExec;
1271 def _vi : VOPC<op.VI, ins, asm, []>,
1272 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1273 let Defs = !if(DefExec, [EXEC], []);
1274 let hasSideEffects = DefExec;
1278 multiclass VOPC_Helper <vopc op, string opName,
1279 dag ins32, string asm32, list<dag> pat32,
1280 dag out64, dag ins64, string asm64, list<dag> pat64,
1281 bit HasMods, bit DefExec, string revOp> {
1282 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1284 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1285 opName, HasMods, DefExec, revOp>;
1288 // Special case for class instructions which only have modifiers on
1289 // the 1st source operand.
1290 multiclass VOPC_Class_Helper <vopc op, string opName,
1291 dag ins32, string asm32, list<dag> pat32,
1292 dag out64, dag ins64, string asm64, list<dag> pat64,
1293 bit HasMods, bit DefExec, string revOp> {
1294 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1296 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1297 opName, HasMods, DefExec, revOp>,
1298 VOP3DisableModFields<1, 0, 0>;
1301 multiclass VOPCInst <vopc op, string opName,
1302 VOPProfile P, PatLeaf cond = COND_NULL,
1303 string revOp = opName,
1304 bit DefExec = 0> : VOPC_Helper <
1306 P.Ins32, P.Asm32, [],
1307 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1310 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1311 i1:$clamp, i32:$omod)),
1312 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1314 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1315 P.HasModifiers, DefExec, revOp
1318 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1319 bit DefExec = 0> : VOPC_Class_Helper <
1321 P.Ins32, P.Asm32, [],
1322 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1325 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1326 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1327 P.HasModifiers, DefExec, opName
1331 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1332 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1334 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1335 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1337 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1338 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1340 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1341 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1344 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1345 PatLeaf cond = COND_NULL,
1347 : VOPCInst <op, opName, P, cond, revOp, 1>;
1349 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1350 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1352 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1353 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1355 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1356 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1358 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1359 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1361 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1362 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1363 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1366 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1367 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1369 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1370 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1372 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1373 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1375 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1376 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1378 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1379 SDPatternOperator node = null_frag> : VOP3_Helper <
1380 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1381 !if(!eq(P.NumSrcArgs, 3),
1384 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1385 i1:$clamp, i32:$omod)),
1386 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1387 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1388 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1390 !if(!eq(P.NumSrcArgs, 2),
1393 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1394 i1:$clamp, i32:$omod)),
1395 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1396 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1397 /* P.NumSrcArgs == 1 */,
1400 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1401 i1:$clamp, i32:$omod))))],
1402 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1403 P.NumSrcArgs, P.HasModifiers
1406 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1407 // only VOP instruction that implicitly reads VCC.
1408 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1410 SDPatternOperator node = null_frag> : VOP3_Helper <
1412 (outs P.DstRC.RegClass:$dst),
1413 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1414 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1415 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1418 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1420 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1421 i1:$clamp, i32:$omod)),
1422 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1423 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1428 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1429 string opName, list<dag> pattern> :
1431 op, (outs vrc:$vdst, SReg_64:$sdst),
1432 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1433 InputModsNoDefault:$src1_modifiers, arc:$src1,
1434 InputModsNoDefault:$src2_modifiers, arc:$src2,
1435 ClampMod:$clamp, omod:$omod),
1436 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1437 opName, opName, 1, 1
1440 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1441 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1443 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1444 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1447 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1448 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1449 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1450 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1451 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1452 i32:$src1_modifiers, P.Src1VT:$src1,
1453 i32:$src2_modifiers, P.Src2VT:$src2,
1457 //===----------------------------------------------------------------------===//
1458 // Interpolation opcodes
1459 //===----------------------------------------------------------------------===//
1461 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1462 VINTRPCommon <outs, ins, "", pattern>,
1463 SIMCInstr<opName, SISubtarget.NONE> {
1465 let isCodeGenOnly = 1;
1468 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1470 VINTRPCommon <outs, ins, asm, []>,
1472 SIMCInstr<opName, SISubtarget.SI>;
1474 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1476 VINTRPCommon <outs, ins, asm, []>,
1478 SIMCInstr<opName, SISubtarget.VI>;
1480 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1481 string disableEncoding = "", string constraints = "",
1482 list<dag> pattern = []> {
1483 let DisableEncoding = disableEncoding,
1484 Constraints = constraints in {
1485 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1487 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1489 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1493 //===----------------------------------------------------------------------===//
1494 // Vector I/O classes
1495 //===----------------------------------------------------------------------===//
1497 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1498 DS <outs, ins, "", pattern>,
1499 SIMCInstr <opName, SISubtarget.NONE> {
1501 let isCodeGenOnly = 1;
1504 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1505 DS <outs, ins, asm, []>,
1507 SIMCInstr <opName, SISubtarget.SI>;
1509 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1510 DS <outs, ins, asm, []>,
1512 SIMCInstr <opName, SISubtarget.VI>;
1514 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1515 DS_Real_si <op,opName, outs, ins, asm> {
1517 // Single load interpret the 2 i8imm operands as a single i16 offset.
1519 let offset0 = offset{7-0};
1520 let offset1 = offset{15-8};
1523 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1524 DS_Real_vi <op, opName, outs, ins, asm> {
1526 // Single load interpret the 2 i8imm operands as a single i16 offset.
1528 let offset0 = offset{7-0};
1529 let offset1 = offset{15-8};
1532 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1533 dag outs = (outs rc:$vdst),
1534 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1535 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1537 def "" : DS_Pseudo <opName, outs, ins, []>;
1539 let data0 = 0, data1 = 0 in {
1540 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1541 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1545 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1546 dag outs = (outs rc:$vdst),
1547 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1548 gds:$gds, M0Reg:$m0),
1549 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1551 def "" : DS_Pseudo <opName, outs, ins, []>;
1553 let data0 = 0, data1 = 0 in {
1554 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1555 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1559 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1561 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1563 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1565 def "" : DS_Pseudo <opName, outs, ins, []>,
1566 AtomicNoRet<opName, 0>;
1568 let data1 = 0, vdst = 0 in {
1569 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1570 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1574 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1576 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1577 ds_offset0:$offset0, ds_offset1:$offset1, gds:$gds, M0Reg:$m0),
1578 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1580 def "" : DS_Pseudo <opName, outs, ins, []>;
1583 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1584 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1588 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1589 string noRetOp = "",
1590 dag outs = (outs rc:$vdst),
1591 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1593 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1595 def "" : DS_Pseudo <opName, outs, ins, []>,
1596 AtomicNoRet<noRetOp, 1>;
1599 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1600 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1604 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1605 string noRetOp = "", dag ins,
1606 dag outs = (outs rc:$vdst),
1607 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1609 def "" : DS_Pseudo <opName, outs, ins, []>,
1610 AtomicNoRet<noRetOp, 1>;
1612 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1613 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1616 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1617 string noRetOp = "", RegisterClass src = rc> :
1618 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1619 (ins VGPR_32:$addr, src:$data0, src:$data1,
1620 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1623 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1624 string noRetOp = opName,
1626 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1627 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1628 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1630 def "" : DS_Pseudo <opName, outs, ins, []>,
1631 AtomicNoRet<noRetOp, 0>;
1634 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1635 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1639 multiclass DS_0A_RET <bits<8> op, string opName,
1640 dag outs = (outs VGPR_32:$vdst),
1641 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1642 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1644 let mayLoad = 1, mayStore = 1 in {
1645 def "" : DS_Pseudo <opName, outs, ins, []>;
1647 let addr = 0, data0 = 0, data1 = 0 in {
1648 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1649 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1650 } // end addr = 0, data0 = 0, data1 = 0
1651 } // end mayLoad = 1, mayStore = 1
1654 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1655 dag outs = (outs VGPR_32:$vdst),
1656 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1657 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1659 def "" : DS_Pseudo <opName, outs, ins, []>;
1661 let data0 = 0, data1 = 0, gds = 1 in {
1662 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1663 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1664 } // end data0 = 0, data1 = 0, gds = 1
1667 multiclass DS_1A_GDS <bits<8> op, string opName,
1669 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1670 string asm = opName#" $addr gds"> {
1672 def "" : DS_Pseudo <opName, outs, ins, []>;
1674 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1675 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1676 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1677 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1680 multiclass DS_1A <bits<8> op, string opName,
1682 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1683 string asm = opName#" $addr"#"$offset"#"$gds"> {
1685 let mayLoad = 1, mayStore = 1 in {
1686 def "" : DS_Pseudo <opName, outs, ins, []>;
1688 let vdst = 0, data0 = 0, data1 = 0 in {
1689 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1690 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1691 } // let vdst = 0, data0 = 0, data1 = 0
1692 } // end mayLoad = 1, mayStore = 1
1695 //===----------------------------------------------------------------------===//
1697 //===----------------------------------------------------------------------===//
1699 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1700 MTBUF <outs, ins, "", pattern>,
1701 SIMCInstr<opName, SISubtarget.NONE> {
1703 let isCodeGenOnly = 1;
1706 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1708 MTBUF <outs, ins, asm, []>,
1710 SIMCInstr<opName, SISubtarget.SI>;
1712 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1713 MTBUF <outs, ins, asm, []>,
1715 SIMCInstr <opName, SISubtarget.VI>;
1717 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1718 list<dag> pattern> {
1720 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1722 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1724 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1728 let mayStore = 1, mayLoad = 0 in {
1730 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1731 RegisterClass regClass> : MTBUF_m <
1733 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1734 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1735 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1736 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1737 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1740 } // mayStore = 1, mayLoad = 0
1742 let mayLoad = 1, mayStore = 0 in {
1744 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1745 RegisterClass regClass> : MTBUF_m <
1746 op, opName, (outs regClass:$dst),
1747 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1748 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1749 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1750 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1751 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1754 } // mayLoad = 1, mayStore = 0
1756 //===----------------------------------------------------------------------===//
1758 //===----------------------------------------------------------------------===//
1760 class mubuf <bits<7> si, bits<7> vi = si> {
1761 field bits<7> SI = si;
1762 field bits<7> VI = vi;
1765 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1766 bit IsAddr64 = is_addr64;
1767 string OpName = NAME # suffix;
1770 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1771 MUBUF <outs, ins, "", pattern>,
1772 SIMCInstr<opName, SISubtarget.NONE> {
1774 let isCodeGenOnly = 1;
1776 // dummy fields, so that we can use let statements around multiclasses
1786 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1788 MUBUF <outs, ins, asm, []>,
1790 SIMCInstr<opName, SISubtarget.SI> {
1794 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1796 MUBUF <outs, ins, asm, []>,
1798 SIMCInstr<opName, SISubtarget.VI> {
1802 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1803 list<dag> pattern> {
1805 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1806 MUBUFAddr64Table <0>;
1809 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1812 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1815 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1816 dag ins, string asm, list<dag> pattern> {
1818 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1819 MUBUFAddr64Table <1>;
1822 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1825 // There is no VI version. If the pseudo is selected, it should be lowered
1826 // for VI appropriately.
1829 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1830 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1834 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1835 string asm, list<dag> pattern, bit is_return> {
1837 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1838 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1839 AtomicNoRet<NAME#"_OFFSET", is_return>;
1841 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1843 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1846 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1850 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1851 string asm, list<dag> pattern, bit is_return> {
1853 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1854 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1855 AtomicNoRet<NAME#"_ADDR64", is_return>;
1857 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1858 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1861 // There is no VI version. If the pseudo is selected, it should be lowered
1862 // for VI appropriately.
1865 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1866 ValueType vt, SDPatternOperator atomic> {
1868 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1870 // No return variants
1873 defm _ADDR64 : MUBUFAtomicAddr64_m <
1874 op, name#"_addr64", (outs),
1875 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1876 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1877 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1880 defm _OFFSET : MUBUFAtomicOffset_m <
1881 op, name#"_offset", (outs),
1882 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
1884 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1888 // Variant that return values
1889 let glc = 1, Constraints = "$vdata = $vdata_in",
1890 DisableEncoding = "$vdata_in" in {
1892 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1893 op, name#"_rtn_addr64", (outs rc:$vdata),
1894 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1895 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1896 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1898 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1899 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1902 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1903 op, name#"_rtn_offset", (outs rc:$vdata),
1904 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
1905 mbuf_offset:$offset, slc:$slc),
1906 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1908 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1909 i1:$slc), vt:$vdata_in))], 1
1914 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1917 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1918 ValueType load_vt = i32,
1919 SDPatternOperator ld = null_frag> {
1921 let mayLoad = 1, mayStore = 0 in {
1922 let offen = 0, idxen = 0, vaddr = 0 in {
1923 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1924 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
1925 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1926 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1927 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1928 i32:$soffset, i16:$offset,
1929 i1:$glc, i1:$slc, i1:$tfe)))]>;
1932 let offen = 1, idxen = 0 in {
1933 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1934 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
1935 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1937 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1940 let offen = 0, idxen = 1 in {
1941 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1942 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
1943 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1944 slc:$slc, tfe:$tfe),
1945 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1948 let offen = 1, idxen = 1 in {
1949 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1950 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
1951 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1952 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1955 let offen = 0, idxen = 0 in {
1956 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1957 (ins VReg_64:$vaddr, SReg_128:$srsrc,
1958 SCSrc_32:$soffset, mbuf_offset:$offset,
1959 glc:$glc, slc:$slc, tfe:$tfe),
1960 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
1961 "$glc"#"$slc"#"$tfe",
1962 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1963 i64:$vaddr, i32:$soffset,
1964 i16:$offset, i1:$glc, i1:$slc,
1970 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1971 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
1972 let mayLoad = 0, mayStore = 1 in {
1973 defm : MUBUF_m <op, name, (outs),
1974 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
1975 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1977 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1978 "$glc"#"$slc"#"$tfe", []>;
1980 let offen = 0, idxen = 0, vaddr = 0 in {
1981 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1982 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
1983 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1984 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1985 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1986 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1987 } // offen = 0, idxen = 0, vaddr = 0
1989 let offen = 1, idxen = 0 in {
1990 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1991 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
1992 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1993 slc:$slc, tfe:$tfe),
1994 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1995 "$glc"#"$slc"#"$tfe", []>;
1996 } // end offen = 1, idxen = 0
1998 let offen = 0, idxen = 1 in {
1999 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2000 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2001 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2002 slc:$slc, tfe:$tfe),
2003 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2006 let offen = 1, idxen = 1 in {
2007 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2008 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2009 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2010 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2013 let offen = 0, idxen = 0 in {
2014 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2015 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2017 mbuf_offset:$offset, glc:$glc, slc:$slc,
2019 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2020 "$offset"#"$glc"#"$slc"#"$tfe",
2021 [(st store_vt:$vdata,
2022 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2023 i32:$soffset, i16:$offset,
2024 i1:$glc, i1:$slc, i1:$tfe))]>;
2026 } // End mayLoad = 0, mayStore = 1
2029 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2030 FLAT <op, (outs regClass:$vdst),
2031 (ins VReg_64:$addr),
2032 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2040 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2041 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2042 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2055 class MIMG_Mask <string op, int channels> {
2057 int Channels = channels;
2060 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2061 RegisterClass dst_rc,
2062 RegisterClass src_rc> : MIMG <
2064 (outs dst_rc:$vdata),
2065 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2066 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2068 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2069 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2074 let hasPostISelHook = 1;
2077 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2078 RegisterClass dst_rc,
2080 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2081 MIMG_Mask<asm#"_V1", channels>;
2082 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2083 MIMG_Mask<asm#"_V2", channels>;
2084 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2085 MIMG_Mask<asm#"_V4", channels>;
2088 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2089 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2090 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2091 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2092 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2095 class MIMG_Sampler_Helper <bits<7> op, string asm,
2096 RegisterClass dst_rc,
2097 RegisterClass src_rc, int wqm> : MIMG <
2099 (outs dst_rc:$vdata),
2100 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2101 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2102 SReg_256:$srsrc, SReg_128:$ssamp),
2103 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2104 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2108 let hasPostISelHook = 1;
2112 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2113 RegisterClass dst_rc,
2114 int channels, int wqm> {
2115 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2116 MIMG_Mask<asm#"_V1", channels>;
2117 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2118 MIMG_Mask<asm#"_V2", channels>;
2119 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2120 MIMG_Mask<asm#"_V4", channels>;
2121 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2122 MIMG_Mask<asm#"_V8", channels>;
2123 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2124 MIMG_Mask<asm#"_V16", channels>;
2127 multiclass MIMG_Sampler <bits<7> op, string asm> {
2128 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2129 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2130 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2131 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2134 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2135 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2136 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2137 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2138 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2141 class MIMG_Gather_Helper <bits<7> op, string asm,
2142 RegisterClass dst_rc,
2143 RegisterClass src_rc, int wqm> : MIMG <
2145 (outs dst_rc:$vdata),
2146 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2147 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2148 SReg_256:$srsrc, SReg_128:$ssamp),
2149 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2150 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2155 // DMASK was repurposed for GATHER4. 4 components are always
2156 // returned and DMASK works like a swizzle - it selects
2157 // the component to fetch. The only useful DMASK values are
2158 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2159 // (red,red,red,red) etc.) The ISA document doesn't mention
2161 // Therefore, disable all code which updates DMASK by setting these two:
2163 let hasPostISelHook = 0;
2167 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2168 RegisterClass dst_rc,
2169 int channels, int wqm> {
2170 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2171 MIMG_Mask<asm#"_V1", channels>;
2172 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2173 MIMG_Mask<asm#"_V2", channels>;
2174 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2175 MIMG_Mask<asm#"_V4", channels>;
2176 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2177 MIMG_Mask<asm#"_V8", channels>;
2178 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2179 MIMG_Mask<asm#"_V16", channels>;
2182 multiclass MIMG_Gather <bits<7> op, string asm> {
2183 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2184 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2185 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2186 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2189 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2190 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2191 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2192 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2193 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2196 //===----------------------------------------------------------------------===//
2197 // Vector instruction mappings
2198 //===----------------------------------------------------------------------===//
2200 // Maps an opcode in e32 form to its e64 equivalent
2201 def getVOPe64 : InstrMapping {
2202 let FilterClass = "VOP";
2203 let RowFields = ["OpName"];
2204 let ColFields = ["Size"];
2206 let ValueCols = [["8"]];
2209 // Maps an opcode in e64 form to its e32 equivalent
2210 def getVOPe32 : InstrMapping {
2211 let FilterClass = "VOP";
2212 let RowFields = ["OpName"];
2213 let ColFields = ["Size"];
2215 let ValueCols = [["4"]];
2218 def getMaskedMIMGOp : InstrMapping {
2219 let FilterClass = "MIMG_Mask";
2220 let RowFields = ["Op"];
2221 let ColFields = ["Channels"];
2223 let ValueCols = [["1"], ["2"], ["3"] ];
2226 // Maps an commuted opcode to its original version
2227 def getCommuteOrig : InstrMapping {
2228 let FilterClass = "VOP2_REV";
2229 let RowFields = ["RevOp"];
2230 let ColFields = ["IsOrig"];
2232 let ValueCols = [["1"]];
2235 // Maps an original opcode to its commuted version
2236 def getCommuteRev : InstrMapping {
2237 let FilterClass = "VOP2_REV";
2238 let RowFields = ["RevOp"];
2239 let ColFields = ["IsOrig"];
2241 let ValueCols = [["0"]];
2244 def getCommuteCmpOrig : InstrMapping {
2245 let FilterClass = "VOP2_REV";
2246 let RowFields = ["RevOp"];
2247 let ColFields = ["IsOrig"];
2249 let ValueCols = [["1"]];
2252 // Maps an original opcode to its commuted version
2253 def getCommuteCmpRev : InstrMapping {
2254 let FilterClass = "VOP2_REV";
2255 let RowFields = ["RevOp"];
2256 let ColFields = ["IsOrig"];
2258 let ValueCols = [["0"]];
2262 def getMCOpcodeGen : InstrMapping {
2263 let FilterClass = "SIMCInstr";
2264 let RowFields = ["PseudoInstr"];
2265 let ColFields = ["Subtarget"];
2266 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2267 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2270 def getAddr64Inst : InstrMapping {
2271 let FilterClass = "MUBUFAddr64Table";
2272 let RowFields = ["OpName"];
2273 let ColFields = ["IsAddr64"];
2275 let ValueCols = [["1"]];
2278 // Maps an atomic opcode to its version with a return value.
2279 def getAtomicRetOp : InstrMapping {
2280 let FilterClass = "AtomicNoRet";
2281 let RowFields = ["NoRetOp"];
2282 let ColFields = ["IsRet"];
2284 let ValueCols = [["1"]];
2287 // Maps an atomic opcode to its returnless version.
2288 def getAtomicNoRetOp : InstrMapping {
2289 let FilterClass = "AtomicNoRet";
2290 let RowFields = ["NoRetOp"];
2291 let ColFields = ["IsRet"];
2293 let ValueCols = [["0"]];
2296 include "SIInstructions.td"
2297 include "CIInstructions.td"
2298 include "VIInstructions.td"