1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
386 SOP1 <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
391 SOP1 <outs, ins, asm, []>,
393 SIMCInstr<opName, SISubtarget.VI>;
395 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
396 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
399 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
400 opName#" $dst, $src0">;
402 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
403 opName#" $dst, $src0">;
406 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
407 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
410 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
411 opName#" $dst, $src0">;
413 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
414 opName#" $dst, $src0">;
417 // no input, 64-bit output.
418 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
419 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
421 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
426 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
432 // 64-bit input, 32-bit output.
433 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
434 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
437 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
438 opName#" $dst, $src0">;
440 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
441 opName#" $dst, $src0">;
444 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
445 SOP2<outs, ins, "", pattern>,
446 SIMCInstr<opName, SISubtarget.NONE> {
451 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
452 SOP2<outs, ins, asm, []>,
454 SIMCInstr<opName, SISubtarget.SI>;
456 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
457 SOP2<outs, ins, asm, []>,
459 SIMCInstr<opName, SISubtarget.VI>;
461 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
462 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
463 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
465 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
466 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
467 opName#" $dst, $src0, $src1 [$scc]">;
469 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
470 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
471 opName#" $dst, $src0, $src1 [$scc]">;
474 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
475 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
476 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
478 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
479 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
481 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
482 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
485 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
486 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
487 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
489 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
490 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
492 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
493 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
496 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
497 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
498 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
500 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
501 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
503 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
504 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
508 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
509 string opName, PatLeaf cond> : SOPC <
510 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
511 opName#" $dst, $src0, $src1", []>;
513 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
514 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
516 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
517 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
519 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
520 SOPK <outs, ins, "", pattern>,
521 SIMCInstr<opName, SISubtarget.NONE> {
525 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
526 SOPK <outs, ins, asm, []>,
528 SIMCInstr<opName, SISubtarget.SI>;
530 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
531 SOPK <outs, ins, asm, []>,
533 SIMCInstr<opName, SISubtarget.VI>;
535 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
536 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
539 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
540 opName#" $dst, $src0">;
542 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
543 opName#" $dst, $src0">;
546 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
547 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
548 (ins SReg_32:$src0, u16imm:$src1), pattern>;
550 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
551 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
553 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
554 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
557 //===----------------------------------------------------------------------===//
559 //===----------------------------------------------------------------------===//
561 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
562 SMRD <outs, ins, "", pattern>,
563 SIMCInstr<opName, SISubtarget.NONE> {
567 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
569 SMRD <outs, ins, asm, []>,
571 SIMCInstr<opName, SISubtarget.SI>;
573 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
575 SMRD <outs, ins, asm, []>,
577 SIMCInstr<opName, SISubtarget.VI>;
579 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
580 string asm, list<dag> pattern> {
582 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
584 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
586 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
589 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
590 RegisterClass dstClass> {
592 op, opName#"_IMM", 1, (outs dstClass:$dst),
593 (ins baseClass:$sbase, u32imm:$offset),
594 opName#" $dst, $sbase, $offset", []
597 defm _SGPR : SMRD_m <
598 op, opName#"_SGPR", 0, (outs dstClass:$dst),
599 (ins baseClass:$sbase, SReg_32:$soff),
600 opName#" $dst, $sbase, $soff", []
604 //===----------------------------------------------------------------------===//
605 // Vector ALU classes
606 //===----------------------------------------------------------------------===//
608 // This must always be right before the operand being input modified.
609 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
610 let PrintMethod = "printOperandAndMods";
612 def InputModsNoDefault : Operand <i32> {
613 let PrintMethod = "printOperandAndMods";
616 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
618 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
619 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
623 // Returns the register class to use for the destination of VOP[123C]
624 // instructions for the given VT.
625 class getVALUDstForVT<ValueType VT> {
626 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
627 !if(!eq(VT.Size, 64), VReg_64,
628 SReg_64)); // else VT == i1
631 // Returns the register class to use for source 0 of VOP[12C]
632 // instructions for the given VT.
633 class getVOPSrc0ForVT<ValueType VT> {
634 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
637 // Returns the register class to use for source 1 of VOP[12C] for the
639 class getVOPSrc1ForVT<ValueType VT> {
640 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
643 // Returns the register classes for the source arguments of a VOP[12C]
644 // instruction for the given SrcVTs.
645 class getInRC32 <list<ValueType> SrcVT> {
646 list<DAGOperand> ret = [
647 getVOPSrc0ForVT<SrcVT[0]>.ret,
648 getVOPSrc1ForVT<SrcVT[1]>.ret
652 // Returns the register class to use for sources of VOP3 instructions for the
654 class getVOP3SrcForVT<ValueType VT> {
655 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
658 // Returns the register classes for the source arguments of a VOP3
659 // instruction for the given SrcVTs.
660 class getInRC64 <list<ValueType> SrcVT> {
661 list<DAGOperand> ret = [
662 getVOP3SrcForVT<SrcVT[0]>.ret,
663 getVOP3SrcForVT<SrcVT[1]>.ret,
664 getVOP3SrcForVT<SrcVT[2]>.ret
668 // Returns 1 if the source arguments have modifiers, 0 if they do not.
669 class hasModifiers<ValueType SrcVT> {
670 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
671 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
674 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
675 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
676 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
677 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
681 // Returns the input arguments for VOP3 instructions for the given SrcVT.
682 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
683 RegisterOperand Src2RC, int NumSrcArgs,
687 !if (!eq(NumSrcArgs, 1),
688 !if (!eq(HasModifiers, 1),
689 // VOP1 with modifiers
690 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
691 ClampMod:$clamp, omod:$omod)
693 // VOP1 without modifiers
696 !if (!eq(NumSrcArgs, 2),
697 !if (!eq(HasModifiers, 1),
698 // VOP 2 with modifiers
699 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
700 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
701 ClampMod:$clamp, omod:$omod)
703 // VOP2 without modifiers
704 (ins Src0RC:$src0, Src1RC:$src1)
706 /* NumSrcArgs == 3 */,
707 !if (!eq(HasModifiers, 1),
708 // VOP3 with modifiers
709 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
710 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
711 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
712 ClampMod:$clamp, omod:$omod)
714 // VOP3 without modifiers
715 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
719 // Returns the assembly string for the inputs and outputs of a VOP[12C]
720 // instruction. This does not add the _e32 suffix, so it can be reused
722 class getAsm32 <int NumSrcArgs> {
723 string src1 = ", $src1";
724 string src2 = ", $src2";
725 string ret = " $dst, $src0"#
726 !if(!eq(NumSrcArgs, 1), "", src1)#
727 !if(!eq(NumSrcArgs, 3), src2, "");
730 // Returns the assembly string for the inputs and outputs of a VOP3
732 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
733 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
734 string src1 = !if(!eq(NumSrcArgs, 1), "",
735 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
736 " $src1_modifiers,"));
737 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
739 !if(!eq(HasModifiers, 0),
740 getAsm32<NumSrcArgs>.ret,
741 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
745 class VOPProfile <list<ValueType> _ArgVT> {
747 field list<ValueType> ArgVT = _ArgVT;
749 field ValueType DstVT = ArgVT[0];
750 field ValueType Src0VT = ArgVT[1];
751 field ValueType Src1VT = ArgVT[2];
752 field ValueType Src2VT = ArgVT[3];
753 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
754 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
755 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
756 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
757 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
758 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
760 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
761 field bit HasModifiers = hasModifiers<Src0VT>.ret;
763 field dag Outs = (outs DstRC:$dst);
765 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
766 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
769 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
770 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
773 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
774 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
775 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
776 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
777 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
778 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
779 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
780 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
781 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
783 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
784 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
785 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
786 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
787 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
788 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
789 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
790 let Src0RC32 = VCSrc_32;
793 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
794 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
795 let Asm64 = " $dst, $src0_modifiers, $src1";
798 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
799 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
800 let Asm64 = " $dst, $src0_modifiers, $src1";
803 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
804 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
806 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
807 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
808 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
809 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
812 class VOP <string opName> {
813 string OpName = opName;
816 class VOP2_REV <string revOp, bit isOrig> {
817 string RevOp = revOp;
821 class AtomicNoRet <string noRetOp, bit isRet> {
822 string NoRetOp = noRetOp;
826 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
827 VOP1Common <outs, ins, "", pattern>,
829 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
833 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
835 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
837 def _si : VOP1<op.SI, outs, ins, asm, []>,
838 SIMCInstr <opName#"_e32", SISubtarget.SI>;
839 def _vi : VOP1<op.VI, outs, ins, asm, []>,
840 SIMCInstr <opName#"_e32", SISubtarget.VI>;
843 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
844 VOP2Common <outs, ins, "", pattern>,
846 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
850 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
851 string opName, string revOpSI> {
852 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
853 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
855 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
856 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
857 SIMCInstr <opName#"_e32", SISubtarget.SI>;
860 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
861 string opName, string revOpSI, string revOpVI> {
862 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
863 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
865 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
866 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
867 SIMCInstr <opName#"_e32", SISubtarget.SI>;
868 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
869 VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
870 SIMCInstr <opName#"_e32", SISubtarget.VI>;
873 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
875 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
876 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
877 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
878 bits<2> omod = !if(HasModifiers, ?, 0);
879 bits<1> clamp = !if(HasModifiers, ?, 0);
880 bits<9> src1 = !if(HasSrc1, ?, 0);
881 bits<9> src2 = !if(HasSrc2, ?, 0);
884 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
885 VOP3Common <outs, ins, "", pattern>,
887 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
891 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
892 VOP3Common <outs, ins, asm, []>,
894 SIMCInstr<opName#"_e64", SISubtarget.SI>;
896 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
897 VOP3Common <outs, ins, asm, []>,
899 SIMCInstr <opName#"_e64", SISubtarget.VI>;
901 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
902 string opName, int NumSrcArgs, bit HasMods = 1> {
904 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
906 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
907 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
908 !if(!eq(NumSrcArgs, 2), 0, 1),
910 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
911 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
912 !if(!eq(NumSrcArgs, 2), 0, 1),
916 // VOP3_m without source modifiers
917 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
918 string opName, int NumSrcArgs, bit HasMods = 1> {
920 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
922 let src0_modifiers = 0,
924 src2_modifiers = 0 in {
925 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
926 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
930 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
931 list<dag> pattern, string opName, bit HasMods = 1> {
933 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
935 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
936 VOP3DisableFields<0, 0, HasMods>;
938 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
939 VOP3DisableFields<0, 0, HasMods>;
942 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
943 list<dag> pattern, string opName, string revOpSI, string revOpVI,
944 bit HasMods = 1, bit UseFullOp = 0> {
946 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
947 VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>;
949 def _si : VOP3_Real_si <op.SI3,
950 outs, ins, asm, opName>,
951 VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
952 VOP3DisableFields<1, 0, HasMods>;
954 def _vi : VOP3_Real_vi <op.VI3,
955 outs, ins, asm, opName>,
956 VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
957 VOP3DisableFields<1, 0, HasMods>;
960 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
961 list<dag> pattern, string opName, string revOp,
962 bit HasMods = 1, bit UseFullOp = 0> {
963 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
964 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
966 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
967 // can write it into any SGPR. We currently don't use the carry out,
968 // so for now hardcode it to VCC as well.
969 let sdst = SIOperand.VCC, Defs = [VCC] in {
970 def _si : VOP3b <op.SI3, outs, ins, asm, []>,
971 VOP3DisableFields<1, 0, HasMods>,
972 SIMCInstr<opName#"_e64", SISubtarget.SI>,
973 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
975 // TODO: Do we need this VI variant here?
976 /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, []>,
977 VOP3DisableFields<1, 0, HasMods>,
978 SIMCInstr<opName#"_e64", SISubtarget.VI>,
979 VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
980 } // End sdst = SIOperand.VCC, Defs = [VCC]
983 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
984 list<dag> pattern, string opName,
985 bit HasMods, bit defExec> {
987 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
989 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
990 VOP3DisableFields<1, 0, HasMods> {
991 let Defs = !if(defExec, [EXEC], []);
994 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
995 VOP3DisableFields<1, 0, HasMods> {
996 let Defs = !if(defExec, [EXEC], []);
1000 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1001 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1002 string asm, list<dag> pattern = []> {
1003 let isPseudo = 1 in {
1004 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1005 SIMCInstr<opName, SISubtarget.NONE>;
1008 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1009 SIMCInstr <opName, SISubtarget.SI>;
1011 def _vi : VOP3Common <outs, ins, asm, []>,
1013 VOP3DisableFields <1, 0, 0>,
1014 SIMCInstr <opName, SISubtarget.VI>;
1017 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1018 dag ins32, string asm32, list<dag> pat32,
1019 dag ins64, string asm64, list<dag> pat64,
1022 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1024 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1027 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1028 SDPatternOperator node = null_frag> : VOP1_Helper <
1030 P.Ins32, P.Asm32, [],
1033 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1034 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1035 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1039 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1040 SDPatternOperator node = null_frag> {
1042 def _e32 : VOP1 <op.SI, P.Outs, P.Ins32, opName#P.Asm32, []>,
1045 def _e64 : VOP3Common <P.Outs, P.Ins64, opName#P.Asm64,
1047 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1048 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1049 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])>,
1052 VOP3DisableFields<0, 0, P.HasModifiers>;
1055 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1056 dag ins32, string asm32, list<dag> pat32,
1057 dag ins64, string asm64, list<dag> pat64,
1058 string revOpSI, string revOpVI, bit HasMods> {
1059 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>;
1061 defm _e64 : VOP3_2_m <op,
1062 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods
1066 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1067 SDPatternOperator node = null_frag,
1068 string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper <
1070 P.Ins32, P.Asm32, [],
1074 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1075 i1:$clamp, i32:$omod)),
1076 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1077 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1078 revOpSI, revOpVI, P.HasModifiers
1081 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1082 dag ins32, string asm32, list<dag> pat32,
1083 dag ins64, string asm64, list<dag> pat64,
1084 string revOp, bit HasMods> {
1086 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>;
1088 defm _e64 : VOP3b_2_m <op,
1089 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1093 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1094 SDPatternOperator node = null_frag,
1095 string revOp = opName> : VOP2b_Helper <
1097 P.Ins32, P.Asm32, [],
1101 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1102 i1:$clamp, i32:$omod)),
1103 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1104 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1105 revOp, P.HasModifiers
1108 // A VOP2 instruction that is VOP3-only on VI.
1109 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1110 dag ins32, string asm32, list<dag> pat32,
1111 dag ins64, string asm64, list<dag> pat64,
1112 string revOpSI, string revOpVI, bit HasMods> {
1113 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOpSI>;
1115 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1116 revOpSI, revOpVI, HasMods>;
1119 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1120 SDPatternOperator node = null_frag,
1121 string revOpSI = opName, string revOpVI = revOpSI>
1124 P.Ins32, P.Asm32, [],
1128 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1129 i1:$clamp, i32:$omod)),
1130 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1131 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1132 revOpSI, revOpVI, P.HasModifiers
1135 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1136 VOPCCommon <ins, "", pattern>,
1138 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1142 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1143 string opName, bit DefExec> {
1144 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1146 def _si : VOPC<op.SI, ins, asm, []>,
1147 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1148 let Defs = !if(DefExec, [EXEC], []);
1151 def _vi : VOPC<op.VI, ins, asm, []>,
1152 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1153 let Defs = !if(DefExec, [EXEC], []);
1157 multiclass VOPC_Helper <vopc op, string opName,
1158 dag ins32, string asm32, list<dag> pat32,
1159 dag out64, dag ins64, string asm64, list<dag> pat64,
1160 bit HasMods, bit DefExec> {
1161 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1163 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1164 opName, HasMods, DefExec>;
1167 multiclass VOPCInst <vopc op, string opName,
1168 VOPProfile P, PatLeaf cond = COND_NULL,
1169 bit DefExec = 0> : VOPC_Helper <
1171 P.Ins32, P.Asm32, [],
1172 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1175 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1176 i1:$clamp, i32:$omod)),
1177 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1179 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1180 P.HasModifiers, DefExec
1183 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1184 bit DefExec = 0> : VOPC_Helper <
1186 P.Ins32, P.Asm32, [],
1187 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1190 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1191 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1192 P.HasModifiers, DefExec
1196 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1197 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1199 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1200 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1202 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1203 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1205 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1206 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1209 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1210 PatLeaf cond = COND_NULL>
1211 : VOPCInst <op, opName, P, cond, 1>;
1213 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1214 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1216 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1217 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1219 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1220 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1222 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1223 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1225 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1226 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1227 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1230 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1231 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1233 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1234 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1236 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1237 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1239 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1240 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1242 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1243 SDPatternOperator node = null_frag> : VOP3_Helper <
1244 op, opName, P.Outs, P.Ins64, P.Asm64,
1245 !if(!eq(P.NumSrcArgs, 3),
1248 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1249 i1:$clamp, i32:$omod)),
1250 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1251 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1252 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1254 !if(!eq(P.NumSrcArgs, 2),
1257 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1258 i1:$clamp, i32:$omod)),
1259 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1260 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1261 /* P.NumSrcArgs == 1 */,
1264 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1265 i1:$clamp, i32:$omod))))],
1266 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1267 P.NumSrcArgs, P.HasModifiers
1270 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1271 string opName, list<dag> pattern> :
1273 op, (outs vrc:$vdst, SReg_64:$sdst),
1274 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1275 InputModsNoDefault:$src1_modifiers, arc:$src1,
1276 InputModsNoDefault:$src2_modifiers, arc:$src2,
1277 ClampMod:$clamp, omod:$omod),
1278 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1279 opName, opName, 1, 1
1282 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1283 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1285 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1286 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1289 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1290 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1291 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1292 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1293 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1294 i32:$src1_modifiers, P.Src1VT:$src1,
1295 i32:$src2_modifiers, P.Src2VT:$src2,
1299 //===----------------------------------------------------------------------===//
1300 // Interpolation opcodes
1301 //===----------------------------------------------------------------------===//
1303 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1304 VINTRPCommon <outs, ins, "", pattern>,
1305 SIMCInstr<opName, SISubtarget.NONE> {
1309 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1311 VINTRPCommon <outs, ins, asm, []>,
1313 SIMCInstr<opName, SISubtarget.SI>;
1315 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1317 VINTRPCommon <outs, ins, asm, []>,
1319 SIMCInstr<opName, SISubtarget.VI>;
1321 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1322 string disableEncoding = "", string constraints = "",
1323 list<dag> pattern = []> {
1324 let DisableEncoding = disableEncoding,
1325 Constraints = constraints in {
1326 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1328 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1330 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1334 //===----------------------------------------------------------------------===//
1335 // Vector I/O classes
1336 //===----------------------------------------------------------------------===//
1338 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1339 DS <outs, ins, "", pattern>,
1340 SIMCInstr <opName, SISubtarget.NONE> {
1344 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1345 DS <outs, ins, asm, []>,
1347 SIMCInstr <opName, SISubtarget.SI>;
1349 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1350 DS <outs, ins, asm, []>,
1352 SIMCInstr <opName, SISubtarget.VI>;
1354 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1355 DS <outs, ins, asm, []>,
1357 SIMCInstr <opName, SISubtarget.SI> {
1359 // Single load interpret the 2 i8imm operands as a single i16 offset.
1361 let offset0 = offset{7-0};
1362 let offset1 = offset{15-8};
1365 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1366 DS <outs, ins, asm, []>,
1368 SIMCInstr <opName, SISubtarget.VI> {
1370 // Single load interpret the 2 i8imm operands as a single i16 offset.
1372 let offset0 = offset{7-0};
1373 let offset1 = offset{15-8};
1376 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1378 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1379 def "" : DS_Pseudo <opName, outs, ins, pat>;
1381 let data0 = 0, data1 = 0 in {
1382 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1383 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1388 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1392 (outs regClass:$vdst),
1393 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1394 asm#" $vdst, $addr"#"$offset"#" [M0]",
1397 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1399 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1400 def "" : DS_Pseudo <opName, outs, ins, pat>;
1402 let data0 = 0, data1 = 0 in {
1403 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1404 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1409 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1413 (outs regClass:$vdst),
1414 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1416 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1419 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1420 string asm, list<dag> pat> {
1421 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1422 def "" : DS_Pseudo <opName, outs, ins, pat>;
1424 let data1 = 0, vdst = 0 in {
1425 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1426 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1431 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1436 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1437 asm#" $addr, $data0"#"$offset"#" [M0]",
1440 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1441 string asm, list<dag> pat> {
1442 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1443 def "" : DS_Pseudo <opName, outs, ins, pat>;
1446 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1447 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1452 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1457 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1458 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1459 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1462 // 1 address, 1 data.
1463 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1464 string asm, list<dag> pat, string noRetOp> {
1465 let mayLoad = 1, mayStore = 1,
1466 hasPostISelHook = 1 // Adjusted to no return version.
1468 def "" : DS_Pseudo <opName, outs, ins, pat>,
1469 AtomicNoRet<noRetOp, 1>;
1472 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1473 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1478 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1479 string noRetOp = ""> : DS_1A1D_RET_m <
1482 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1483 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1485 // 1 address, 2 data.
1486 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1487 string asm, list<dag> pat, string noRetOp> {
1488 let mayLoad = 1, mayStore = 1,
1489 hasPostISelHook = 1 // Adjusted to no return version.
1491 def "" : DS_Pseudo <opName, outs, ins, pat>,
1492 AtomicNoRet<noRetOp, 1>;
1494 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1495 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1499 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1500 string noRetOp = ""> : DS_1A2D_RET_m <
1503 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1504 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1507 // 1 address, 2 data.
1508 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1509 string asm, list<dag> pat, string noRetOp> {
1510 let mayLoad = 1, mayStore = 1 in {
1511 def "" : DS_Pseudo <opName, outs, ins, pat>,
1512 AtomicNoRet<noRetOp, 0>;
1514 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1515 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1519 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1520 string noRetOp = asm> : DS_1A2D_NORET_m <
1523 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1524 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1527 // 1 address, 1 data.
1528 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1529 string asm, list<dag> pat, string noRetOp> {
1530 let mayLoad = 1, mayStore = 1 in {
1531 def "" : DS_Pseudo <opName, outs, ins, pat>,
1532 AtomicNoRet<noRetOp, 0>;
1535 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1536 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1541 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1542 string noRetOp = asm> : DS_1A1D_NORET_m <
1545 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1546 asm#" $addr, $data0"#"$offset"#" [M0]",
1549 //===----------------------------------------------------------------------===//
1551 //===----------------------------------------------------------------------===//
1553 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1554 MTBUF <outs, ins, "", pattern>,
1555 SIMCInstr<opName, SISubtarget.NONE> {
1559 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1561 MTBUF <outs, ins, asm, []>,
1563 SIMCInstr<opName, SISubtarget.SI>;
1565 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1566 MTBUF <outs, ins, asm, []>,
1568 SIMCInstr <opName, SISubtarget.VI>;
1570 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1571 list<dag> pattern> {
1573 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1575 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1577 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1581 let mayStore = 1, mayLoad = 0 in {
1583 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1584 RegisterClass regClass> : MTBUF_m <
1586 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1587 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1588 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1589 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1590 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1593 } // mayStore = 1, mayLoad = 0
1595 let mayLoad = 1, mayStore = 0 in {
1597 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1598 RegisterClass regClass> : MTBUF_m <
1599 op, opName, (outs regClass:$dst),
1600 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1601 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1602 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1603 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1604 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1607 } // mayLoad = 1, mayStore = 0
1609 //===----------------------------------------------------------------------===//
1611 //===----------------------------------------------------------------------===//
1613 class mubuf <bits<7> si, bits<7> vi = si> {
1614 field bits<7> SI = si;
1615 field bits<7> VI = vi;
1618 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1619 bit IsAddr64 = is_addr64;
1620 string OpName = NAME # suffix;
1623 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1624 MUBUF <outs, ins, "", pattern>,
1625 SIMCInstr<opName, SISubtarget.NONE> {
1628 // dummy fields, so that we can use let statements around multiclasses
1638 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1640 MUBUF <outs, ins, asm, []>,
1642 SIMCInstr<opName, SISubtarget.SI> {
1646 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1648 MUBUF <outs, ins, asm, []>,
1650 SIMCInstr<opName, SISubtarget.VI> {
1654 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1655 list<dag> pattern> {
1657 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1658 MUBUFAddr64Table <0>;
1661 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1664 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1667 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1668 dag ins, string asm, list<dag> pattern> {
1670 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1671 MUBUFAddr64Table <1>;
1674 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1677 // There is no VI version. If the pseudo is selected, it should be lowered
1678 // for VI appropriately.
1681 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1682 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1686 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1687 string asm, list<dag> pattern, bit is_return> {
1689 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1690 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1691 AtomicNoRet<NAME#"_OFFSET", is_return>;
1693 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1695 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1698 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1702 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1703 string asm, list<dag> pattern, bit is_return> {
1705 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1706 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1707 AtomicNoRet<NAME#"_ADDR64", is_return>;
1709 let offen = 0, idxen = 0, addr64 = 1, tfe = 0, soffset = 128 in {
1710 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1713 // There is no VI version. If the pseudo is selected, it should be lowered
1714 // for VI appropriately.
1717 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1718 ValueType vt, SDPatternOperator atomic> {
1720 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1722 // No return variants
1725 defm _ADDR64 : MUBUFAtomicAddr64_m <
1726 op, name#"_addr64", (outs),
1727 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1728 mbuf_offset:$offset, slc:$slc),
1729 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", [], 0
1732 defm _OFFSET : MUBUFAtomicOffset_m <
1733 op, name#"_offset", (outs),
1734 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1735 SCSrc_32:$soffset, slc:$slc),
1736 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1740 // Variant that return values
1741 let glc = 1, Constraints = "$vdata = $vdata_in",
1742 DisableEncoding = "$vdata_in" in {
1744 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1745 op, name#"_rtn_addr64", (outs rc:$vdata),
1746 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1747 mbuf_offset:$offset, slc:$slc),
1748 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1750 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1751 i1:$slc), vt:$vdata_in))], 1
1754 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1755 op, name#"_rtn_offset", (outs rc:$vdata),
1756 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1757 SCSrc_32:$soffset, slc:$slc),
1758 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1760 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1761 i1:$slc), vt:$vdata_in))], 1
1766 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1769 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1770 ValueType load_vt = i32,
1771 SDPatternOperator ld = null_frag> {
1773 let mayLoad = 1, mayStore = 0 in {
1774 let offen = 0, idxen = 0, vaddr = 0 in {
1775 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1776 (ins SReg_128:$srsrc,
1777 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1778 slc:$slc, tfe:$tfe),
1779 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1780 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1781 i32:$soffset, i16:$offset,
1782 i1:$glc, i1:$slc, i1:$tfe)))]>;
1785 let offen = 1, idxen = 0 in {
1786 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1787 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1788 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1790 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1793 let offen = 0, idxen = 1 in {
1794 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1795 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1796 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1797 slc:$slc, tfe:$tfe),
1798 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1801 let offen = 1, idxen = 1 in {
1802 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1803 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1804 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1805 name#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1808 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1809 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1810 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1811 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1812 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1813 i64:$vaddr, i16:$offset)))]>;
1818 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1819 ValueType store_vt, SDPatternOperator st> {
1820 let mayLoad = 0, mayStore = 1 in {
1821 defm : MUBUF_m <op, name, (outs),
1822 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1823 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1825 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1826 "$glc"#"$slc"#"$tfe", []>;
1828 let offen = 0, idxen = 0, vaddr = 0 in {
1829 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1830 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1831 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1832 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1833 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1834 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1835 } // offen = 0, idxen = 0, vaddr = 0
1837 let offen = 1, idxen = 0 in {
1838 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1839 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1840 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1841 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1842 "$glc"#"$slc"#"$tfe", []>;
1843 } // end offen = 1, idxen = 0
1845 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0,
1846 soffset = 128 /* ZERO */ in {
1847 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1848 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1849 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1850 [(st store_vt:$vdata,
1851 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>;
1853 } // End mayLoad = 0, mayStore = 1
1856 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1857 FLAT <op, (outs regClass:$data),
1858 (ins VReg_64:$addr),
1859 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1866 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1867 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1868 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1880 class MIMG_Mask <string op, int channels> {
1882 int Channels = channels;
1885 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1886 RegisterClass dst_rc,
1887 RegisterClass src_rc> : MIMG <
1889 (outs dst_rc:$vdata),
1890 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1891 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1893 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1894 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1899 let hasPostISelHook = 1;
1902 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1903 RegisterClass dst_rc,
1905 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1906 MIMG_Mask<asm#"_V1", channels>;
1907 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1908 MIMG_Mask<asm#"_V2", channels>;
1909 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1910 MIMG_Mask<asm#"_V4", channels>;
1913 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1914 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1915 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1916 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1917 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1920 class MIMG_Sampler_Helper <bits<7> op, string asm,
1921 RegisterClass dst_rc,
1922 RegisterClass src_rc> : MIMG <
1924 (outs dst_rc:$vdata),
1925 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1926 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1927 SReg_256:$srsrc, SReg_128:$ssamp),
1928 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1929 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1933 let hasPostISelHook = 1;
1936 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1937 RegisterClass dst_rc,
1939 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32>,
1940 MIMG_Mask<asm#"_V1", channels>;
1941 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1942 MIMG_Mask<asm#"_V2", channels>;
1943 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1944 MIMG_Mask<asm#"_V4", channels>;
1945 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1946 MIMG_Mask<asm#"_V8", channels>;
1947 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1948 MIMG_Mask<asm#"_V16", channels>;
1951 multiclass MIMG_Sampler <bits<7> op, string asm> {
1952 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1>;
1953 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1954 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1955 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1958 class MIMG_Gather_Helper <bits<7> op, string asm,
1959 RegisterClass dst_rc,
1960 RegisterClass src_rc> : MIMG <
1962 (outs dst_rc:$vdata),
1963 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1964 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1965 SReg_256:$srsrc, SReg_128:$ssamp),
1966 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1967 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1972 // DMASK was repurposed for GATHER4. 4 components are always
1973 // returned and DMASK works like a swizzle - it selects
1974 // the component to fetch. The only useful DMASK values are
1975 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1976 // (red,red,red,red) etc.) The ISA document doesn't mention
1978 // Therefore, disable all code which updates DMASK by setting these two:
1980 let hasPostISelHook = 0;
1983 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1984 RegisterClass dst_rc,
1986 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32>,
1987 MIMG_Mask<asm#"_V1", channels>;
1988 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1989 MIMG_Mask<asm#"_V2", channels>;
1990 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1991 MIMG_Mask<asm#"_V4", channels>;
1992 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1993 MIMG_Mask<asm#"_V8", channels>;
1994 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1995 MIMG_Mask<asm#"_V16", channels>;
1998 multiclass MIMG_Gather <bits<7> op, string asm> {
1999 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1>;
2000 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
2001 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
2002 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
2005 //===----------------------------------------------------------------------===//
2006 // Vector instruction mappings
2007 //===----------------------------------------------------------------------===//
2009 // Maps an opcode in e32 form to its e64 equivalent
2010 def getVOPe64 : InstrMapping {
2011 let FilterClass = "VOP";
2012 let RowFields = ["OpName"];
2013 let ColFields = ["Size"];
2015 let ValueCols = [["8"]];
2018 // Maps an opcode in e64 form to its e32 equivalent
2019 def getVOPe32 : InstrMapping {
2020 let FilterClass = "VOP";
2021 let RowFields = ["OpName"];
2022 let ColFields = ["Size"];
2024 let ValueCols = [["4"]];
2027 // Maps an original opcode to its commuted version
2028 def getCommuteRev : InstrMapping {
2029 let FilterClass = "VOP2_REV";
2030 let RowFields = ["RevOp"];
2031 let ColFields = ["IsOrig"];
2033 let ValueCols = [["0"]];
2036 def getMaskedMIMGOp : InstrMapping {
2037 let FilterClass = "MIMG_Mask";
2038 let RowFields = ["Op"];
2039 let ColFields = ["Channels"];
2041 let ValueCols = [["1"], ["2"], ["3"] ];
2044 // Maps an commuted opcode to its original version
2045 def getCommuteOrig : InstrMapping {
2046 let FilterClass = "VOP2_REV";
2047 let RowFields = ["RevOp"];
2048 let ColFields = ["IsOrig"];
2050 let ValueCols = [["1"]];
2053 def getMCOpcodeGen : InstrMapping {
2054 let FilterClass = "SIMCInstr";
2055 let RowFields = ["PseudoInstr"];
2056 let ColFields = ["Subtarget"];
2057 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2058 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2061 def getAddr64Inst : InstrMapping {
2062 let FilterClass = "MUBUFAddr64Table";
2063 let RowFields = ["OpName"];
2064 let ColFields = ["IsAddr64"];
2066 let ValueCols = [["1"]];
2069 // Maps an atomic opcode to its version with a return value.
2070 def getAtomicRetOp : InstrMapping {
2071 let FilterClass = "AtomicNoRet";
2072 let RowFields = ["NoRetOp"];
2073 let ColFields = ["IsRet"];
2075 let ValueCols = [["1"]];
2078 // Maps an atomic opcode to its returnless version.
2079 def getAtomicNoRetOp : InstrMapping {
2080 let FilterClass = "AtomicNoRet";
2081 let RowFields = ["NoRetOp"];
2082 let ColFields = ["IsRet"];
2084 let ValueCols = [["0"]];
2087 include "SIInstructions.td"
2088 include "CIInstructions.td"
2089 include "VIInstructions.td"