1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
14 class vopc <bits<8> si> : vop {
15 field bits<8> SI = si;
17 field bits<9> SI3 = {0, si{7-0}};
20 class vop1 <bits<8> si> : vop {
21 field bits<8> SI = si;
23 field bits<9> SI3 = {1, 1, si{6-0}};
26 class vop2 <bits<6> si> : vop {
27 field bits<6> SI = si;
29 field bits<9> SI3 = {1, 0, 0, si{5-0}};
32 class vop3 <bits<9> si> : vop {
33 field bits<9> SI3 = si;
36 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
37 // in AMDGPUMCInstLower.h
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
47 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
48 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
49 [SDNPMayLoad, SDNPMemOperand]
52 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
54 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
55 SDTCisVT<1, iAny>, // vdata(VGPR)
56 SDTCisVT<2, i32>, // num_channels(imm)
57 SDTCisVT<3, i32>, // vaddr(VGPR)
58 SDTCisVT<4, i32>, // soffset(SGPR)
59 SDTCisVT<5, i32>, // inst_offset(imm)
60 SDTCisVT<6, i32>, // dfmt(imm)
61 SDTCisVT<7, i32>, // nfmt(imm)
62 SDTCisVT<8, i32>, // offen(imm)
63 SDTCisVT<9, i32>, // idxen(imm)
64 SDTCisVT<10, i32>, // glc(imm)
65 SDTCisVT<11, i32>, // slc(imm)
66 SDTCisVT<12, i32> // tfe(imm)
68 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
71 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
72 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
76 class SDSample<string opcode> : SDNode <opcode,
77 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
78 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
81 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
82 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
83 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
84 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
86 def SIconstdata_ptr : SDNode<
87 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
90 // Transformation function, extract the lower 32bit of a 64bit immediate
91 def LO32 : SDNodeXForm<imm, [{
92 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
95 def LO32f : SDNodeXForm<fpimm, [{
96 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
97 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
100 // Transformation function, extract the upper 32bit of a 64bit immediate
101 def HI32 : SDNodeXForm<imm, [{
102 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
105 def HI32f : SDNodeXForm<fpimm, [{
106 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
107 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
110 def IMM8bitDWORD : PatLeaf <(imm),
111 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
114 def as_dword_i32imm : SDNodeXForm<imm, [{
115 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
118 def as_i1imm : SDNodeXForm<imm, [{
119 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
122 def as_i8imm : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
126 def as_i16imm : SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
130 def as_i32imm: SDNodeXForm<imm, [{
131 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
134 def IMM8bit : PatLeaf <(imm),
135 [{return isUInt<8>(N->getZExtValue());}]
138 def IMM12bit : PatLeaf <(imm),
139 [{return isUInt<12>(N->getZExtValue());}]
142 def IMM16bit : PatLeaf <(imm),
143 [{return isUInt<16>(N->getZExtValue());}]
146 def IMM32bit : PatLeaf <(imm),
147 [{return isUInt<32>(N->getZExtValue());}]
150 def mubuf_vaddr_offset : PatFrag<
151 (ops node:$ptr, node:$offset, node:$imm_offset),
152 (add (add node:$ptr, node:$offset), node:$imm_offset)
155 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
156 return isInlineImmediate(N);
159 class SGPRImm <dag frag> : PatLeaf<frag, [{
160 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
161 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
164 const SIRegisterInfo *SIRI =
165 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
166 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
168 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
175 //===----------------------------------------------------------------------===//
177 //===----------------------------------------------------------------------===//
179 def FRAMEri32 : Operand<iPTR> {
180 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
183 def sopp_brtarget : Operand<OtherVT> {
184 let EncoderMethod = "getSOPPBrEncoding";
185 let OperandType = "OPERAND_PCREL";
188 include "SIInstrFormats.td"
190 let OperandType = "OPERAND_IMMEDIATE" in {
192 def offen : Operand<i1> {
193 let PrintMethod = "printOffen";
195 def idxen : Operand<i1> {
196 let PrintMethod = "printIdxen";
198 def addr64 : Operand<i1> {
199 let PrintMethod = "printAddr64";
201 def mbuf_offset : Operand<i16> {
202 let PrintMethod = "printMBUFOffset";
204 def ds_offset : Operand<i16> {
205 let PrintMethod = "printDSOffset";
207 def ds_offset0 : Operand<i8> {
208 let PrintMethod = "printDSOffset0";
210 def ds_offset1 : Operand<i8> {
211 let PrintMethod = "printDSOffset1";
213 def glc : Operand <i1> {
214 let PrintMethod = "printGLC";
216 def slc : Operand <i1> {
217 let PrintMethod = "printSLC";
219 def tfe : Operand <i1> {
220 let PrintMethod = "printTFE";
223 def omod : Operand <i32> {
224 let PrintMethod = "printOModSI";
227 def ClampMod : Operand <i1> {
228 let PrintMethod = "printClampSI";
231 } // End OperandType = "OPERAND_IMMEDIATE"
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
237 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
238 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
240 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
241 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
242 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
243 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
244 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
245 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
247 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
248 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
249 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
251 //===----------------------------------------------------------------------===//
252 // SI assembler operands
253 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
275 // SI Instruction multiclass helpers.
277 // Instructions with _32 take 32-bit operands.
278 // Instructions with _64 take 64-bit operands.
280 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
281 // encoding is the standard encoding, but instruction that make use of
282 // any of the instruction modifiers must use the 64-bit encoding.
284 // Instructions with _e32 use the 32-bit encoding.
285 // Instructions with _e64 use the 64-bit encoding.
287 //===----------------------------------------------------------------------===//
289 class SIMCInstr <string pseudo, int subtarget> {
290 string PseudoInstr = pseudo;
291 int Subtarget = subtarget;
294 //===----------------------------------------------------------------------===//
296 //===----------------------------------------------------------------------===//
298 class EXPCommon : InstSI<
300 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
301 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
302 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
311 let isPseudo = 1 in {
312 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
315 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
322 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
323 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
324 opName#" $dst, $src0", pattern
327 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
328 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
329 opName#" $dst, $src0", pattern
332 // 64-bit input, 32-bit output.
333 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
334 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
335 opName#" $dst, $src0", pattern
338 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
339 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
340 opName#" $dst, $src0, $src1", pattern
343 class SOP2_SELECT_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
344 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
345 opName#" $dst, $src0, $src1 [$scc]", pattern
348 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
349 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
350 opName#" $dst, $src0, $src1", pattern
353 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
354 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
355 opName#" $dst, $src0, $src1", pattern
359 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
360 string opName, PatLeaf cond> : SOPC <
361 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
362 opName#" $dst, $src0, $src1", []>;
364 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
365 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
367 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
368 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
370 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
371 op, (outs SReg_32:$dst), (ins i16imm:$src0),
372 opName#" $dst, $src0", pattern
375 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
376 op, (outs SReg_64:$dst), (ins i16imm:$src0),
377 opName#" $dst, $src0", pattern
380 //===----------------------------------------------------------------------===//
382 //===----------------------------------------------------------------------===//
384 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
385 SMRD <outs, ins, "", pattern>,
386 SIMCInstr<opName, SISubtarget.NONE> {
390 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
392 SMRD <outs, ins, asm, []>,
394 SIMCInstr<opName, SISubtarget.SI>;
396 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
397 string asm, list<dag> pattern> {
399 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
401 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
405 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
406 RegisterClass dstClass> {
408 op, opName#"_IMM", 1, (outs dstClass:$dst),
409 (ins baseClass:$sbase, u32imm:$offset),
410 opName#" $dst, $sbase, $offset", []
413 defm _SGPR : SMRD_m <
414 op, opName#"_SGPR", 0, (outs dstClass:$dst),
415 (ins baseClass:$sbase, SReg_32:$soff),
416 opName#" $dst, $sbase, $soff", []
420 //===----------------------------------------------------------------------===//
421 // Vector ALU classes
422 //===----------------------------------------------------------------------===//
424 // This must always be right before the operand being input modified.
425 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
426 let PrintMethod = "printOperandAndMods";
428 def InputModsNoDefault : Operand <i32> {
429 let PrintMethod = "printOperandAndMods";
432 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
434 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
435 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
439 // Returns the register class to use for the destination of VOP[123C]
440 // instructions for the given VT.
441 class getVALUDstForVT<ValueType VT> {
442 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
445 // Returns the register class to use for source 0 of VOP[12C]
446 // instructions for the given VT.
447 class getVOPSrc0ForVT<ValueType VT> {
448 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
451 // Returns the register class to use for source 1 of VOP[12C] for the
453 class getVOPSrc1ForVT<ValueType VT> {
454 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
457 // Returns the register classes for the source arguments of a VOP[12C]
458 // instruction for the given SrcVTs.
459 class getInRC32 <list<ValueType> SrcVT> {
460 list<RegisterClass> ret = [
461 getVOPSrc0ForVT<SrcVT[0]>.ret,
462 getVOPSrc1ForVT<SrcVT[1]>.ret
466 // Returns the register class to use for sources of VOP3 instructions for the
468 class getVOP3SrcForVT<ValueType VT> {
469 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
472 // Returns the register classes for the source arguments of a VOP3
473 // instruction for the given SrcVTs.
474 class getInRC64 <list<ValueType> SrcVT> {
475 list<RegisterClass> ret = [
476 getVOP3SrcForVT<SrcVT[0]>.ret,
477 getVOP3SrcForVT<SrcVT[1]>.ret,
478 getVOP3SrcForVT<SrcVT[2]>.ret
482 // Returns 1 if the source arguments have modifiers, 0 if they do not.
483 class hasModifiers<ValueType SrcVT> {
484 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
485 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
488 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
489 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
490 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
491 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
495 // Returns the input arguments for VOP3 instructions for the given SrcVT.
496 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
497 RegisterClass Src2RC, int NumSrcArgs,
501 !if (!eq(NumSrcArgs, 1),
502 !if (!eq(HasModifiers, 1),
503 // VOP1 with modifiers
504 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
505 ClampMod:$clamp, omod:$omod)
507 // VOP1 without modifiers
510 !if (!eq(NumSrcArgs, 2),
511 !if (!eq(HasModifiers, 1),
512 // VOP 2 with modifiers
513 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
514 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
515 ClampMod:$clamp, omod:$omod)
517 // VOP2 without modifiers
518 (ins Src0RC:$src0, Src1RC:$src1)
520 /* NumSrcArgs == 3 */,
521 !if (!eq(HasModifiers, 1),
522 // VOP3 with modifiers
523 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
524 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
525 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
526 ClampMod:$clamp, omod:$omod)
528 // VOP3 without modifiers
529 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
533 // Returns the assembly string for the inputs and outputs of a VOP[12C]
534 // instruction. This does not add the _e32 suffix, so it can be reused
536 class getAsm32 <int NumSrcArgs> {
537 string src1 = ", $src1";
538 string src2 = ", $src2";
539 string ret = " $dst, $src0"#
540 !if(!eq(NumSrcArgs, 1), "", src1)#
541 !if(!eq(NumSrcArgs, 3), src2, "");
544 // Returns the assembly string for the inputs and outputs of a VOP3
546 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
547 string src0 = "$src0_modifiers,";
548 string src1 = !if(!eq(NumSrcArgs, 1), "",
549 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
550 " $src1_modifiers,"));
551 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
553 !if(!eq(HasModifiers, 0),
554 getAsm32<NumSrcArgs>.ret,
555 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
559 class VOPProfile <list<ValueType> _ArgVT> {
561 field list<ValueType> ArgVT = _ArgVT;
563 field ValueType DstVT = ArgVT[0];
564 field ValueType Src0VT = ArgVT[1];
565 field ValueType Src1VT = ArgVT[2];
566 field ValueType Src2VT = ArgVT[3];
567 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
568 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
569 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
570 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
571 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
572 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
574 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
575 field bit HasModifiers = hasModifiers<Src0VT>.ret;
577 field dag Outs = (outs DstRC:$dst);
579 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
580 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
583 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
584 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
587 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
588 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
589 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
590 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
591 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
592 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
593 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
594 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
595 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
597 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
598 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
599 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
600 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
601 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
602 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
603 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
604 let Src0RC32 = VCSrc_32;
606 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
607 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
609 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
610 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
611 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
612 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
615 class VOP <string opName> {
616 string OpName = opName;
619 class VOP2_REV <string revOp, bit isOrig> {
620 string RevOp = revOp;
624 class AtomicNoRet <string noRetOp, bit isRet> {
625 string NoRetOp = noRetOp;
629 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
630 VOP1Common <outs, ins, "", pattern>,
631 SIMCInstr<opName, SISubtarget.NONE> {
635 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
637 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
639 def _si : VOP1<op.SI, outs, ins, asm, []>,
640 SIMCInstr <opName, SISubtarget.SI>;
643 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
645 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
646 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
647 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
648 bits<2> omod = !if(HasModifiers, ?, 0);
649 bits<1> clamp = !if(HasModifiers, ?, 0);
650 bits<9> src1 = !if(HasSrc1, ?, 0);
651 bits<9> src2 = !if(HasSrc2, ?, 0);
654 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
655 VOP3Common <outs, ins, "", pattern>,
657 SIMCInstr<opName, SISubtarget.NONE> {
661 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
662 VOP3 <op, outs, ins, asm, []>,
663 SIMCInstr<opName, SISubtarget.SI>;
665 multiclass VOP3_m <vop3 op, dag outs, dag ins, string asm, list<dag> pattern,
666 string opName, int NumSrcArgs, bit HasMods = 1> {
668 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
670 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
671 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
672 !if(!eq(NumSrcArgs, 2), 0, 1),
677 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
678 list<dag> pattern, string opName, bit HasMods = 1> {
680 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
682 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
683 VOP3DisableFields<0, 0, HasMods>;
686 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
687 list<dag> pattern, string opName, string revOp,
688 bit HasMods = 1, bit UseFullOp = 0> {
690 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
691 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
693 def _si : VOP3_Real_si <op.SI3,
694 outs, ins, asm, opName>,
695 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
696 VOP3DisableFields<1, 0, HasMods>;
699 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
700 list<dag> pattern, string opName, string revOp,
701 bit HasMods = 1, bit UseFullOp = 0> {
702 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
703 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
705 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
706 // can write it into any SGPR. We currently don't use the carry out,
707 // so for now hardcode it to VCC as well.
708 let sdst = SIOperand.VCC, Defs = [VCC] in {
709 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
710 VOP3DisableFields<1, 0, HasMods>,
711 SIMCInstr<opName, SISubtarget.SI>,
712 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
713 } // End sdst = SIOperand.VCC, Defs = [VCC]
716 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
717 list<dag> pattern, string opName,
718 bit HasMods, bit defExec> {
720 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
722 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
723 VOP3DisableFields<1, 0, HasMods> {
724 let Defs = !if(defExec, [EXEC], []);
728 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
729 dag ins32, string asm32, list<dag> pat32,
730 dag ins64, string asm64, list<dag> pat64,
733 def _e32 : VOP1 <op.SI, outs, ins32, opName#asm32, pat32>, VOP<opName>;
735 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
738 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
739 SDPatternOperator node = null_frag> : VOP1_Helper <
741 P.Ins32, P.Asm32, [],
744 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
745 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
746 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
750 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
751 list<dag> pattern, string revOp> :
752 VOP2 <op, outs, ins, opName#asm, pattern>,
754 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
756 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
757 dag ins32, string asm32, list<dag> pat32,
758 dag ins64, string asm64, list<dag> pat64,
759 string revOp, bit HasMods> {
760 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
762 defm _e64 : VOP3_2_m <op,
763 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
767 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
768 SDPatternOperator node = null_frag,
769 string revOp = opName> : VOP2_Helper <
771 P.Ins32, P.Asm32, [],
775 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
776 i1:$clamp, i32:$omod)),
777 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
778 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
779 revOp, P.HasModifiers
782 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
783 dag ins32, string asm32, list<dag> pat32,
784 dag ins64, string asm64, list<dag> pat64,
785 string revOp, bit HasMods> {
787 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
789 defm _e64 : VOP3b_2_m <op,
790 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
794 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
795 SDPatternOperator node = null_frag,
796 string revOp = opName> : VOP2b_Helper <
798 P.Ins32, P.Asm32, [],
802 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
803 i1:$clamp, i32:$omod)),
804 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
805 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
806 revOp, P.HasModifiers
809 multiclass VOPC_Helper <vopc op, string opName,
810 dag ins32, string asm32, list<dag> pat32,
811 dag out64, dag ins64, string asm64, list<dag> pat64,
812 bit HasMods, bit DefExec> {
813 def _e32 : VOPC <op.SI, ins32, opName#asm32, pat32>, VOP <opName> {
814 let Defs = !if(DefExec, [EXEC], []);
817 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
821 multiclass VOPCInst <vopc op, string opName,
822 VOPProfile P, PatLeaf cond = COND_NULL,
823 bit DefExec = 0> : VOPC_Helper <
825 P.Ins32, P.Asm32, [],
826 (outs SReg_64:$dst), P.Ins64, P.Asm64,
829 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
830 i1:$clamp, i32:$omod)),
831 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
833 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
834 P.HasModifiers, DefExec
837 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
838 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
840 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
841 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
843 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
844 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
846 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
847 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
850 multiclass VOPCX <vopc op, string opName, VOPProfile P,
851 PatLeaf cond = COND_NULL>
852 : VOPCInst <op, opName, P, cond, 1>;
854 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
855 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
857 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
858 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
860 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
861 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
863 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
864 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
866 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
867 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
868 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
871 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
872 SDPatternOperator node = null_frag> : VOP3_Helper <
873 op, opName, P.Outs, P.Ins64, P.Asm64,
874 !if(!eq(P.NumSrcArgs, 3),
877 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
878 i1:$clamp, i32:$omod)),
879 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
880 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
881 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
883 !if(!eq(P.NumSrcArgs, 2),
886 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
887 i1:$clamp, i32:$omod)),
888 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
889 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
890 /* P.NumSrcArgs == 1 */,
893 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
894 i1:$clamp, i32:$omod))))],
895 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
896 P.NumSrcArgs, P.HasModifiers
899 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterClass arc,
900 string opName, list<dag> pattern> :
902 op, (outs vrc:$vdst, SReg_64:$sdst),
903 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
904 InputModsNoDefault:$src1_modifiers, arc:$src1,
905 InputModsNoDefault:$src2_modifiers, arc:$src2,
906 ClampMod:$clamp, omod:$omod),
907 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
911 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
912 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
914 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
915 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
918 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
919 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
920 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
921 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
922 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
923 i32:$src1_modifiers, P.Src1VT:$src1,
924 i32:$src2_modifiers, P.Src2VT:$src2,
928 //===----------------------------------------------------------------------===//
929 // Vector I/O classes
930 //===----------------------------------------------------------------------===//
932 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
933 DS <op, outs, ins, asm, pat> {
936 // Single load interpret the 2 i8imm operands as a single i16 offset.
937 let offset0 = offset{7-0};
938 let offset1 = offset{15-8};
941 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
943 (outs regClass:$vdst),
944 (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset),
945 asm#" $vdst, $addr"#"$offset"#" [M0]",
953 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
955 (outs regClass:$vdst),
956 (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1),
957 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
965 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
968 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset),
969 asm#" $addr, $data0"#"$offset"#" [M0]",
977 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
980 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
981 ds_offset0:$offset0, ds_offset1:$offset1),
982 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
989 // 1 address, 1 data.
990 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
993 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),
994 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
995 AtomicNoRet<noRetOp, 1> {
1001 let hasPostISelHook = 1; // Adjusted to no return version.
1004 // 1 address, 2 data.
1005 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
1008 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),
1009 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1011 AtomicNoRet<noRetOp, 1> {
1015 let hasPostISelHook = 1; // Adjusted to no return version.
1018 // 1 address, 2 data.
1019 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1022 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),
1023 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1025 AtomicNoRet<noRetOp, 0> {
1030 // 1 address, 1 data.
1031 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1034 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),
1035 asm#" $addr, $data0"#"$offset"#" [M0]",
1037 AtomicNoRet<noRetOp, 0> {
1044 //===----------------------------------------------------------------------===//
1046 //===----------------------------------------------------------------------===//
1048 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1049 MTBUF <outs, ins, "", pattern>,
1050 SIMCInstr<opName, SISubtarget.NONE> {
1054 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1056 MTBUF <outs, ins, asm, []>,
1058 SIMCInstr<opName, SISubtarget.SI>;
1060 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1061 list<dag> pattern> {
1063 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1065 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1069 let mayStore = 1, mayLoad = 0 in {
1071 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1072 RegisterClass regClass> : MTBUF_m <
1074 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1075 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1076 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1077 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1078 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1081 } // mayStore = 1, mayLoad = 0
1083 let mayLoad = 1, mayStore = 0 in {
1085 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1086 RegisterClass regClass> : MTBUF_m <
1087 op, opName, (outs regClass:$dst),
1088 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1089 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1090 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1091 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1092 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1095 } // mayLoad = 1, mayStore = 0
1097 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1099 bit IsAddr64 = is_addr64;
1100 string OpName = NAME # suffix;
1103 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1104 : MUBUF <op, outs, ins, asm, pattern> {
1114 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1115 : MUBUF <op, outs, ins, asm, pattern> {
1125 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1126 ValueType vt, SDPatternOperator atomic> {
1128 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1130 // No return variants
1133 def _ADDR64 : MUBUFAtomicAddr64 <
1135 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1136 mbuf_offset:$offset, slc:$slc),
1137 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1138 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1140 def _OFFSET : MUBUFAtomicOffset <
1142 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1143 SSrc_32:$soffset, slc:$slc),
1144 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1145 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1148 // Variant that return values
1149 let glc = 1, Constraints = "$vdata = $vdata_in",
1150 DisableEncoding = "$vdata_in" in {
1152 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1153 op, (outs rc:$vdata),
1154 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1155 mbuf_offset:$offset, slc:$slc),
1156 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1158 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1159 i1:$slc), vt:$vdata_in))]
1160 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1162 def _RTN_OFFSET : MUBUFAtomicOffset <
1163 op, (outs rc:$vdata),
1164 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1165 SSrc_32:$soffset, slc:$slc),
1166 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1168 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1169 i1:$slc), vt:$vdata_in))]
1170 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1174 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1177 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1178 ValueType load_vt = i32,
1179 SDPatternOperator ld = null_frag> {
1181 let lds = 0, mayLoad = 1 in {
1185 let offen = 0, idxen = 0, vaddr = 0 in {
1186 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1187 (ins SReg_128:$srsrc,
1188 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1189 slc:$slc, tfe:$tfe),
1190 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1191 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1192 i32:$soffset, i16:$offset,
1193 i1:$glc, i1:$slc, i1:$tfe)))]>,
1194 MUBUFAddr64Table<0>;
1197 let offen = 1, idxen = 0 in {
1198 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1199 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1200 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1202 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1205 let offen = 0, idxen = 1 in {
1206 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1207 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1208 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1209 slc:$slc, tfe:$tfe),
1210 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1213 let offen = 1, idxen = 1 in {
1214 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1215 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1216 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1217 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1221 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1222 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1223 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1224 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1225 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1226 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1231 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1232 ValueType store_vt, SDPatternOperator st> {
1234 let addr64 = 0, lds = 0 in {
1238 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1239 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1241 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1242 "$glc"#"$slc"#"$tfe",
1246 let offen = 0, idxen = 0, vaddr = 0 in {
1247 def _OFFSET : MUBUF <
1249 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1250 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1251 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1252 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1253 i16:$offset, i1:$glc, i1:$slc,
1255 >, MUBUFAddr64Table<0>;
1256 } // offen = 0, idxen = 0, vaddr = 0
1258 let offen = 1, idxen = 0 in {
1259 def _OFFEN : MUBUF <
1261 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1262 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1263 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1264 "$glc"#"$slc"#"$tfe",
1267 } // end offen = 1, idxen = 0
1269 } // End addr64 = 0, lds = 0
1271 def _ADDR64 : MUBUF <
1273 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1274 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1275 [(st store_vt:$vdata,
1276 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1290 let soffset = 128; // ZERO
1294 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1295 FLAT <op, (outs regClass:$data),
1296 (ins VReg_64:$addr),
1297 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1304 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1305 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1306 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1318 class MIMG_Mask <string op, int channels> {
1320 int Channels = channels;
1323 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1324 RegisterClass dst_rc,
1325 RegisterClass src_rc> : MIMG <
1327 (outs dst_rc:$vdata),
1328 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1329 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1331 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1332 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1337 let hasPostISelHook = 1;
1340 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1341 RegisterClass dst_rc,
1343 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1344 MIMG_Mask<asm#"_V1", channels>;
1345 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1346 MIMG_Mask<asm#"_V2", channels>;
1347 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1348 MIMG_Mask<asm#"_V4", channels>;
1351 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1352 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1353 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1354 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1355 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1358 class MIMG_Sampler_Helper <bits<7> op, string asm,
1359 RegisterClass dst_rc,
1360 RegisterClass src_rc> : MIMG <
1362 (outs dst_rc:$vdata),
1363 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1364 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1365 SReg_256:$srsrc, SReg_128:$ssamp),
1366 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1367 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1371 let hasPostISelHook = 1;
1374 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1375 RegisterClass dst_rc,
1377 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1378 MIMG_Mask<asm#"_V1", channels>;
1379 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1380 MIMG_Mask<asm#"_V2", channels>;
1381 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1382 MIMG_Mask<asm#"_V4", channels>;
1383 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1384 MIMG_Mask<asm#"_V8", channels>;
1385 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1386 MIMG_Mask<asm#"_V16", channels>;
1389 multiclass MIMG_Sampler <bits<7> op, string asm> {
1390 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1391 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1392 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1393 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1396 class MIMG_Gather_Helper <bits<7> op, string asm,
1397 RegisterClass dst_rc,
1398 RegisterClass src_rc> : MIMG <
1400 (outs dst_rc:$vdata),
1401 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1402 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1403 SReg_256:$srsrc, SReg_128:$ssamp),
1404 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1405 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1410 // DMASK was repurposed for GATHER4. 4 components are always
1411 // returned and DMASK works like a swizzle - it selects
1412 // the component to fetch. The only useful DMASK values are
1413 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1414 // (red,red,red,red) etc.) The ISA document doesn't mention
1416 // Therefore, disable all code which updates DMASK by setting these two:
1418 let hasPostISelHook = 0;
1421 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1422 RegisterClass dst_rc,
1424 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1425 MIMG_Mask<asm#"_V1", channels>;
1426 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1427 MIMG_Mask<asm#"_V2", channels>;
1428 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1429 MIMG_Mask<asm#"_V4", channels>;
1430 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1431 MIMG_Mask<asm#"_V8", channels>;
1432 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1433 MIMG_Mask<asm#"_V16", channels>;
1436 multiclass MIMG_Gather <bits<7> op, string asm> {
1437 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1438 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1439 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1440 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1443 //===----------------------------------------------------------------------===//
1444 // Vector instruction mappings
1445 //===----------------------------------------------------------------------===//
1447 // Maps an opcode in e32 form to its e64 equivalent
1448 def getVOPe64 : InstrMapping {
1449 let FilterClass = "VOP";
1450 let RowFields = ["OpName"];
1451 let ColFields = ["Size"];
1453 let ValueCols = [["8"]];
1456 // Maps an opcode in e64 form to its e32 equivalent
1457 def getVOPe32 : InstrMapping {
1458 let FilterClass = "VOP";
1459 let RowFields = ["OpName"];
1460 let ColFields = ["Size"];
1462 let ValueCols = [["4"]];
1465 // Maps an original opcode to its commuted version
1466 def getCommuteRev : InstrMapping {
1467 let FilterClass = "VOP2_REV";
1468 let RowFields = ["RevOp"];
1469 let ColFields = ["IsOrig"];
1471 let ValueCols = [["0"]];
1474 def getMaskedMIMGOp : InstrMapping {
1475 let FilterClass = "MIMG_Mask";
1476 let RowFields = ["Op"];
1477 let ColFields = ["Channels"];
1479 let ValueCols = [["1"], ["2"], ["3"] ];
1482 // Maps an commuted opcode to its original version
1483 def getCommuteOrig : InstrMapping {
1484 let FilterClass = "VOP2_REV";
1485 let RowFields = ["RevOp"];
1486 let ColFields = ["IsOrig"];
1488 let ValueCols = [["1"]];
1491 def isDS : InstrMapping {
1492 let FilterClass = "DS";
1493 let RowFields = ["Inst"];
1494 let ColFields = ["Size"];
1496 let ValueCols = [["8"]];
1499 def getMCOpcode : InstrMapping {
1500 let FilterClass = "SIMCInstr";
1501 let RowFields = ["PseudoInstr"];
1502 let ColFields = ["Subtarget"];
1503 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1504 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1507 def getAddr64Inst : InstrMapping {
1508 let FilterClass = "MUBUFAddr64Table";
1509 let RowFields = ["OpName"];
1510 let ColFields = ["IsAddr64"];
1512 let ValueCols = [["1"]];
1515 // Maps an atomic opcode to its version with a return value.
1516 def getAtomicRetOp : InstrMapping {
1517 let FilterClass = "AtomicNoRet";
1518 let RowFields = ["NoRetOp"];
1519 let ColFields = ["IsRet"];
1521 let ValueCols = [["1"]];
1524 // Maps an atomic opcode to its returnless version.
1525 def getAtomicNoRetOp : InstrMapping {
1526 let FilterClass = "AtomicNoRet";
1527 let RowFields = ["NoRetOp"];
1528 let ColFields = ["IsRet"];
1530 let ValueCols = [["0"]];
1533 include "SIInstructions.td"