1 //===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDTVCCBinaryOp : SDTypeProfile<1, 2, [
14 SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 2>
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 // and operation on 64-bit wide vcc
22 def SIsreg1_and : SDNode<"SIISD::VCC_AND", SDTVCCBinaryOp,
23 [SDNPCommutative, SDNPAssociative]
26 // Special bitcast node for sharing VCC register between VALU and SALU
27 def SIsreg1_bitcast : SDNode<"SIISD::VCC_BITCAST",
28 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
31 // and operation on 64-bit wide vcc
32 def SIvcc_and : SDNode<"SIISD::VCC_AND", SDTVCCBinaryOp,
33 [SDNPCommutative, SDNPAssociative]
36 // Special bitcast node for sharing VCC register between VALU and SALU
37 def SIvcc_bitcast : SDNode<"SIISD::VCC_BITCAST",
38 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
41 // SMRD takes a 64bit memory address and can only add an 32bit offset
42 def SIadd64bit32bit : SDNode<"ISD::ADD",
43 SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i32>]>
46 // Transformation function, extract the lower 32bit of a 64bit immediate
47 def LO32 : SDNodeXForm<imm, [{
48 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
51 // Transformation function, extract the upper 32bit of a 64bit immediate
52 def HI32 : SDNodeXForm<imm, [{
53 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
56 def IMM8bitDWORD : ImmLeaf <
58 return (Imm & ~0x3FC) == 0;
59 }], SDNodeXForm<imm, [{
60 return CurDAG->getTargetConstant(
61 N->getZExtValue() >> 2, MVT::i32);
65 def IMM12bit : ImmLeaf <
67 [{return isUInt<12>(Imm);}]
70 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
71 AMDGPUInst<outs, ins, asm, pattern> {
73 field bits<1> VM_CNT = 0;
74 field bits<1> EXP_CNT = 0;
75 field bits<1> LGKM_CNT = 0;
77 let TSFlags{0} = VM_CNT;
78 let TSFlags{1} = EXP_CNT;
79 let TSFlags{2} = LGKM_CNT;
82 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
83 InstSI <outs, ins, asm, pattern> {
89 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
90 InstSI <outs, ins, asm, pattern> {
96 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
97 let EncoderMethod = "encodeOperand";
98 let MIOperandInfo = opInfo;
101 class GPR4Align <RegisterClass rc> : Operand <vAny> {
102 let EncoderMethod = "GPR4AlignEncode";
103 let MIOperandInfo = (ops rc:$reg);
106 class GPR2Align <RegisterClass rc> : Operand <iPTR> {
107 let EncoderMethod = "GPR2AlignEncode";
108 let MIOperandInfo = (ops rc:$reg);
111 let Uses = [EXEC] in {
115 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
116 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
117 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
132 let Inst{10} = COMPR;
135 let Inst{31-26} = 0x3e;
136 let Inst{39-32} = VSRC0;
137 let Inst{47-40} = VSRC1;
138 let Inst{55-48} = VSRC2;
139 let Inst{63-56} = VSRC3;
144 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
145 Enc64 <outs, ins, asm, pattern> {
160 let Inst{11-8} = DMASK;
161 let Inst{12} = UNORM;
167 let Inst{24-18} = op;
169 let Inst{31-26} = 0x3c;
170 let Inst{39-32} = VADDR;
171 let Inst{47-40} = VDATA;
172 let Inst{52-48} = SRSRC;
173 let Inst{57-53} = SSAMP;
179 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
180 Enc64<outs, ins, asm, pattern> {
196 let Inst{11-0} = OFFSET;
197 let Inst{12} = OFFEN;
198 let Inst{13} = IDXEN;
200 let Inst{15} = ADDR64;
201 let Inst{18-16} = op;
202 let Inst{22-19} = DFMT;
203 let Inst{25-23} = NFMT;
204 let Inst{31-26} = 0x3a; //encoding
205 let Inst{39-32} = VADDR;
206 let Inst{47-40} = VDATA;
207 let Inst{52-48} = SRSRC;
210 let Inst{63-56} = SOFFSET;
215 let neverHasSideEffects = 1;
218 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
219 Enc64<outs, ins, asm, pattern> {
234 let Inst{11-0} = OFFSET;
235 let Inst{12} = OFFEN;
236 let Inst{13} = IDXEN;
238 let Inst{15} = ADDR64;
240 let Inst{24-18} = op;
241 let Inst{31-26} = 0x38; //encoding
242 let Inst{39-32} = VADDR;
243 let Inst{47-40} = VDATA;
244 let Inst{52-48} = SRSRC;
247 let Inst{63-56} = SOFFSET;
252 let neverHasSideEffects = 1;
255 } // End Uses = [EXEC]
257 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
258 list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
264 let Inst{7-0} = OFFSET;
266 let Inst{14-9} = SBASE;
267 let Inst{21-15} = SDST;
268 let Inst{26-22} = op;
269 let Inst{31-27} = 0x18; //encoding
274 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
275 Enc32<outs, ins, asm, pattern> {
280 let Inst{7-0} = SSRC0;
282 let Inst{22-16} = SDST;
283 let Inst{31-23} = 0x17d; //encoding;
287 let hasSideEffects = 0;
290 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
291 Enc32 <outs, ins, asm, pattern> {
297 let Inst{7-0} = SSRC0;
298 let Inst{15-8} = SSRC1;
299 let Inst{22-16} = SDST;
300 let Inst{29-23} = op;
301 let Inst{31-30} = 0x2; // encoding
305 let hasSideEffects = 0;
308 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
309 Enc32<outs, ins, asm, pattern> {
314 let Inst{7-0} = SSRC0;
315 let Inst{15-8} = SSRC1;
316 let Inst{22-16} = op;
317 let Inst{31-23} = 0x17e;
319 let DisableEncoding = "$dst";
322 let hasSideEffects = 0;
325 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
326 Enc32 <outs, ins , asm, pattern> {
331 let Inst{15-0} = SIMM16;
332 let Inst{22-16} = SDST;
333 let Inst{27-23} = op;
334 let Inst{31-28} = 0xb; //encoding
338 let hasSideEffects = 0;
341 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
349 let Inst{15-0} = SIMM16;
350 let Inst{22-16} = op;
351 let Inst{31-23} = 0x17f; // encoding
355 let hasSideEffects = 0;
358 let Uses = [EXEC] in {
360 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
361 Enc32 <outs, ins, asm, pattern> {
368 let Inst{7-0} = VSRC;
369 let Inst{9-8} = ATTRCHAN;
370 let Inst{15-10} = ATTR;
371 let Inst{17-16} = op;
372 let Inst{25-18} = VDST;
373 let Inst{31-26} = 0x32; // encoding
375 let neverHasSideEffects = 1;
380 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
381 Enc32 <outs, ins, asm, pattern> {
386 let Inst{8-0} = SRC0;
388 let Inst{24-17} = VDST;
389 let Inst{31-25} = 0x3f; //encoding
393 let hasSideEffects = 0;
396 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
397 Enc32 <outs, ins, asm, pattern> {
403 let Inst{8-0} = SRC0;
404 let Inst{16-9} = VSRC1;
405 let Inst{24-17} = VDST;
406 let Inst{30-25} = op;
407 let Inst{31} = 0x0; //encoding
411 let hasSideEffects = 0;
414 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
415 Enc64 <outs, ins, asm, pattern> {
426 let Inst{7-0} = VDST;
427 let Inst{10-8} = ABS;
428 let Inst{11} = CLAMP;
429 let Inst{25-17} = op;
430 let Inst{31-26} = 0x34; //encoding
431 let Inst{40-32} = SRC0;
432 let Inst{49-41} = SRC1;
433 let Inst{58-50} = SRC2;
434 let Inst{60-59} = OMOD;
435 let Inst{63-61} = NEG;
439 let hasSideEffects = 0;
442 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
443 Enc64 <outs, ins, asm, pattern> {
453 let Inst{7-0} = VDST;
454 let Inst{14-8} = SDST;
455 let Inst{25-17} = op;
456 let Inst{31-26} = 0x34; //encoding
457 let Inst{40-32} = SRC0;
458 let Inst{49-41} = SRC1;
459 let Inst{58-50} = SRC2;
460 let Inst{60-59} = OMOD;
461 let Inst{63-61} = NEG;
465 let hasSideEffects = 0;
468 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
469 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
474 let Inst{8-0} = SRC0;
475 let Inst{16-9} = VSRC1;
476 let Inst{24-17} = op;
477 let Inst{31-25} = 0x3e;
479 let DisableEncoding = "$dst";
482 let hasSideEffects = 0;
485 } // End Uses = [EXEC]
487 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
489 (outs VReg_128:$vdata),
490 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
491 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
492 GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
499 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
501 (outs regClass:$dst),
502 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
503 i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
504 i1imm:$tfe, SReg_32:$soffset),
511 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
513 (outs regClass:$dst),
514 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
515 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
516 i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
523 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
526 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
527 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
528 GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
535 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
538 (outs dstClass:$dst),
539 (ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
546 (outs dstClass:$dst),
547 (ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
553 include "SIInstrFormats.td"
554 include "SIInstructions.td"