1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
15 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
16 [SDNPMayLoad, SDNPMemOperand]
19 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
21 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
22 SDTCisVT<1, iAny>, // vdata(VGPR)
23 SDTCisVT<2, i32>, // num_channels(imm)
24 SDTCisVT<3, i32>, // vaddr(VGPR)
25 SDTCisVT<4, i32>, // soffset(SGPR)
26 SDTCisVT<5, i32>, // inst_offset(imm)
27 SDTCisVT<6, i32>, // dfmt(imm)
28 SDTCisVT<7, i32>, // nfmt(imm)
29 SDTCisVT<8, i32>, // offen(imm)
30 SDTCisVT<9, i32>, // idxen(imm)
31 SDTCisVT<10, i32>, // glc(imm)
32 SDTCisVT<11, i32>, // slc(imm)
33 SDTCisVT<12, i32> // tfe(imm)
35 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
38 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
39 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
43 class SDSample<string opcode> : SDNode <opcode,
44 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
45 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
48 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
49 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
50 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
51 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
53 // Transformation function, extract the lower 32bit of a 64bit immediate
54 def LO32 : SDNodeXForm<imm, [{
55 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
58 def LO32f : SDNodeXForm<fpimm, [{
59 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
60 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
63 // Transformation function, extract the upper 32bit of a 64bit immediate
64 def HI32 : SDNodeXForm<imm, [{
65 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
68 def HI32f : SDNodeXForm<fpimm, [{
69 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
70 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
73 def IMM8bitDWORD : PatLeaf <(imm),
74 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
77 def as_dword_i32imm : SDNodeXForm<imm, [{
78 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
81 def as_i1imm : SDNodeXForm<imm, [{
82 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
85 def as_i8imm : SDNodeXForm<imm, [{
86 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
89 def as_i16imm : SDNodeXForm<imm, [{
90 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
93 def as_i32imm: SDNodeXForm<imm, [{
94 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
97 def IMM8bit : PatLeaf <(imm),
98 [{return isUInt<8>(N->getZExtValue());}]
101 def IMM12bit : PatLeaf <(imm),
102 [{return isUInt<12>(N->getZExtValue());}]
105 def IMM16bit : PatLeaf <(imm),
106 [{return isUInt<16>(N->getZExtValue());}]
109 def IMM32bit : PatLeaf <(imm),
110 [{return isUInt<32>(N->getZExtValue());}]
113 def mubuf_vaddr_offset : PatFrag<
114 (ops node:$ptr, node:$offset, node:$imm_offset),
115 (add (add node:$ptr, node:$offset), node:$imm_offset)
118 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
119 return isInlineImmediate(N);
122 class SGPRImm <dag frag> : PatLeaf<frag, [{
123 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
124 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
127 const SIRegisterInfo *SIRI =
128 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
129 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
131 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
138 def FRAMEri32 : Operand<iPTR> {
139 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
142 //===----------------------------------------------------------------------===//
143 // SI assembler operands
144 //===----------------------------------------------------------------------===//
151 include "SIInstrFormats.td"
153 //===----------------------------------------------------------------------===//
155 // SI Instruction multiclass helpers.
157 // Instructions with _32 take 32-bit operands.
158 // Instructions with _64 take 64-bit operands.
160 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
161 // encoding is the standard encoding, but instruction that make use of
162 // any of the instruction modifiers must use the 64-bit encoding.
164 // Instructions with _e32 use the 32-bit encoding.
165 // Instructions with _e64 use the 64-bit encoding.
167 //===----------------------------------------------------------------------===//
169 //===----------------------------------------------------------------------===//
171 //===----------------------------------------------------------------------===//
173 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
174 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
175 opName#" $dst, $src0", pattern
178 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
179 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
180 opName#" $dst, $src0", pattern
183 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
184 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
185 opName#" $dst, $src0, $src1", pattern
188 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
189 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
190 opName#" $dst, $src0, $src1", pattern
193 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
194 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
195 opName#" $dst, $src0, $src1", pattern
199 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
200 string opName, PatLeaf cond> : SOPC <
201 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
202 opName#" $dst, $src0, $src1", []>;
204 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
205 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
207 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
208 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
210 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
211 op, (outs SReg_32:$dst), (ins i16imm:$src0),
212 opName#" $dst, $src0", pattern
215 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
216 op, (outs SReg_64:$dst), (ins i16imm:$src0),
217 opName#" $dst, $src0", pattern
220 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
221 RegisterClass dstClass> {
223 op, 1, (outs dstClass:$dst),
224 (ins baseClass:$sbase, u32imm:$offset),
225 asm#" $dst, $sbase, $offset", []
229 op, 0, (outs dstClass:$dst),
230 (ins baseClass:$sbase, SReg_32:$soff),
231 asm#" $dst, $sbase, $soff", []
235 //===----------------------------------------------------------------------===//
236 // Vector ALU classes
237 //===----------------------------------------------------------------------===//
239 class VOP <string opName> {
240 string OpName = opName;
243 class VOP2_REV <string revOp, bit isOrig> {
244 string RevOp = revOp;
248 // This must always be right before the operand being input modified.
249 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
250 let PrintMethod = "printOperandAndMods";
253 multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
254 string opName, list<dag> pattern> {
257 op, (outs drc:$dst), (ins src:$src0),
258 opName#"_e32 $dst, $src0", pattern
262 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
264 (ins InputMods:$src0_modifiers, src:$src0, i32imm:$clamp, i32imm:$omod),
265 opName#"_e64 $dst, $src0_modifiers, $clamp, $omod", []
267 let src1 = SIOperand.ZERO;
268 let src2 = SIOperand.ZERO;
272 multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern>
273 : VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
275 multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
276 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
278 multiclass VOP1_32_64 <bits<8> op, string opName, list<dag> pattern>
279 : VOP1_Helper <op, VReg_32, VSrc_64, opName, pattern>;
281 multiclass VOP1_64_32 <bits<8> op, string opName, list<dag> pattern>
282 : VOP1_Helper <op, VReg_64, VSrc_32, opName, pattern>;
284 multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
285 string opName, list<dag> pattern, string revOp> {
287 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1),
288 opName#"_e32 $dst, $src0, $src1", pattern
289 >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
292 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
294 (ins InputMods:$src0_modifiers, arc:$src0,
295 InputMods:$src1_modifiers, arc:$src1,
296 i32imm:$clamp, i32imm:$omod),
297 opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", []
298 >, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
299 let src2 = SIOperand.ZERO;
303 multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern,
304 string revOp = opName>
305 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern, revOp>;
307 multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern,
308 string revOp = opName>
309 : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern, revOp>;
311 multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
312 RegisterClass src0_rc, string revOp = opName> {
315 op, (outs VReg_32:$dst), (ins src0_rc:$src0, VReg_32:$src1),
316 opName#"_e32 $dst, $src0, $src1", pattern
317 >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
320 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
322 (ins InputMods: $src0_modifiers, VSrc_32:$src0,
323 InputMods:$src1_modifiers, VSrc_32:$src1,
324 i32imm:$clamp, i32imm:$omod),
325 opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", []
326 >, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
327 let src2 = SIOperand.ZERO;
328 /* the VOP2 variant puts the carry out into VCC, the VOP3 variant
329 can write it into any SGPR. We currently don't use the carry out,
330 so for now hardcode it to VCC as well */
331 let sdst = SIOperand.VCC;
335 multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
336 string opName, ValueType vt, PatLeaf cond> {
339 op, (ins arc:$src0, vrc:$src1),
340 opName#"_e32 $dst, $src0, $src1", []
344 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
346 (ins InputMods:$src0_modifiers, arc:$src0,
347 InputMods:$src1_modifiers, arc:$src1,
348 InstFlag:$clamp, InstFlag:$omod),
349 opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod",
350 !if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>,
351 [(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
354 let src2 = SIOperand.ZERO;
355 let src2_modifiers = 0;
359 multiclass VOPC_32 <bits<8> op, string opName,
360 ValueType vt = untyped, PatLeaf cond = COND_NULL>
361 : VOPC_Helper <op, VReg_32, VSrc_32, opName, vt, cond>;
363 multiclass VOPC_64 <bits<8> op, string opName,
364 ValueType vt = untyped, PatLeaf cond = COND_NULL>
365 : VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>;
367 class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
368 op, (outs VReg_32:$dst),
369 (ins InputMods: $src0_modifiers, VSrc_32:$src0, InputMods:$src1_modifiers,
370 VSrc_32:$src1, InputMods:$src2_modifiers, VSrc_32:$src2,
371 InstFlag:$clamp, InstFlag:$omod),
372 opName#" $dst, $src0_modifiers, $src1, $src2, $clamp, $omod", pattern
375 class VOP3_64_Shift <bits <9> op, string opName, list<dag> pattern> : VOP3 <
376 op, (outs VReg_64:$dst),
377 (ins VSrc_64:$src0, VSrc_32:$src1),
378 opName#" $dst, $src0, $src1", pattern
381 let src2 = SIOperand.ZERO;
382 let src0_modifiers = 0;
387 class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
388 op, (outs VReg_64:$dst),
389 (ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
390 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
391 opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
394 //===----------------------------------------------------------------------===//
395 // Vector I/O classes
396 //===----------------------------------------------------------------------===//
398 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
399 DS <op, outs, ins, asm, pat> {
402 // Single load interpret the 2 i8imm operands as a single i16 offset.
403 let offset0 = offset{7-0};
404 let offset1 = offset{15-8};
407 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
409 (outs regClass:$vdst),
410 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
411 asm#" $vdst, $addr, $offset, [M0]",
419 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
421 (outs regClass:$vdst),
422 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
423 asm#" $gds, $vdst, $addr, $offset0, $offset1, [M0]",
431 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
434 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
435 asm#" $addr, $data0, $offset [M0]",
443 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
446 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u8imm:$offset0, u8imm:$offset1),
447 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
454 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
457 (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, u16imm:$offset),
458 asm#" $vdst, $addr, $data0, $offset, [M0]",
466 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
469 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
470 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
471 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
472 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
473 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
479 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
481 let lds = 0, mayLoad = 1 in {
485 let offen = 0, idxen = 0 in {
486 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
487 (ins SReg_128:$srsrc, VReg_32:$vaddr,
488 u16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
489 i1imm:$slc, i1imm:$tfe),
490 asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
493 let offen = 1, idxen = 0, offset = 0 in {
494 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
495 (ins SReg_128:$srsrc, VReg_32:$vaddr,
496 SSrc_32:$soffset, i1imm:$glc, i1imm:$slc,
498 asm#" $vdata, $srsrc + $vaddr + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
501 let offen = 0, idxen = 1 in {
502 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
503 (ins SReg_128:$srsrc, VReg_32:$vaddr,
504 u16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
505 i1imm:$slc, i1imm:$tfe),
506 asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
509 let offen = 1, idxen = 1 in {
510 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
511 (ins SReg_128:$srsrc, VReg_64:$vaddr,
512 SSrc_32:$soffset, i1imm:$glc,
513 i1imm:$slc, i1imm:$tfe),
514 asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
518 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
519 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
520 (ins SReg_128:$srsrc, VReg_64:$vaddr, u16imm:$offset),
521 asm#" $vdata, $srsrc + $vaddr + $offset", []>;
526 class MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
527 MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
529 name#" $vdata, $srsrc + $vaddr + $offset",
543 let soffset = 128; // ZERO
546 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
548 (outs regClass:$dst),
549 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
550 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
551 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
552 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
553 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
559 class MIMG_Mask <string op, int channels> {
561 int Channels = channels;
564 class MIMG_NoSampler_Helper <bits<7> op, string asm,
565 RegisterClass dst_rc,
566 RegisterClass src_rc> : MIMG <
568 (outs dst_rc:$vdata),
569 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
570 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
572 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
573 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
578 let hasPostISelHook = 1;
581 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
582 RegisterClass dst_rc,
584 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
585 MIMG_Mask<asm#"_V1", channels>;
586 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
587 MIMG_Mask<asm#"_V2", channels>;
588 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
589 MIMG_Mask<asm#"_V4", channels>;
592 multiclass MIMG_NoSampler <bits<7> op, string asm> {
593 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
594 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
595 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
596 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
599 class MIMG_Sampler_Helper <bits<7> op, string asm,
600 RegisterClass dst_rc,
601 RegisterClass src_rc> : MIMG <
603 (outs dst_rc:$vdata),
604 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
605 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
606 SReg_256:$srsrc, SReg_128:$ssamp),
607 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
608 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
612 let hasPostISelHook = 1;
615 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
616 RegisterClass dst_rc,
618 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
619 MIMG_Mask<asm#"_V1", channels>;
620 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
621 MIMG_Mask<asm#"_V2", channels>;
622 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
623 MIMG_Mask<asm#"_V4", channels>;
624 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
625 MIMG_Mask<asm#"_V8", channels>;
626 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
627 MIMG_Mask<asm#"_V16", channels>;
630 multiclass MIMG_Sampler <bits<7> op, string asm> {
631 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
632 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
633 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
634 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
637 //===----------------------------------------------------------------------===//
638 // Vector instruction mappings
639 //===----------------------------------------------------------------------===//
641 // Maps an opcode in e32 form to its e64 equivalent
642 def getVOPe64 : InstrMapping {
643 let FilterClass = "VOP";
644 let RowFields = ["OpName"];
645 let ColFields = ["Size"];
647 let ValueCols = [["8"]];
650 // Maps an original opcode to its commuted version
651 def getCommuteRev : InstrMapping {
652 let FilterClass = "VOP2_REV";
653 let RowFields = ["RevOp"];
654 let ColFields = ["IsOrig"];
656 let ValueCols = [["0"]];
659 def getMaskedMIMGOp : InstrMapping {
660 let FilterClass = "MIMG_Mask";
661 let RowFields = ["Op"];
662 let ColFields = ["Channels"];
664 let ValueCols = [["1"], ["2"], ["3"] ];
667 // Maps an commuted opcode to its original version
668 def getCommuteOrig : InstrMapping {
669 let FilterClass = "VOP2_REV";
670 let RowFields = ["RevOp"];
671 let ColFields = ["IsOrig"];
673 let ValueCols = [["1"]];
676 def isDS : InstrMapping {
677 let FilterClass = "DS";
678 let RowFields = ["Inst"];
679 let ColFields = ["Size"];
681 let ValueCols = [["8"]];
684 include "SIInstructions.td"