1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def gds : Operand <i1> {
268 let PrintMethod = "printGDS";
270 def glc : Operand <i1> {
271 let PrintMethod = "printGLC";
273 def slc : Operand <i1> {
274 let PrintMethod = "printSLC";
276 def tfe : Operand <i1> {
277 let PrintMethod = "printTFE";
280 def omod : Operand <i32> {
281 let PrintMethod = "printOModSI";
284 def ClampMod : Operand <i1> {
285 let PrintMethod = "printClampSI";
288 } // End OperandType = "OPERAND_IMMEDIATE"
290 //===----------------------------------------------------------------------===//
292 //===----------------------------------------------------------------------===//
294 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
295 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
297 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
298 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
299 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
300 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
301 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
302 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
304 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
305 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
306 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
307 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
309 //===----------------------------------------------------------------------===//
310 // SI assembler operands
311 //===----------------------------------------------------------------------===//
331 //===----------------------------------------------------------------------===//
333 // SI Instruction multiclass helpers.
335 // Instructions with _32 take 32-bit operands.
336 // Instructions with _64 take 64-bit operands.
338 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
339 // encoding is the standard encoding, but instruction that make use of
340 // any of the instruction modifiers must use the 64-bit encoding.
342 // Instructions with _e32 use the 32-bit encoding.
343 // Instructions with _e64 use the 64-bit encoding.
345 //===----------------------------------------------------------------------===//
347 class SIMCInstr <string pseudo, int subtarget> {
348 string PseudoInstr = pseudo;
349 int Subtarget = subtarget;
352 //===----------------------------------------------------------------------===//
354 //===----------------------------------------------------------------------===//
356 class EXPCommon : InstSI<
358 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
359 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
360 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
369 let isPseudo = 1, isCodeGenOnly = 1 in {
370 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
373 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
375 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
382 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
383 SOP1 <outs, ins, "", pattern>,
384 SIMCInstr<opName, SISubtarget.NONE> {
386 let isCodeGenOnly = 1;
389 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
390 SOP1 <outs, ins, asm, []>,
392 SIMCInstr<opName, SISubtarget.SI>;
394 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
395 SOP1 <outs, ins, asm, []>,
397 SIMCInstr<opName, SISubtarget.VI>;
399 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
402 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
404 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
406 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
410 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
411 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
412 opName#" $dst, $src0", pattern
415 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
416 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
417 opName#" $dst, $src0", pattern
420 // no input, 64-bit output.
421 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
422 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
424 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
429 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
435 // 64-bit input, no output
436 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
437 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
439 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
444 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
450 // 64-bit input, 32-bit output.
451 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
452 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
453 opName#" $dst, $src0", pattern
456 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
457 SOP2<outs, ins, "", pattern>,
458 SIMCInstr<opName, SISubtarget.NONE> {
460 let isCodeGenOnly = 1;
463 // Pseudo instructions have no encodings, but adding this field here allows
465 // let sdst = xxx in {
466 // for multiclasses that include both real and pseudo instructions.
467 field bits<7> sdst = 0;
470 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
471 SOP2<outs, ins, asm, []>,
473 SIMCInstr<opName, SISubtarget.SI>;
475 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
476 SOP2<outs, ins, asm, []>,
478 SIMCInstr<opName, SISubtarget.VI>;
480 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
481 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
482 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
484 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
485 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
486 opName#" $dst, $src0, $src1 [$scc]">;
488 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
489 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
490 opName#" $dst, $src0, $src1 [$scc]">;
493 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
496 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
498 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
500 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
504 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
505 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
506 opName#" $dst, $src0, $src1", pattern
509 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
510 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
511 opName#" $dst, $src0, $src1", pattern
514 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
515 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
516 opName#" $dst, $src0, $src1", pattern
519 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
520 string opName, PatLeaf cond> : SOPC <
521 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
522 opName#" $dst, $src0, $src1", []>;
524 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
525 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
527 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
528 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
530 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
531 SOPK <outs, ins, "", pattern>,
532 SIMCInstr<opName, SISubtarget.NONE> {
534 let isCodeGenOnly = 1;
537 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
538 SOPK <outs, ins, asm, []>,
540 SIMCInstr<opName, SISubtarget.SI>;
542 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
543 SOPK <outs, ins, asm, []>,
545 SIMCInstr<opName, SISubtarget.VI>;
547 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
548 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
551 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
552 opName#" $dst, $src0">;
554 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
555 opName#" $dst, $src0">;
558 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
559 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
560 (ins SReg_32:$src0, u16imm:$src1), pattern>;
562 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
563 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
565 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
566 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
569 //===----------------------------------------------------------------------===//
571 //===----------------------------------------------------------------------===//
573 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
574 SMRD <outs, ins, "", pattern>,
575 SIMCInstr<opName, SISubtarget.NONE> {
577 let isCodeGenOnly = 1;
580 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
582 SMRD <outs, ins, asm, []>,
584 SIMCInstr<opName, SISubtarget.SI>;
586 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
588 SMRD <outs, ins, asm, []>,
590 SIMCInstr<opName, SISubtarget.VI>;
592 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
593 string asm, list<dag> pattern> {
595 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
597 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
599 // glc is only applicable to scalar stores, which are not yet
602 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
606 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
607 RegisterClass dstClass> {
609 op, opName#"_IMM", 1, (outs dstClass:$dst),
610 (ins baseClass:$sbase, u32imm:$offset),
611 opName#" $dst, $sbase, $offset", []
614 defm _SGPR : SMRD_m <
615 op, opName#"_SGPR", 0, (outs dstClass:$dst),
616 (ins baseClass:$sbase, SReg_32:$soff),
617 opName#" $dst, $sbase, $soff", []
621 //===----------------------------------------------------------------------===//
622 // Vector ALU classes
623 //===----------------------------------------------------------------------===//
625 // This must always be right before the operand being input modified.
626 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
627 let PrintMethod = "printOperandAndMods";
629 def InputModsNoDefault : Operand <i32> {
630 let PrintMethod = "printOperandAndMods";
633 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
635 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
636 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
640 // Returns the register class to use for the destination of VOP[123C]
641 // instructions for the given VT.
642 class getVALUDstForVT<ValueType VT> {
643 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
644 !if(!eq(VT.Size, 64), VReg_64,
645 SReg_64)); // else VT == i1
648 // Returns the register class to use for source 0 of VOP[12C]
649 // instructions for the given VT.
650 class getVOPSrc0ForVT<ValueType VT> {
651 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
654 // Returns the register class to use for source 1 of VOP[12C] for the
656 class getVOPSrc1ForVT<ValueType VT> {
657 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
660 // Returns the register class to use for sources of VOP3 instructions for the
662 class getVOP3SrcForVT<ValueType VT> {
663 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
666 // Returns 1 if the source arguments have modifiers, 0 if they do not.
667 class hasModifiers<ValueType SrcVT> {
668 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
669 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
672 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
673 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
674 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
675 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
679 // Returns the input arguments for VOP3 instructions for the given SrcVT.
680 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
681 RegisterOperand Src2RC, int NumSrcArgs,
685 !if (!eq(NumSrcArgs, 1),
686 !if (!eq(HasModifiers, 1),
687 // VOP1 with modifiers
688 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
689 ClampMod:$clamp, omod:$omod)
691 // VOP1 without modifiers
694 !if (!eq(NumSrcArgs, 2),
695 !if (!eq(HasModifiers, 1),
696 // VOP 2 with modifiers
697 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
698 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
699 ClampMod:$clamp, omod:$omod)
701 // VOP2 without modifiers
702 (ins Src0RC:$src0, Src1RC:$src1)
704 /* NumSrcArgs == 3 */,
705 !if (!eq(HasModifiers, 1),
706 // VOP3 with modifiers
707 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
708 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
709 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
710 ClampMod:$clamp, omod:$omod)
712 // VOP3 without modifiers
713 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
717 // Returns the assembly string for the inputs and outputs of a VOP[12C]
718 // instruction. This does not add the _e32 suffix, so it can be reused
720 class getAsm32 <int NumSrcArgs> {
721 string src1 = ", $src1";
722 string src2 = ", $src2";
723 string ret = " $dst, $src0"#
724 !if(!eq(NumSrcArgs, 1), "", src1)#
725 !if(!eq(NumSrcArgs, 3), src2, "");
728 // Returns the assembly string for the inputs and outputs of a VOP3
730 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
731 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
732 string src1 = !if(!eq(NumSrcArgs, 1), "",
733 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
734 " $src1_modifiers,"));
735 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
737 !if(!eq(HasModifiers, 0),
738 getAsm32<NumSrcArgs>.ret,
739 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
743 class VOPProfile <list<ValueType> _ArgVT> {
745 field list<ValueType> ArgVT = _ArgVT;
747 field ValueType DstVT = ArgVT[0];
748 field ValueType Src0VT = ArgVT[1];
749 field ValueType Src1VT = ArgVT[2];
750 field ValueType Src2VT = ArgVT[3];
751 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
752 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
753 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
754 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
755 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
756 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
758 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
759 field bit HasModifiers = hasModifiers<Src0VT>.ret;
761 field dag Outs = (outs DstRC:$dst);
763 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
764 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
767 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
768 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
771 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
772 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
773 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
774 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
775 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
776 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
777 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
778 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
779 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
781 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
782 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
783 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
784 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
785 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
786 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
787 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
788 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
789 let Src0RC32 = VCSrc_32;
792 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
793 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
794 let Asm64 = " $dst, $src0_modifiers, $src1";
797 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
798 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
799 let Asm64 = " $dst, $src0_modifiers, $src1";
802 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
803 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
804 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
806 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
807 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
808 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
809 field string Asm = " $dst, $src0, $vsrc1, $src2";
811 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
812 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
813 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
816 class VOP <string opName> {
817 string OpName = opName;
820 class VOP2_REV <string revOp, bit isOrig> {
821 string RevOp = revOp;
825 class AtomicNoRet <string noRetOp, bit isRet> {
826 string NoRetOp = noRetOp;
830 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
831 VOP1Common <outs, ins, "", pattern>,
833 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
835 let isCodeGenOnly = 1;
841 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
843 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
845 def _si : VOP1<op.SI, outs, ins, asm, []>,
846 SIMCInstr <opName#"_e32", SISubtarget.SI>;
847 def _vi : VOP1<op.VI, outs, ins, asm, []>,
848 SIMCInstr <opName#"_e32", SISubtarget.VI>;
851 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
853 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
855 def _si : VOP1<op.SI, outs, ins, asm, []>,
856 SIMCInstr <opName#"_e32", SISubtarget.SI>;
857 // No VI instruction. This class is for SI only.
860 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
861 VOP2Common <outs, ins, "", pattern>,
863 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
865 let isCodeGenOnly = 1;
868 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
869 string opName, string revOp> {
870 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
871 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
873 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
874 SIMCInstr <opName#"_e32", SISubtarget.SI>;
877 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
878 string opName, string revOp> {
879 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
880 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
882 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
883 SIMCInstr <opName#"_e32", SISubtarget.SI>;
884 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
885 SIMCInstr <opName#"_e32", SISubtarget.VI>;
888 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
890 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
891 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
892 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
893 bits<2> omod = !if(HasModifiers, ?, 0);
894 bits<1> clamp = !if(HasModifiers, ?, 0);
895 bits<9> src1 = !if(HasSrc1, ?, 0);
896 bits<9> src2 = !if(HasSrc2, ?, 0);
899 class VOP3DisableModFields <bit HasSrc0Mods,
902 bit HasOutputMods = 0> {
903 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
904 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
905 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
906 bits<2> omod = !if(HasOutputMods, ?, 0);
907 bits<1> clamp = !if(HasOutputMods, ?, 0);
910 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
911 VOP3Common <outs, ins, "", pattern>,
913 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
915 let isCodeGenOnly = 1;
918 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
919 VOP3Common <outs, ins, asm, []>,
921 SIMCInstr<opName#"_e64", SISubtarget.SI>;
923 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
924 VOP3Common <outs, ins, asm, []>,
926 SIMCInstr <opName#"_e64", SISubtarget.VI>;
928 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
929 VOP3Common <outs, ins, asm, []>,
931 SIMCInstr<opName#"_e64", SISubtarget.SI>;
933 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
934 VOP3Common <outs, ins, asm, []>,
936 SIMCInstr <opName#"_e64", SISubtarget.VI>;
938 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
939 string opName, int NumSrcArgs, bit HasMods = 1> {
941 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
943 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
944 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
945 !if(!eq(NumSrcArgs, 2), 0, 1),
947 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
948 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
949 !if(!eq(NumSrcArgs, 2), 0, 1),
953 // VOP3_m without source modifiers
954 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
955 string opName, int NumSrcArgs, bit HasMods = 1> {
957 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
959 let src0_modifiers = 0,
964 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
965 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
969 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
970 list<dag> pattern, string opName, bit HasMods = 1> {
972 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
974 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
975 VOP3DisableFields<0, 0, HasMods>;
977 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
978 VOP3DisableFields<0, 0, HasMods>;
981 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
982 list<dag> pattern, string opName, bit HasMods = 1> {
984 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
986 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
987 VOP3DisableFields<0, 0, HasMods>;
988 // No VI instruction. This class is for SI only.
991 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
992 list<dag> pattern, string opName, string revOp,
993 bit HasMods = 1, bit UseFullOp = 0> {
995 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
996 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
998 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
999 VOP3DisableFields<1, 0, HasMods>;
1001 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1002 VOP3DisableFields<1, 0, HasMods>;
1005 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1006 list<dag> pattern, string opName, string revOp,
1007 bit HasMods = 1, bit UseFullOp = 0> {
1009 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1010 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1012 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1013 VOP3DisableFields<1, 0, HasMods>;
1015 // No VI instruction. This class is for SI only.
1018 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1019 // option of implicit vcc use?
1020 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1021 list<dag> pattern, string opName, string revOp,
1022 bit HasMods = 1, bit UseFullOp = 0> {
1023 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1024 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1026 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1027 // can write it into any SGPR. We currently don't use the carry out,
1028 // so for now hardcode it to VCC as well.
1029 let sdst = SIOperand.VCC, Defs = [VCC] in {
1030 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1031 VOP3DisableFields<1, 0, HasMods>;
1033 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1034 VOP3DisableFields<1, 0, HasMods>;
1035 } // End sdst = SIOperand.VCC, Defs = [VCC]
1038 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1039 list<dag> pattern, string opName, string revOp,
1040 bit HasMods = 1, bit UseFullOp = 0> {
1041 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1044 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1045 VOP3DisableFields<1, 1, HasMods>;
1047 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1048 VOP3DisableFields<1, 1, HasMods>;
1051 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1052 list<dag> pattern, string opName,
1053 bit HasMods, bit defExec> {
1055 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1057 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1058 VOP3DisableFields<1, 0, HasMods> {
1059 let Defs = !if(defExec, [EXEC], []);
1062 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1063 VOP3DisableFields<1, 0, HasMods> {
1064 let Defs = !if(defExec, [EXEC], []);
1068 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1069 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1070 string asm, list<dag> pattern = []> {
1071 let isPseudo = 1, isCodeGenOnly = 1 in {
1072 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1073 SIMCInstr<opName, SISubtarget.NONE>;
1076 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1077 SIMCInstr <opName, SISubtarget.SI>;
1079 def _vi : VOP3Common <outs, ins, asm, []>,
1081 VOP3DisableFields <1, 0, 0>,
1082 SIMCInstr <opName, SISubtarget.VI>;
1085 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1086 dag ins32, string asm32, list<dag> pat32,
1087 dag ins64, string asm64, list<dag> pat64,
1090 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1092 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1095 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1096 SDPatternOperator node = null_frag> : VOP1_Helper <
1098 P.Ins32, P.Asm32, [],
1101 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1102 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1103 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1107 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1108 SDPatternOperator node = null_frag> {
1110 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1112 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1114 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1115 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1116 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1117 opName, P.HasModifiers>;
1120 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1121 dag ins32, string asm32, list<dag> pat32,
1122 dag ins64, string asm64, list<dag> pat64,
1123 string revOp, bit HasMods> {
1124 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1126 defm _e64 : VOP3_2_m <op,
1127 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1131 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1132 SDPatternOperator node = null_frag,
1133 string revOp = opName> : VOP2_Helper <
1135 P.Ins32, P.Asm32, [],
1139 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1140 i1:$clamp, i32:$omod)),
1141 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1142 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1143 revOp, P.HasModifiers
1146 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1147 SDPatternOperator node = null_frag,
1148 string revOp = opName> {
1149 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1151 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1154 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1155 i1:$clamp, i32:$omod)),
1156 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1157 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1158 opName, revOp, P.HasModifiers>;
1161 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1162 dag ins32, string asm32, list<dag> pat32,
1163 dag ins64, string asm64, list<dag> pat64,
1164 string revOp, bit HasMods> {
1166 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1168 defm _e64 : VOP3b_2_m <op,
1169 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1173 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1174 SDPatternOperator node = null_frag,
1175 string revOp = opName> : VOP2b_Helper <
1177 P.Ins32, P.Asm32, [],
1181 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1182 i1:$clamp, i32:$omod)),
1183 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1184 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1185 revOp, P.HasModifiers
1188 // A VOP2 instruction that is VOP3-only on VI.
1189 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1190 dag ins32, string asm32, list<dag> pat32,
1191 dag ins64, string asm64, list<dag> pat64,
1192 string revOp, bit HasMods> {
1193 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1195 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1199 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1200 SDPatternOperator node = null_frag,
1201 string revOp = opName>
1204 P.Ins32, P.Asm32, [],
1208 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1209 i1:$clamp, i32:$omod)),
1210 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1211 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1212 revOp, P.HasModifiers
1215 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1217 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1219 let isCodeGenOnly = 0 in {
1220 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1221 !strconcat(opName, VOP_MADK.Asm), []>,
1222 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1225 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1226 !strconcat(opName, VOP_MADK.Asm), []>,
1227 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1229 } // End isCodeGenOnly = 0
1232 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1233 VOPCCommon <ins, "", pattern>,
1235 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1237 let isCodeGenOnly = 1;
1240 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1241 string opName, bit DefExec> {
1242 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1244 def _si : VOPC<op.SI, ins, asm, []>,
1245 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1246 let Defs = !if(DefExec, [EXEC], []);
1249 def _vi : VOPC<op.VI, ins, asm, []>,
1250 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1251 let Defs = !if(DefExec, [EXEC], []);
1255 multiclass VOPC_Helper <vopc op, string opName,
1256 dag ins32, string asm32, list<dag> pat32,
1257 dag out64, dag ins64, string asm64, list<dag> pat64,
1258 bit HasMods, bit DefExec> {
1259 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1261 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1262 opName, HasMods, DefExec>;
1265 // Special case for class instructions which only have modifiers on
1266 // the 1st source operand.
1267 multiclass VOPC_Class_Helper <vopc op, string opName,
1268 dag ins32, string asm32, list<dag> pat32,
1269 dag out64, dag ins64, string asm64, list<dag> pat64,
1270 bit HasMods, bit DefExec> {
1271 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1273 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1274 opName, HasMods, DefExec>,
1275 VOP3DisableModFields<1, 0, 0>;
1278 multiclass VOPCInst <vopc op, string opName,
1279 VOPProfile P, PatLeaf cond = COND_NULL,
1280 bit DefExec = 0> : VOPC_Helper <
1282 P.Ins32, P.Asm32, [],
1283 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1286 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1287 i1:$clamp, i32:$omod)),
1288 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1290 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1291 P.HasModifiers, DefExec
1294 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1295 bit DefExec = 0> : VOPC_Class_Helper <
1297 P.Ins32, P.Asm32, [],
1298 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1301 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1302 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1303 P.HasModifiers, DefExec
1307 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1308 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1310 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1311 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1313 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1314 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1316 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1317 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1320 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1321 PatLeaf cond = COND_NULL>
1322 : VOPCInst <op, opName, P, cond, 1>;
1324 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1325 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1327 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1328 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1330 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1331 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1333 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1334 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1336 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1337 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1338 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1341 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1342 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1344 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1345 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1347 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1348 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1350 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1351 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1353 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1354 SDPatternOperator node = null_frag> : VOP3_Helper <
1355 op, opName, P.Outs, P.Ins64, P.Asm64,
1356 !if(!eq(P.NumSrcArgs, 3),
1359 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1360 i1:$clamp, i32:$omod)),
1361 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1362 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1363 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1365 !if(!eq(P.NumSrcArgs, 2),
1368 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1369 i1:$clamp, i32:$omod)),
1370 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1371 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1372 /* P.NumSrcArgs == 1 */,
1375 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1376 i1:$clamp, i32:$omod))))],
1377 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1378 P.NumSrcArgs, P.HasModifiers
1381 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1382 // only VOP instruction that implicitly reads VCC.
1383 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1385 SDPatternOperator node = null_frag> : VOP3_Helper <
1388 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1389 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1390 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1393 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1395 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1396 i1:$clamp, i32:$omod)),
1397 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1398 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1403 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1404 string opName, list<dag> pattern> :
1406 op, (outs vrc:$vdst, SReg_64:$sdst),
1407 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1408 InputModsNoDefault:$src1_modifiers, arc:$src1,
1409 InputModsNoDefault:$src2_modifiers, arc:$src2,
1410 ClampMod:$clamp, omod:$omod),
1411 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1412 opName, opName, 1, 1
1415 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1416 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1418 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1419 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1422 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1423 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1424 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1425 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1426 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1427 i32:$src1_modifiers, P.Src1VT:$src1,
1428 i32:$src2_modifiers, P.Src2VT:$src2,
1432 //===----------------------------------------------------------------------===//
1433 // Interpolation opcodes
1434 //===----------------------------------------------------------------------===//
1436 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1437 VINTRPCommon <outs, ins, "", pattern>,
1438 SIMCInstr<opName, SISubtarget.NONE> {
1440 let isCodeGenOnly = 1;
1443 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1445 VINTRPCommon <outs, ins, asm, []>,
1447 SIMCInstr<opName, SISubtarget.SI>;
1449 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1451 VINTRPCommon <outs, ins, asm, []>,
1453 SIMCInstr<opName, SISubtarget.VI>;
1455 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1456 string disableEncoding = "", string constraints = "",
1457 list<dag> pattern = []> {
1458 let DisableEncoding = disableEncoding,
1459 Constraints = constraints in {
1460 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1462 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1464 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1468 //===----------------------------------------------------------------------===//
1469 // Vector I/O classes
1470 //===----------------------------------------------------------------------===//
1472 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1473 DS <outs, ins, "", pattern>,
1474 SIMCInstr <opName, SISubtarget.NONE> {
1476 let isCodeGenOnly = 1;
1479 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1480 DS <outs, ins, asm, []>,
1482 SIMCInstr <opName, SISubtarget.SI>;
1484 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1485 DS <outs, ins, asm, []>,
1487 SIMCInstr <opName, SISubtarget.VI>;
1489 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1490 DS_Real_si <op,opName, outs, ins, asm> {
1492 // Single load interpret the 2 i8imm operands as a single i16 offset.
1494 let offset0 = offset{7-0};
1495 let offset1 = offset{15-8};
1498 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1499 DS_Real_vi <op, opName, outs, ins, asm> {
1501 // Single load interpret the 2 i8imm operands as a single i16 offset.
1503 let offset0 = offset{7-0};
1504 let offset1 = offset{15-8};
1507 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1508 dag outs = (outs rc:$vdst),
1509 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1510 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1512 def "" : DS_Pseudo <opName, outs, ins, []>;
1514 let data0 = 0, data1 = 0 in {
1515 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1516 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1520 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1521 dag outs = (outs rc:$vdst),
1522 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1523 gds:$gds, M0Reg:$m0),
1524 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1526 def "" : DS_Pseudo <opName, outs, ins, []>;
1528 let data0 = 0, data1 = 0 in {
1529 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1530 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1534 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1536 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1538 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1540 def "" : DS_Pseudo <opName, outs, ins, []>,
1541 AtomicNoRet<opName, 0>;
1543 let data1 = 0, vdst = 0 in {
1544 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1545 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1549 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1551 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1552 ds_offset0:$offset0, ds_offset1:$offset1, gds:$gds, M0Reg:$m0),
1553 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1555 def "" : DS_Pseudo <opName, outs, ins, []>;
1558 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1559 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1563 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1564 string noRetOp = "",
1565 dag outs = (outs rc:$vdst),
1566 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1568 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1570 def "" : DS_Pseudo <opName, outs, ins, []>,
1571 AtomicNoRet<noRetOp, 1>;
1574 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1575 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1579 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1580 string noRetOp = "", dag ins,
1581 dag outs = (outs rc:$vdst),
1582 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1584 def "" : DS_Pseudo <opName, outs, ins, []>,
1585 AtomicNoRet<noRetOp, 1>;
1587 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1588 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1591 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1592 string noRetOp = "", RegisterClass src = rc> :
1593 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1594 (ins VGPR_32:$addr, src:$data0, src:$data1,
1595 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1598 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1599 string noRetOp = opName,
1601 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1602 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1603 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1605 def "" : DS_Pseudo <opName, outs, ins, []>,
1606 AtomicNoRet<noRetOp, 0>;
1609 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1610 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1614 multiclass DS_0A_RET <bits<8> op, string opName,
1615 dag outs = (outs VGPR_32:$vdst),
1616 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1617 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1619 let mayLoad = 1, mayStore = 1 in {
1620 def "" : DS_Pseudo <opName, outs, ins, []>;
1622 let addr = 0, data0 = 0, data1 = 0 in {
1623 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1624 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1625 } // end addr = 0, data0 = 0, data1 = 0
1626 } // end mayLoad = 1, mayStore = 1
1629 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1630 dag outs = (outs VGPR_32:$vdst),
1631 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1632 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1634 def "" : DS_Pseudo <opName, outs, ins, []>;
1636 let data0 = 0, data1 = 0, gds = 1 in {
1637 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1638 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1639 } // end data0 = 0, data1 = 0, gds = 1
1642 multiclass DS_1A_GDS <bits<8> op, string opName,
1644 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1645 string asm = opName#" $addr gds"> {
1647 def "" : DS_Pseudo <opName, outs, ins, []>;
1649 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1650 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1651 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1652 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1655 multiclass DS_1A <bits<8> op, string opName,
1657 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1658 string asm = opName#" $addr"#"$offset"#"$gds"> {
1660 let mayLoad = 1, mayStore = 1 in {
1661 def "" : DS_Pseudo <opName, outs, ins, []>;
1663 let vdst = 0, data0 = 0, data1 = 0 in {
1664 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1665 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1666 } // let vdst = 0, data0 = 0, data1 = 0
1667 } // end mayLoad = 1, mayStore = 1
1670 //===----------------------------------------------------------------------===//
1672 //===----------------------------------------------------------------------===//
1674 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1675 MTBUF <outs, ins, "", pattern>,
1676 SIMCInstr<opName, SISubtarget.NONE> {
1678 let isCodeGenOnly = 1;
1681 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1683 MTBUF <outs, ins, asm, []>,
1685 SIMCInstr<opName, SISubtarget.SI>;
1687 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1688 MTBUF <outs, ins, asm, []>,
1690 SIMCInstr <opName, SISubtarget.VI>;
1692 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1693 list<dag> pattern> {
1695 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1697 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1699 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1703 let mayStore = 1, mayLoad = 0 in {
1705 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1706 RegisterClass regClass> : MTBUF_m <
1708 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1709 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1710 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1711 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1712 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1715 } // mayStore = 1, mayLoad = 0
1717 let mayLoad = 1, mayStore = 0 in {
1719 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1720 RegisterClass regClass> : MTBUF_m <
1721 op, opName, (outs regClass:$dst),
1722 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1723 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1724 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1725 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1726 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1729 } // mayLoad = 1, mayStore = 0
1731 //===----------------------------------------------------------------------===//
1733 //===----------------------------------------------------------------------===//
1735 class mubuf <bits<7> si, bits<7> vi = si> {
1736 field bits<7> SI = si;
1737 field bits<7> VI = vi;
1740 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1741 bit IsAddr64 = is_addr64;
1742 string OpName = NAME # suffix;
1745 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1746 MUBUF <outs, ins, "", pattern>,
1747 SIMCInstr<opName, SISubtarget.NONE> {
1749 let isCodeGenOnly = 1;
1751 // dummy fields, so that we can use let statements around multiclasses
1761 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1763 MUBUF <outs, ins, asm, []>,
1765 SIMCInstr<opName, SISubtarget.SI> {
1769 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1771 MUBUF <outs, ins, asm, []>,
1773 SIMCInstr<opName, SISubtarget.VI> {
1777 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1778 list<dag> pattern> {
1780 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1781 MUBUFAddr64Table <0>;
1784 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1787 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1790 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1791 dag ins, string asm, list<dag> pattern> {
1793 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1794 MUBUFAddr64Table <1>;
1797 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1800 // There is no VI version. If the pseudo is selected, it should be lowered
1801 // for VI appropriately.
1804 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1805 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1809 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1810 string asm, list<dag> pattern, bit is_return> {
1812 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1813 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1814 AtomicNoRet<NAME#"_OFFSET", is_return>;
1816 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1818 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1821 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1825 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1826 string asm, list<dag> pattern, bit is_return> {
1828 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1829 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1830 AtomicNoRet<NAME#"_ADDR64", is_return>;
1832 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1833 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1836 // There is no VI version. If the pseudo is selected, it should be lowered
1837 // for VI appropriately.
1840 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1841 ValueType vt, SDPatternOperator atomic> {
1843 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1845 // No return variants
1848 defm _ADDR64 : MUBUFAtomicAddr64_m <
1849 op, name#"_addr64", (outs),
1850 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1851 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1852 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1855 defm _OFFSET : MUBUFAtomicOffset_m <
1856 op, name#"_offset", (outs),
1857 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
1859 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1863 // Variant that return values
1864 let glc = 1, Constraints = "$vdata = $vdata_in",
1865 DisableEncoding = "$vdata_in" in {
1867 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1868 op, name#"_rtn_addr64", (outs rc:$vdata),
1869 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1870 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1871 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1873 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1874 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1877 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1878 op, name#"_rtn_offset", (outs rc:$vdata),
1879 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
1880 mbuf_offset:$offset, slc:$slc),
1881 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1883 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1884 i1:$slc), vt:$vdata_in))], 1
1889 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1892 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1893 ValueType load_vt = i32,
1894 SDPatternOperator ld = null_frag> {
1896 let mayLoad = 1, mayStore = 0 in {
1897 let offen = 0, idxen = 0, vaddr = 0 in {
1898 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1899 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
1900 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1901 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1902 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1903 i32:$soffset, i16:$offset,
1904 i1:$glc, i1:$slc, i1:$tfe)))]>;
1907 let offen = 1, idxen = 0 in {
1908 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1909 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1910 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1912 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1915 let offen = 0, idxen = 1 in {
1916 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1917 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1918 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1919 slc:$slc, tfe:$tfe),
1920 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1923 let offen = 1, idxen = 1 in {
1924 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1925 (ins SReg_128:$srsrc, VReg_64:$vaddr, SCSrc_32:$soffset,
1926 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1927 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1930 let offen = 0, idxen = 0 in {
1931 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1932 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1933 SCSrc_32:$soffset, mbuf_offset:$offset,
1934 glc:$glc, slc:$slc, tfe:$tfe),
1935 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
1936 "$glc"#"$slc"#"$tfe",
1937 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1938 i64:$vaddr, i32:$soffset,
1939 i16:$offset, i1:$glc, i1:$slc,
1945 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1946 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
1947 let mayLoad = 0, mayStore = 1 in {
1948 defm : MUBUF_m <op, name, (outs),
1949 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1950 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1952 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1953 "$glc"#"$slc"#"$tfe", []>;
1955 let offen = 0, idxen = 0, vaddr = 0 in {
1956 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1957 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
1958 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1959 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1960 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1961 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1962 } // offen = 0, idxen = 0, vaddr = 0
1964 let offen = 1, idxen = 0 in {
1965 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1966 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr,
1967 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1968 slc:$slc, tfe:$tfe),
1969 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1970 "$glc"#"$slc"#"$tfe", []>;
1971 } // end offen = 1, idxen = 0
1973 let offen = 0, idxen = 0 in {
1974 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1975 (ins vdataClass:$vdata, SReg_128:$srsrc,
1976 VReg_64:$vaddr, SCSrc_32:$soffset,
1977 mbuf_offset:$offset, glc:$glc, slc:$slc,
1979 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
1980 "$offset"#"$glc"#"$slc"#"$tfe",
1981 [(st store_vt:$vdata,
1982 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1983 i32:$soffset, i16:$offset,
1984 i1:$glc, i1:$slc, i1:$tfe))]>;
1986 } // End mayLoad = 0, mayStore = 1
1989 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1990 FLAT <op, (outs regClass:$vdst),
1991 (ins VReg_64:$addr),
1992 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2000 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2001 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2002 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2015 class MIMG_Mask <string op, int channels> {
2017 int Channels = channels;
2020 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2021 RegisterClass dst_rc,
2022 RegisterClass src_rc> : MIMG <
2024 (outs dst_rc:$vdata),
2025 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2026 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2028 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2029 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2034 let hasPostISelHook = 1;
2037 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2038 RegisterClass dst_rc,
2040 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2041 MIMG_Mask<asm#"_V1", channels>;
2042 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2043 MIMG_Mask<asm#"_V2", channels>;
2044 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2045 MIMG_Mask<asm#"_V4", channels>;
2048 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2049 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2050 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2051 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2052 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2055 class MIMG_Sampler_Helper <bits<7> op, string asm,
2056 RegisterClass dst_rc,
2057 RegisterClass src_rc, int wqm> : MIMG <
2059 (outs dst_rc:$vdata),
2060 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2061 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2062 SReg_256:$srsrc, SReg_128:$ssamp),
2063 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2064 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2068 let hasPostISelHook = 1;
2072 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2073 RegisterClass dst_rc,
2074 int channels, int wqm> {
2075 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2076 MIMG_Mask<asm#"_V1", channels>;
2077 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2078 MIMG_Mask<asm#"_V2", channels>;
2079 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2080 MIMG_Mask<asm#"_V4", channels>;
2081 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2082 MIMG_Mask<asm#"_V8", channels>;
2083 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2084 MIMG_Mask<asm#"_V16", channels>;
2087 multiclass MIMG_Sampler <bits<7> op, string asm> {
2088 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2089 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2090 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2091 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2094 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2095 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2096 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2097 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2098 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2101 class MIMG_Gather_Helper <bits<7> op, string asm,
2102 RegisterClass dst_rc,
2103 RegisterClass src_rc, int wqm> : MIMG <
2105 (outs dst_rc:$vdata),
2106 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2107 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2108 SReg_256:$srsrc, SReg_128:$ssamp),
2109 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2110 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2115 // DMASK was repurposed for GATHER4. 4 components are always
2116 // returned and DMASK works like a swizzle - it selects
2117 // the component to fetch. The only useful DMASK values are
2118 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2119 // (red,red,red,red) etc.) The ISA document doesn't mention
2121 // Therefore, disable all code which updates DMASK by setting these two:
2123 let hasPostISelHook = 0;
2127 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2128 RegisterClass dst_rc,
2129 int channels, int wqm> {
2130 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2131 MIMG_Mask<asm#"_V1", channels>;
2132 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2133 MIMG_Mask<asm#"_V2", channels>;
2134 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2135 MIMG_Mask<asm#"_V4", channels>;
2136 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2137 MIMG_Mask<asm#"_V8", channels>;
2138 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2139 MIMG_Mask<asm#"_V16", channels>;
2142 multiclass MIMG_Gather <bits<7> op, string asm> {
2143 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2144 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2145 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2146 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2149 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2150 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2151 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2152 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2153 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2156 //===----------------------------------------------------------------------===//
2157 // Vector instruction mappings
2158 //===----------------------------------------------------------------------===//
2160 // Maps an opcode in e32 form to its e64 equivalent
2161 def getVOPe64 : InstrMapping {
2162 let FilterClass = "VOP";
2163 let RowFields = ["OpName"];
2164 let ColFields = ["Size"];
2166 let ValueCols = [["8"]];
2169 // Maps an opcode in e64 form to its e32 equivalent
2170 def getVOPe32 : InstrMapping {
2171 let FilterClass = "VOP";
2172 let RowFields = ["OpName"];
2173 let ColFields = ["Size"];
2175 let ValueCols = [["4"]];
2178 // Maps an original opcode to its commuted version
2179 def getCommuteRev : InstrMapping {
2180 let FilterClass = "VOP2_REV";
2181 let RowFields = ["RevOp"];
2182 let ColFields = ["IsOrig"];
2184 let ValueCols = [["0"]];
2187 def getMaskedMIMGOp : InstrMapping {
2188 let FilterClass = "MIMG_Mask";
2189 let RowFields = ["Op"];
2190 let ColFields = ["Channels"];
2192 let ValueCols = [["1"], ["2"], ["3"] ];
2195 // Maps an commuted opcode to its original version
2196 def getCommuteOrig : InstrMapping {
2197 let FilterClass = "VOP2_REV";
2198 let RowFields = ["RevOp"];
2199 let ColFields = ["IsOrig"];
2201 let ValueCols = [["1"]];
2204 def getMCOpcodeGen : InstrMapping {
2205 let FilterClass = "SIMCInstr";
2206 let RowFields = ["PseudoInstr"];
2207 let ColFields = ["Subtarget"];
2208 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2209 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2212 def getAddr64Inst : InstrMapping {
2213 let FilterClass = "MUBUFAddr64Table";
2214 let RowFields = ["OpName"];
2215 let ColFields = ["IsAddr64"];
2217 let ValueCols = [["1"]];
2220 // Maps an atomic opcode to its version with a return value.
2221 def getAtomicRetOp : InstrMapping {
2222 let FilterClass = "AtomicNoRet";
2223 let RowFields = ["NoRetOp"];
2224 let ColFields = ["IsRet"];
2226 let ValueCols = [["1"]];
2229 // Maps an atomic opcode to its returnless version.
2230 def getAtomicNoRetOp : InstrMapping {
2231 let FilterClass = "AtomicNoRet";
2232 let RowFields = ["NoRetOp"];
2233 let ColFields = ["IsRet"];
2235 let ValueCols = [["0"]];
2238 include "SIInstructions.td"
2239 include "CIInstructions.td"
2240 include "VIInstructions.td"