1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
386 SOP1 <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
391 SOP1 <outs, ins, asm, []>,
393 SIMCInstr<opName, SISubtarget.VI>;
395 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
398 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
400 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
402 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
406 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
407 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
408 opName#" $dst, $src0", pattern
411 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
412 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
413 opName#" $dst, $src0", pattern
416 // no input, 64-bit output.
417 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
418 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
420 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
425 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
431 // 64-bit input, 32-bit output.
432 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
433 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
434 opName#" $dst, $src0", pattern
437 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
438 SOP2<outs, ins, "", pattern>,
439 SIMCInstr<opName, SISubtarget.NONE> {
444 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
445 SOP2<outs, ins, asm, []>,
447 SIMCInstr<opName, SISubtarget.SI>;
449 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
450 SOP2<outs, ins, asm, []>,
452 SIMCInstr<opName, SISubtarget.VI>;
454 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
455 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
456 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
458 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
459 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
460 opName#" $dst, $src0, $src1 [$scc]">;
462 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
463 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
464 opName#" $dst, $src0, $src1 [$scc]">;
467 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
468 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
469 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
471 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
472 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
474 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
475 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
478 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
479 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
480 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
482 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
483 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
485 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
486 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
489 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
490 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
491 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
493 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
494 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
496 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
497 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
501 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
502 string opName, PatLeaf cond> : SOPC <
503 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
504 opName#" $dst, $src0, $src1", []>;
506 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
507 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
509 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
510 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
512 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
513 SOPK <outs, ins, "", pattern>,
514 SIMCInstr<opName, SISubtarget.NONE> {
518 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
519 SOPK <outs, ins, asm, []>,
521 SIMCInstr<opName, SISubtarget.SI>;
523 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
524 SOPK <outs, ins, asm, []>,
526 SIMCInstr<opName, SISubtarget.VI>;
528 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
529 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
532 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
533 opName#" $dst, $src0">;
535 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
536 opName#" $dst, $src0">;
539 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
540 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
541 (ins SReg_32:$src0, u16imm:$src1), pattern>;
543 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
544 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
546 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
547 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
550 //===----------------------------------------------------------------------===//
552 //===----------------------------------------------------------------------===//
554 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
555 SMRD <outs, ins, "", pattern>,
556 SIMCInstr<opName, SISubtarget.NONE> {
560 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
562 SMRD <outs, ins, asm, []>,
564 SIMCInstr<opName, SISubtarget.SI>;
566 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
568 SMRD <outs, ins, asm, []>,
570 SIMCInstr<opName, SISubtarget.VI>;
572 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
573 string asm, list<dag> pattern> {
575 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
577 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
579 // glc is only applicable to scalar stores, which are not yet
582 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
586 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
587 RegisterClass dstClass> {
589 op, opName#"_IMM", 1, (outs dstClass:$dst),
590 (ins baseClass:$sbase, u32imm:$offset),
591 opName#" $dst, $sbase, $offset", []
594 defm _SGPR : SMRD_m <
595 op, opName#"_SGPR", 0, (outs dstClass:$dst),
596 (ins baseClass:$sbase, SReg_32:$soff),
597 opName#" $dst, $sbase, $soff", []
601 //===----------------------------------------------------------------------===//
602 // Vector ALU classes
603 //===----------------------------------------------------------------------===//
605 // This must always be right before the operand being input modified.
606 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
607 let PrintMethod = "printOperandAndMods";
609 def InputModsNoDefault : Operand <i32> {
610 let PrintMethod = "printOperandAndMods";
613 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
615 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
616 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
620 // Returns the register class to use for the destination of VOP[123C]
621 // instructions for the given VT.
622 class getVALUDstForVT<ValueType VT> {
623 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
624 !if(!eq(VT.Size, 64), VReg_64,
625 SReg_64)); // else VT == i1
628 // Returns the register class to use for source 0 of VOP[12C]
629 // instructions for the given VT.
630 class getVOPSrc0ForVT<ValueType VT> {
631 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
634 // Returns the register class to use for source 1 of VOP[12C] for the
636 class getVOPSrc1ForVT<ValueType VT> {
637 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
640 // Returns the register class to use for sources of VOP3 instructions for the
642 class getVOP3SrcForVT<ValueType VT> {
643 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
646 // Returns 1 if the source arguments have modifiers, 0 if they do not.
647 class hasModifiers<ValueType SrcVT> {
648 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
649 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
652 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
653 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
654 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
655 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
659 // Returns the input arguments for VOP3 instructions for the given SrcVT.
660 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
661 RegisterOperand Src2RC, int NumSrcArgs,
665 !if (!eq(NumSrcArgs, 1),
666 !if (!eq(HasModifiers, 1),
667 // VOP1 with modifiers
668 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
669 ClampMod:$clamp, omod:$omod)
671 // VOP1 without modifiers
674 !if (!eq(NumSrcArgs, 2),
675 !if (!eq(HasModifiers, 1),
676 // VOP 2 with modifiers
677 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
678 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
679 ClampMod:$clamp, omod:$omod)
681 // VOP2 without modifiers
682 (ins Src0RC:$src0, Src1RC:$src1)
684 /* NumSrcArgs == 3 */,
685 !if (!eq(HasModifiers, 1),
686 // VOP3 with modifiers
687 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
688 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
689 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
690 ClampMod:$clamp, omod:$omod)
692 // VOP3 without modifiers
693 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
697 // Returns the assembly string for the inputs and outputs of a VOP[12C]
698 // instruction. This does not add the _e32 suffix, so it can be reused
700 class getAsm32 <int NumSrcArgs> {
701 string src1 = ", $src1";
702 string src2 = ", $src2";
703 string ret = " $dst, $src0"#
704 !if(!eq(NumSrcArgs, 1), "", src1)#
705 !if(!eq(NumSrcArgs, 3), src2, "");
708 // Returns the assembly string for the inputs and outputs of a VOP3
710 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
711 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
712 string src1 = !if(!eq(NumSrcArgs, 1), "",
713 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
714 " $src1_modifiers,"));
715 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
717 !if(!eq(HasModifiers, 0),
718 getAsm32<NumSrcArgs>.ret,
719 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
723 class VOPProfile <list<ValueType> _ArgVT> {
725 field list<ValueType> ArgVT = _ArgVT;
727 field ValueType DstVT = ArgVT[0];
728 field ValueType Src0VT = ArgVT[1];
729 field ValueType Src1VT = ArgVT[2];
730 field ValueType Src2VT = ArgVT[3];
731 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
732 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
733 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
734 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
735 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
736 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
738 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
739 field bit HasModifiers = hasModifiers<Src0VT>.ret;
741 field dag Outs = (outs DstRC:$dst);
743 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
744 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
747 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
748 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
751 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
752 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
753 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
754 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
755 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
756 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
757 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
758 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
759 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
761 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
762 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
763 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
764 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
765 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
766 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
767 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
768 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
769 let Src0RC32 = VCSrc_32;
772 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
773 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
774 let Asm64 = " $dst, $src0_modifiers, $src1";
777 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
778 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
779 let Asm64 = " $dst, $src0_modifiers, $src1";
782 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
783 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
784 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
786 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
787 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
788 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
789 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
792 class VOP <string opName> {
793 string OpName = opName;
796 class VOP2_REV <string revOp, bit isOrig> {
797 string RevOp = revOp;
801 class AtomicNoRet <string noRetOp, bit isRet> {
802 string NoRetOp = noRetOp;
806 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
807 VOP1Common <outs, ins, "", pattern>,
809 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
813 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
815 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
817 def _si : VOP1<op.SI, outs, ins, asm, []>,
818 SIMCInstr <opName#"_e32", SISubtarget.SI>;
819 def _vi : VOP1<op.VI, outs, ins, asm, []>,
820 SIMCInstr <opName#"_e32", SISubtarget.VI>;
823 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
825 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
827 def _si : VOP1<op.SI, outs, ins, asm, []>,
828 SIMCInstr <opName#"_e32", SISubtarget.SI>;
829 // No VI instruction. This class is for SI only.
832 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
833 VOP2Common <outs, ins, "", pattern>,
835 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
839 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
840 string opName, string revOp> {
841 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
842 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
844 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
845 SIMCInstr <opName#"_e32", SISubtarget.SI>;
848 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
849 string opName, string revOp> {
850 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
851 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
853 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
854 SIMCInstr <opName#"_e32", SISubtarget.SI>;
855 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
856 SIMCInstr <opName#"_e32", SISubtarget.VI>;
859 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
861 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
862 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
863 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
864 bits<2> omod = !if(HasModifiers, ?, 0);
865 bits<1> clamp = !if(HasModifiers, ?, 0);
866 bits<9> src1 = !if(HasSrc1, ?, 0);
867 bits<9> src2 = !if(HasSrc2, ?, 0);
870 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
871 VOP3Common <outs, ins, "", pattern>,
873 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
877 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
878 VOP3Common <outs, ins, asm, []>,
880 SIMCInstr<opName#"_e64", SISubtarget.SI>;
882 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
883 VOP3Common <outs, ins, asm, []>,
885 SIMCInstr <opName#"_e64", SISubtarget.VI>;
887 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
888 VOP3Common <outs, ins, asm, []>,
890 SIMCInstr<opName#"_e64", SISubtarget.SI>;
892 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
893 VOP3Common <outs, ins, asm, []>,
895 SIMCInstr <opName#"_e64", SISubtarget.VI>;
897 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
898 string opName, int NumSrcArgs, bit HasMods = 1> {
900 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
902 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
903 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
904 !if(!eq(NumSrcArgs, 2), 0, 1),
906 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
907 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
908 !if(!eq(NumSrcArgs, 2), 0, 1),
912 // VOP3_m without source modifiers
913 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
914 string opName, int NumSrcArgs, bit HasMods = 1> {
916 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
918 let src0_modifiers = 0,
923 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
924 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
928 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
929 list<dag> pattern, string opName, bit HasMods = 1> {
931 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
933 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
934 VOP3DisableFields<0, 0, HasMods>;
936 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
937 VOP3DisableFields<0, 0, HasMods>;
940 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
941 list<dag> pattern, string opName, bit HasMods = 1> {
943 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
945 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
946 VOP3DisableFields<0, 0, HasMods>;
947 // No VI instruction. This class is for SI only.
950 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
951 list<dag> pattern, string opName, string revOp,
952 bit HasMods = 1, bit UseFullOp = 0> {
954 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
955 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
957 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
958 VOP3DisableFields<1, 0, HasMods>;
960 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
961 VOP3DisableFields<1, 0, HasMods>;
964 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
965 list<dag> pattern, string opName, string revOp,
966 bit HasMods = 1, bit UseFullOp = 0> {
968 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
969 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
971 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
972 VOP3DisableFields<1, 0, HasMods>;
974 // No VI instruction. This class is for SI only.
977 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
978 // option of implicit vcc use?
979 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
980 list<dag> pattern, string opName, string revOp,
981 bit HasMods = 1, bit UseFullOp = 0> {
982 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
983 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
985 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
986 // can write it into any SGPR. We currently don't use the carry out,
987 // so for now hardcode it to VCC as well.
988 let sdst = SIOperand.VCC, Defs = [VCC] in {
989 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
990 VOP3DisableFields<1, 0, HasMods>;
992 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
993 VOP3DisableFields<1, 0, HasMods>;
994 } // End sdst = SIOperand.VCC, Defs = [VCC]
997 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
998 list<dag> pattern, string opName, string revOp,
999 bit HasMods = 1, bit UseFullOp = 0> {
1000 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1003 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1004 VOP3DisableFields<1, 1, HasMods>;
1006 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1007 VOP3DisableFields<1, 1, HasMods>;
1010 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1011 list<dag> pattern, string opName,
1012 bit HasMods, bit defExec> {
1014 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1016 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1017 VOP3DisableFields<1, 0, HasMods> {
1018 let Defs = !if(defExec, [EXEC], []);
1021 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1022 VOP3DisableFields<1, 0, HasMods> {
1023 let Defs = !if(defExec, [EXEC], []);
1027 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1028 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1029 string asm, list<dag> pattern = []> {
1030 let isPseudo = 1 in {
1031 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1032 SIMCInstr<opName, SISubtarget.NONE>;
1035 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1036 SIMCInstr <opName, SISubtarget.SI>;
1038 def _vi : VOP3Common <outs, ins, asm, []>,
1040 VOP3DisableFields <1, 0, 0>,
1041 SIMCInstr <opName, SISubtarget.VI>;
1044 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1045 dag ins32, string asm32, list<dag> pat32,
1046 dag ins64, string asm64, list<dag> pat64,
1049 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1051 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1054 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1055 SDPatternOperator node = null_frag> : VOP1_Helper <
1057 P.Ins32, P.Asm32, [],
1060 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1061 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1062 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1066 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1067 SDPatternOperator node = null_frag> {
1069 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1071 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1073 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1074 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1075 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1076 opName, P.HasModifiers>;
1079 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1080 dag ins32, string asm32, list<dag> pat32,
1081 dag ins64, string asm64, list<dag> pat64,
1082 string revOp, bit HasMods> {
1083 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1085 defm _e64 : VOP3_2_m <op,
1086 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1090 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1091 SDPatternOperator node = null_frag,
1092 string revOp = opName> : VOP2_Helper <
1094 P.Ins32, P.Asm32, [],
1098 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1099 i1:$clamp, i32:$omod)),
1100 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1101 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1102 revOp, P.HasModifiers
1105 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1106 SDPatternOperator node = null_frag,
1107 string revOp = opName> {
1108 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1110 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1113 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1114 i1:$clamp, i32:$omod)),
1115 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1116 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1117 opName, revOp, P.HasModifiers>;
1120 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1121 dag ins32, string asm32, list<dag> pat32,
1122 dag ins64, string asm64, list<dag> pat64,
1123 string revOp, bit HasMods> {
1125 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1127 defm _e64 : VOP3b_2_m <op,
1128 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1132 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1133 SDPatternOperator node = null_frag,
1134 string revOp = opName> : VOP2b_Helper <
1136 P.Ins32, P.Asm32, [],
1140 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1141 i1:$clamp, i32:$omod)),
1142 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1143 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1144 revOp, P.HasModifiers
1147 // A VOP2 instruction that is VOP3-only on VI.
1148 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1149 dag ins32, string asm32, list<dag> pat32,
1150 dag ins64, string asm64, list<dag> pat64,
1151 string revOp, bit HasMods> {
1152 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1154 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1158 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1159 SDPatternOperator node = null_frag,
1160 string revOp = opName>
1163 P.Ins32, P.Asm32, [],
1167 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1168 i1:$clamp, i32:$omod)),
1169 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1170 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1171 revOp, P.HasModifiers
1174 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1175 VOPCCommon <ins, "", pattern>,
1177 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1181 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1182 string opName, bit DefExec> {
1183 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1185 def _si : VOPC<op.SI, ins, asm, []>,
1186 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1187 let Defs = !if(DefExec, [EXEC], []);
1190 def _vi : VOPC<op.VI, ins, asm, []>,
1191 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1192 let Defs = !if(DefExec, [EXEC], []);
1196 multiclass VOPC_Helper <vopc op, string opName,
1197 dag ins32, string asm32, list<dag> pat32,
1198 dag out64, dag ins64, string asm64, list<dag> pat64,
1199 bit HasMods, bit DefExec> {
1200 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1202 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1203 opName, HasMods, DefExec>;
1206 multiclass VOPCInst <vopc op, string opName,
1207 VOPProfile P, PatLeaf cond = COND_NULL,
1208 bit DefExec = 0> : VOPC_Helper <
1210 P.Ins32, P.Asm32, [],
1211 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1214 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1215 i1:$clamp, i32:$omod)),
1216 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1218 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1219 P.HasModifiers, DefExec
1222 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1223 bit DefExec = 0> : VOPC_Helper <
1225 P.Ins32, P.Asm32, [],
1226 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1229 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1230 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1231 P.HasModifiers, DefExec
1235 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1236 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1238 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1239 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1241 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1242 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1244 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1245 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1248 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1249 PatLeaf cond = COND_NULL>
1250 : VOPCInst <op, opName, P, cond, 1>;
1252 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1253 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1255 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1256 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1258 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1259 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1261 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1262 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1264 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1265 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1266 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1269 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1270 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1272 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1273 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1275 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1276 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1278 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1279 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1281 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1282 SDPatternOperator node = null_frag> : VOP3_Helper <
1283 op, opName, P.Outs, P.Ins64, P.Asm64,
1284 !if(!eq(P.NumSrcArgs, 3),
1287 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1288 i1:$clamp, i32:$omod)),
1289 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1290 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1291 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1293 !if(!eq(P.NumSrcArgs, 2),
1296 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1297 i1:$clamp, i32:$omod)),
1298 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1299 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1300 /* P.NumSrcArgs == 1 */,
1303 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1304 i1:$clamp, i32:$omod))))],
1305 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1306 P.NumSrcArgs, P.HasModifiers
1309 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1310 // only VOP instruction that implicitly reads VCC.
1311 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1313 SDPatternOperator node = null_frag> : VOP3_Helper <
1316 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1317 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1318 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1321 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1323 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1324 i1:$clamp, i32:$omod)),
1325 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1326 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1331 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1332 string opName, list<dag> pattern> :
1334 op, (outs vrc:$vdst, SReg_64:$sdst),
1335 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1336 InputModsNoDefault:$src1_modifiers, arc:$src1,
1337 InputModsNoDefault:$src2_modifiers, arc:$src2,
1338 ClampMod:$clamp, omod:$omod),
1339 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1340 opName, opName, 1, 1
1343 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1344 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1346 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1347 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1350 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1351 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1352 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1353 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1354 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1355 i32:$src1_modifiers, P.Src1VT:$src1,
1356 i32:$src2_modifiers, P.Src2VT:$src2,
1360 //===----------------------------------------------------------------------===//
1361 // Interpolation opcodes
1362 //===----------------------------------------------------------------------===//
1364 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1365 VINTRPCommon <outs, ins, "", pattern>,
1366 SIMCInstr<opName, SISubtarget.NONE> {
1370 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1372 VINTRPCommon <outs, ins, asm, []>,
1374 SIMCInstr<opName, SISubtarget.SI>;
1376 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1378 VINTRPCommon <outs, ins, asm, []>,
1380 SIMCInstr<opName, SISubtarget.VI>;
1382 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1383 string disableEncoding = "", string constraints = "",
1384 list<dag> pattern = []> {
1385 let DisableEncoding = disableEncoding,
1386 Constraints = constraints in {
1387 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1389 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1391 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1395 //===----------------------------------------------------------------------===//
1396 // Vector I/O classes
1397 //===----------------------------------------------------------------------===//
1399 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1400 DS <outs, ins, "", pattern>,
1401 SIMCInstr <opName, SISubtarget.NONE> {
1405 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1406 DS <outs, ins, asm, []>,
1408 SIMCInstr <opName, SISubtarget.SI>;
1410 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1411 DS <outs, ins, asm, []>,
1413 SIMCInstr <opName, SISubtarget.VI>;
1415 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1416 DS <outs, ins, asm, []>,
1418 SIMCInstr <opName, SISubtarget.SI> {
1420 // Single load interpret the 2 i8imm operands as a single i16 offset.
1422 let offset0 = offset{7-0};
1423 let offset1 = offset{15-8};
1426 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1427 DS <outs, ins, asm, []>,
1429 SIMCInstr <opName, SISubtarget.VI> {
1431 // Single load interpret the 2 i8imm operands as a single i16 offset.
1433 let offset0 = offset{7-0};
1434 let offset1 = offset{15-8};
1437 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1439 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1440 def "" : DS_Pseudo <opName, outs, ins, pat>;
1442 let data0 = 0, data1 = 0 in {
1443 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1444 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1449 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1453 (outs regClass:$vdst),
1454 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1455 asm#" $vdst, $addr"#"$offset"#" [M0]",
1458 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1460 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1461 def "" : DS_Pseudo <opName, outs, ins, pat>;
1463 let data0 = 0, data1 = 0 in {
1464 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1465 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1470 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1474 (outs regClass:$vdst),
1475 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1477 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1480 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1481 string asm, list<dag> pat> {
1482 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1483 def "" : DS_Pseudo <opName, outs, ins, pat>;
1485 let data1 = 0, vdst = 0 in {
1486 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1487 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1492 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1497 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1498 asm#" $addr, $data0"#"$offset"#" [M0]",
1501 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1502 string asm, list<dag> pat> {
1503 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1504 def "" : DS_Pseudo <opName, outs, ins, pat>;
1507 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1508 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1513 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1518 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1519 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1520 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1523 // 1 address, 1 data.
1524 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1525 string asm, list<dag> pat, string noRetOp> {
1526 let mayLoad = 1, mayStore = 1,
1527 hasPostISelHook = 1 // Adjusted to no return version.
1529 def "" : DS_Pseudo <opName, outs, ins, pat>,
1530 AtomicNoRet<noRetOp, 1>;
1533 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1534 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1539 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1540 string noRetOp = ""> : DS_1A1D_RET_m <
1543 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1544 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1546 // 1 address, 2 data.
1547 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1548 string asm, list<dag> pat, string noRetOp> {
1549 let mayLoad = 1, mayStore = 1,
1550 hasPostISelHook = 1 // Adjusted to no return version.
1552 def "" : DS_Pseudo <opName, outs, ins, pat>,
1553 AtomicNoRet<noRetOp, 1>;
1555 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1556 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1560 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1561 string noRetOp = ""> : DS_1A2D_RET_m <
1564 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1565 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1568 // 1 address, 2 data.
1569 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1570 string asm, list<dag> pat, string noRetOp> {
1571 let mayLoad = 1, mayStore = 1 in {
1572 def "" : DS_Pseudo <opName, outs, ins, pat>,
1573 AtomicNoRet<noRetOp, 0>;
1576 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1577 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1582 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1583 string noRetOp = asm> : DS_1A2D_NORET_m <
1586 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1587 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1590 // 1 address, 1 data.
1591 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1592 string asm, list<dag> pat, string noRetOp> {
1593 let mayLoad = 1, mayStore = 1 in {
1594 def "" : DS_Pseudo <opName, outs, ins, pat>,
1595 AtomicNoRet<noRetOp, 0>;
1597 let data1 = 0, vdst = 0 in {
1598 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1599 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1604 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1605 string noRetOp = asm> : DS_1A1D_NORET_m <
1608 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1609 asm#" $addr, $data0"#"$offset"#" [M0]",
1612 //===----------------------------------------------------------------------===//
1614 //===----------------------------------------------------------------------===//
1616 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1617 MTBUF <outs, ins, "", pattern>,
1618 SIMCInstr<opName, SISubtarget.NONE> {
1622 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1624 MTBUF <outs, ins, asm, []>,
1626 SIMCInstr<opName, SISubtarget.SI>;
1628 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1629 MTBUF <outs, ins, asm, []>,
1631 SIMCInstr <opName, SISubtarget.VI>;
1633 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1634 list<dag> pattern> {
1636 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1638 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1640 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1644 let mayStore = 1, mayLoad = 0 in {
1646 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1647 RegisterClass regClass> : MTBUF_m <
1649 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1650 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1651 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1652 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1653 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1656 } // mayStore = 1, mayLoad = 0
1658 let mayLoad = 1, mayStore = 0 in {
1660 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1661 RegisterClass regClass> : MTBUF_m <
1662 op, opName, (outs regClass:$dst),
1663 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1664 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1665 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1666 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1667 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1670 } // mayLoad = 1, mayStore = 0
1672 //===----------------------------------------------------------------------===//
1674 //===----------------------------------------------------------------------===//
1676 class mubuf <bits<7> si, bits<7> vi = si> {
1677 field bits<7> SI = si;
1678 field bits<7> VI = vi;
1681 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1682 bit IsAddr64 = is_addr64;
1683 string OpName = NAME # suffix;
1686 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1687 MUBUF <outs, ins, "", pattern>,
1688 SIMCInstr<opName, SISubtarget.NONE> {
1691 // dummy fields, so that we can use let statements around multiclasses
1701 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1703 MUBUF <outs, ins, asm, []>,
1705 SIMCInstr<opName, SISubtarget.SI> {
1709 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1711 MUBUF <outs, ins, asm, []>,
1713 SIMCInstr<opName, SISubtarget.VI> {
1717 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1718 list<dag> pattern> {
1720 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1721 MUBUFAddr64Table <0>;
1724 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1727 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1730 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1731 dag ins, string asm, list<dag> pattern> {
1733 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1734 MUBUFAddr64Table <1>;
1737 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1740 // There is no VI version. If the pseudo is selected, it should be lowered
1741 // for VI appropriately.
1744 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1745 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1749 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1750 string asm, list<dag> pattern, bit is_return> {
1752 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1753 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1754 AtomicNoRet<NAME#"_OFFSET", is_return>;
1756 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1758 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1761 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1765 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1766 string asm, list<dag> pattern, bit is_return> {
1768 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1769 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1770 AtomicNoRet<NAME#"_ADDR64", is_return>;
1772 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1773 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1776 // There is no VI version. If the pseudo is selected, it should be lowered
1777 // for VI appropriately.
1780 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1781 ValueType vt, SDPatternOperator atomic> {
1783 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1785 // No return variants
1788 defm _ADDR64 : MUBUFAtomicAddr64_m <
1789 op, name#"_addr64", (outs),
1790 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1791 mbuf_offset:$offset, SCSrc_32:$soffset, slc:$slc),
1792 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1795 defm _OFFSET : MUBUFAtomicOffset_m <
1796 op, name#"_offset", (outs),
1797 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1798 SCSrc_32:$soffset, slc:$slc),
1799 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1803 // Variant that return values
1804 let glc = 1, Constraints = "$vdata = $vdata_in",
1805 DisableEncoding = "$vdata_in" in {
1807 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1808 op, name#"_rtn_addr64", (outs rc:$vdata),
1809 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1810 mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
1811 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1813 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1814 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1817 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1818 op, name#"_rtn_offset", (outs rc:$vdata),
1819 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1820 SCSrc_32:$soffset, slc:$slc),
1821 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1823 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1824 i1:$slc), vt:$vdata_in))], 1
1829 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1832 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1833 ValueType load_vt = i32,
1834 SDPatternOperator ld = null_frag> {
1836 let mayLoad = 1, mayStore = 0 in {
1837 let offen = 0, idxen = 0, vaddr = 0 in {
1838 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1839 (ins SReg_128:$srsrc,
1840 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1841 slc:$slc, tfe:$tfe),
1842 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1843 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1844 i32:$soffset, i16:$offset,
1845 i1:$glc, i1:$slc, i1:$tfe)))]>;
1848 let offen = 1, idxen = 0 in {
1849 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1850 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1851 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1853 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1856 let offen = 0, idxen = 1 in {
1857 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1858 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1859 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1860 slc:$slc, tfe:$tfe),
1861 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1864 let offen = 1, idxen = 1 in {
1865 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1866 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1867 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1868 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1871 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1872 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1873 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1874 SCSrc_32:$soffset, mbuf_offset:$offset),
1875 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1876 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1877 i64:$vaddr, i32:$soffset,
1883 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1884 ValueType store_vt, SDPatternOperator st> {
1885 let mayLoad = 0, mayStore = 1 in {
1886 defm : MUBUF_m <op, name, (outs),
1887 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1888 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1890 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1891 "$glc"#"$slc"#"$tfe", []>;
1893 let offen = 0, idxen = 0, vaddr = 0 in {
1894 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1895 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1896 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1897 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1898 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1899 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1900 } // offen = 0, idxen = 0, vaddr = 0
1902 let offen = 1, idxen = 0 in {
1903 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1904 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1905 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1906 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1907 "$glc"#"$slc"#"$tfe", []>;
1908 } // end offen = 1, idxen = 0
1910 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1911 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1912 (ins vdataClass:$vdata, SReg_128:$srsrc,
1913 VReg_64:$vaddr, SCSrc_32:$soffset,
1914 mbuf_offset:$offset),
1915 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1916 [(st store_vt:$vdata,
1917 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1918 i32:$soffset, i16:$offset))]>;
1920 } // End mayLoad = 0, mayStore = 1
1923 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1924 FLAT <op, (outs regClass:$vdst),
1925 (ins VReg_64:$addr),
1926 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
1934 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1935 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1936 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1949 class MIMG_Mask <string op, int channels> {
1951 int Channels = channels;
1954 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1955 RegisterClass dst_rc,
1956 RegisterClass src_rc> : MIMG <
1958 (outs dst_rc:$vdata),
1959 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1960 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1962 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1963 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1968 let hasPostISelHook = 1;
1971 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1972 RegisterClass dst_rc,
1974 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1975 MIMG_Mask<asm#"_V1", channels>;
1976 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1977 MIMG_Mask<asm#"_V2", channels>;
1978 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1979 MIMG_Mask<asm#"_V4", channels>;
1982 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1983 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1984 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1985 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1986 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1989 class MIMG_Sampler_Helper <bits<7> op, string asm,
1990 RegisterClass dst_rc,
1991 RegisterClass src_rc, int wqm> : MIMG <
1993 (outs dst_rc:$vdata),
1994 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1995 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1996 SReg_256:$srsrc, SReg_128:$ssamp),
1997 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1998 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2002 let hasPostISelHook = 1;
2006 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2007 RegisterClass dst_rc,
2008 int channels, int wqm> {
2009 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2010 MIMG_Mask<asm#"_V1", channels>;
2011 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2012 MIMG_Mask<asm#"_V2", channels>;
2013 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2014 MIMG_Mask<asm#"_V4", channels>;
2015 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2016 MIMG_Mask<asm#"_V8", channels>;
2017 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2018 MIMG_Mask<asm#"_V16", channels>;
2021 multiclass MIMG_Sampler <bits<7> op, string asm> {
2022 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2023 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2024 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2025 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2028 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2029 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2030 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2031 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2032 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2035 class MIMG_Gather_Helper <bits<7> op, string asm,
2036 RegisterClass dst_rc,
2037 RegisterClass src_rc, int wqm> : MIMG <
2039 (outs dst_rc:$vdata),
2040 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2041 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2042 SReg_256:$srsrc, SReg_128:$ssamp),
2043 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2044 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2049 // DMASK was repurposed for GATHER4. 4 components are always
2050 // returned and DMASK works like a swizzle - it selects
2051 // the component to fetch. The only useful DMASK values are
2052 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2053 // (red,red,red,red) etc.) The ISA document doesn't mention
2055 // Therefore, disable all code which updates DMASK by setting these two:
2057 let hasPostISelHook = 0;
2061 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2062 RegisterClass dst_rc,
2063 int channels, int wqm> {
2064 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2065 MIMG_Mask<asm#"_V1", channels>;
2066 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2067 MIMG_Mask<asm#"_V2", channels>;
2068 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2069 MIMG_Mask<asm#"_V4", channels>;
2070 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2071 MIMG_Mask<asm#"_V8", channels>;
2072 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2073 MIMG_Mask<asm#"_V16", channels>;
2076 multiclass MIMG_Gather <bits<7> op, string asm> {
2077 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2078 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2079 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2080 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2083 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2084 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2085 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2086 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2087 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2090 //===----------------------------------------------------------------------===//
2091 // Vector instruction mappings
2092 //===----------------------------------------------------------------------===//
2094 // Maps an opcode in e32 form to its e64 equivalent
2095 def getVOPe64 : InstrMapping {
2096 let FilterClass = "VOP";
2097 let RowFields = ["OpName"];
2098 let ColFields = ["Size"];
2100 let ValueCols = [["8"]];
2103 // Maps an opcode in e64 form to its e32 equivalent
2104 def getVOPe32 : InstrMapping {
2105 let FilterClass = "VOP";
2106 let RowFields = ["OpName"];
2107 let ColFields = ["Size"];
2109 let ValueCols = [["4"]];
2112 // Maps an original opcode to its commuted version
2113 def getCommuteRev : InstrMapping {
2114 let FilterClass = "VOP2_REV";
2115 let RowFields = ["RevOp"];
2116 let ColFields = ["IsOrig"];
2118 let ValueCols = [["0"]];
2121 def getMaskedMIMGOp : InstrMapping {
2122 let FilterClass = "MIMG_Mask";
2123 let RowFields = ["Op"];
2124 let ColFields = ["Channels"];
2126 let ValueCols = [["1"], ["2"], ["3"] ];
2129 // Maps an commuted opcode to its original version
2130 def getCommuteOrig : InstrMapping {
2131 let FilterClass = "VOP2_REV";
2132 let RowFields = ["RevOp"];
2133 let ColFields = ["IsOrig"];
2135 let ValueCols = [["1"]];
2138 def getMCOpcodeGen : InstrMapping {
2139 let FilterClass = "SIMCInstr";
2140 let RowFields = ["PseudoInstr"];
2141 let ColFields = ["Subtarget"];
2142 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2143 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2146 def getAddr64Inst : InstrMapping {
2147 let FilterClass = "MUBUFAddr64Table";
2148 let RowFields = ["OpName"];
2149 let ColFields = ["IsAddr64"];
2151 let ValueCols = [["1"]];
2154 // Maps an atomic opcode to its version with a return value.
2155 def getAtomicRetOp : InstrMapping {
2156 let FilterClass = "AtomicNoRet";
2157 let RowFields = ["NoRetOp"];
2158 let ColFields = ["IsRet"];
2160 let ValueCols = [["1"]];
2163 // Maps an atomic opcode to its returnless version.
2164 def getAtomicNoRetOp : InstrMapping {
2165 let FilterClass = "AtomicNoRet";
2166 let RowFields = ["NoRetOp"];
2167 let ColFields = ["IsRet"];
2169 let ValueCols = [["0"]];
2172 include "SIInstructions.td"
2173 include "CIInstructions.td"
2174 include "VIInstructions.td"