1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
386 SOP1 <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
391 SOP1 <outs, ins, asm, []>,
393 SIMCInstr<opName, SISubtarget.VI>;
395 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
398 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
400 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
402 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
406 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
407 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
408 opName#" $dst, $src0", pattern
411 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
412 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
413 opName#" $dst, $src0", pattern
416 // no input, 64-bit output.
417 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
418 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
420 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
425 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
431 // 64-bit input, no output
432 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
433 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
435 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
440 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
446 // 64-bit input, 32-bit output.
447 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
448 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
449 opName#" $dst, $src0", pattern
452 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
453 SOP2<outs, ins, "", pattern>,
454 SIMCInstr<opName, SISubtarget.NONE> {
458 // Pseudo instructions have no encodings, but adding this field here allows
460 // let sdst = xxx in {
461 // for multiclasses that include both real and pseudo instructions.
462 field bits<7> sdst = 0;
465 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
466 SOP2<outs, ins, asm, []>,
468 SIMCInstr<opName, SISubtarget.SI>;
470 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
471 SOP2<outs, ins, asm, []>,
473 SIMCInstr<opName, SISubtarget.VI>;
475 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
476 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
477 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
479 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
480 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
481 opName#" $dst, $src0, $src1 [$scc]">;
483 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
484 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
485 opName#" $dst, $src0, $src1 [$scc]">;
488 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
491 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
493 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
495 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
499 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
500 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
501 opName#" $dst, $src0, $src1", pattern
504 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
505 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
506 opName#" $dst, $src0, $src1", pattern
509 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
510 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
511 opName#" $dst, $src0, $src1", pattern
514 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
515 string opName, PatLeaf cond> : SOPC <
516 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
517 opName#" $dst, $src0, $src1", []>;
519 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
520 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
522 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
523 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
525 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
526 SOPK <outs, ins, "", pattern>,
527 SIMCInstr<opName, SISubtarget.NONE> {
531 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
532 SOPK <outs, ins, asm, []>,
534 SIMCInstr<opName, SISubtarget.SI>;
536 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
537 SOPK <outs, ins, asm, []>,
539 SIMCInstr<opName, SISubtarget.VI>;
541 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
542 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
545 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
546 opName#" $dst, $src0">;
548 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
549 opName#" $dst, $src0">;
552 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
553 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
554 (ins SReg_32:$src0, u16imm:$src1), pattern>;
556 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
557 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
559 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
560 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
563 //===----------------------------------------------------------------------===//
565 //===----------------------------------------------------------------------===//
567 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
568 SMRD <outs, ins, "", pattern>,
569 SIMCInstr<opName, SISubtarget.NONE> {
573 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
575 SMRD <outs, ins, asm, []>,
577 SIMCInstr<opName, SISubtarget.SI>;
579 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
581 SMRD <outs, ins, asm, []>,
583 SIMCInstr<opName, SISubtarget.VI>;
585 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
586 string asm, list<dag> pattern> {
588 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
590 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
592 // glc is only applicable to scalar stores, which are not yet
595 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
599 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
600 RegisterClass dstClass> {
602 op, opName#"_IMM", 1, (outs dstClass:$dst),
603 (ins baseClass:$sbase, u32imm:$offset),
604 opName#" $dst, $sbase, $offset", []
607 defm _SGPR : SMRD_m <
608 op, opName#"_SGPR", 0, (outs dstClass:$dst),
609 (ins baseClass:$sbase, SReg_32:$soff),
610 opName#" $dst, $sbase, $soff", []
614 //===----------------------------------------------------------------------===//
615 // Vector ALU classes
616 //===----------------------------------------------------------------------===//
618 // This must always be right before the operand being input modified.
619 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
620 let PrintMethod = "printOperandAndMods";
622 def InputModsNoDefault : Operand <i32> {
623 let PrintMethod = "printOperandAndMods";
626 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
628 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
629 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
633 // Returns the register class to use for the destination of VOP[123C]
634 // instructions for the given VT.
635 class getVALUDstForVT<ValueType VT> {
636 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
637 !if(!eq(VT.Size, 64), VReg_64,
638 SReg_64)); // else VT == i1
641 // Returns the register class to use for source 0 of VOP[12C]
642 // instructions for the given VT.
643 class getVOPSrc0ForVT<ValueType VT> {
644 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
647 // Returns the register class to use for source 1 of VOP[12C] for the
649 class getVOPSrc1ForVT<ValueType VT> {
650 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
653 // Returns the register class to use for sources of VOP3 instructions for the
655 class getVOP3SrcForVT<ValueType VT> {
656 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
659 // Returns 1 if the source arguments have modifiers, 0 if they do not.
660 class hasModifiers<ValueType SrcVT> {
661 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
662 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
665 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
666 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
667 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
668 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
672 // Returns the input arguments for VOP3 instructions for the given SrcVT.
673 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
674 RegisterOperand Src2RC, int NumSrcArgs,
678 !if (!eq(NumSrcArgs, 1),
679 !if (!eq(HasModifiers, 1),
680 // VOP1 with modifiers
681 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
682 ClampMod:$clamp, omod:$omod)
684 // VOP1 without modifiers
687 !if (!eq(NumSrcArgs, 2),
688 !if (!eq(HasModifiers, 1),
689 // VOP 2 with modifiers
690 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
691 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
692 ClampMod:$clamp, omod:$omod)
694 // VOP2 without modifiers
695 (ins Src0RC:$src0, Src1RC:$src1)
697 /* NumSrcArgs == 3 */,
698 !if (!eq(HasModifiers, 1),
699 // VOP3 with modifiers
700 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
701 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
702 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
703 ClampMod:$clamp, omod:$omod)
705 // VOP3 without modifiers
706 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
710 // Returns the assembly string for the inputs and outputs of a VOP[12C]
711 // instruction. This does not add the _e32 suffix, so it can be reused
713 class getAsm32 <int NumSrcArgs> {
714 string src1 = ", $src1";
715 string src2 = ", $src2";
716 string ret = " $dst, $src0"#
717 !if(!eq(NumSrcArgs, 1), "", src1)#
718 !if(!eq(NumSrcArgs, 3), src2, "");
721 // Returns the assembly string for the inputs and outputs of a VOP3
723 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
724 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
725 string src1 = !if(!eq(NumSrcArgs, 1), "",
726 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
727 " $src1_modifiers,"));
728 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
730 !if(!eq(HasModifiers, 0),
731 getAsm32<NumSrcArgs>.ret,
732 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
736 class VOPProfile <list<ValueType> _ArgVT> {
738 field list<ValueType> ArgVT = _ArgVT;
740 field ValueType DstVT = ArgVT[0];
741 field ValueType Src0VT = ArgVT[1];
742 field ValueType Src1VT = ArgVT[2];
743 field ValueType Src2VT = ArgVT[3];
744 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
745 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
746 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
747 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
748 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
749 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
751 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
752 field bit HasModifiers = hasModifiers<Src0VT>.ret;
754 field dag Outs = (outs DstRC:$dst);
756 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
757 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
760 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
761 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
764 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
765 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
766 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
767 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
768 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
769 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
770 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
771 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
772 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
774 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
775 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
776 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
777 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
778 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
779 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
780 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
781 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
782 let Src0RC32 = VCSrc_32;
785 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
786 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
787 let Asm64 = " $dst, $src0_modifiers, $src1";
790 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
791 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
792 let Asm64 = " $dst, $src0_modifiers, $src1";
795 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
796 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
797 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
799 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
800 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
801 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
802 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
805 class VOP <string opName> {
806 string OpName = opName;
809 class VOP2_REV <string revOp, bit isOrig> {
810 string RevOp = revOp;
814 class AtomicNoRet <string noRetOp, bit isRet> {
815 string NoRetOp = noRetOp;
819 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
820 VOP1Common <outs, ins, "", pattern>,
822 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
826 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
828 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
830 def _si : VOP1<op.SI, outs, ins, asm, []>,
831 SIMCInstr <opName#"_e32", SISubtarget.SI>;
832 def _vi : VOP1<op.VI, outs, ins, asm, []>,
833 SIMCInstr <opName#"_e32", SISubtarget.VI>;
836 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
838 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
840 def _si : VOP1<op.SI, outs, ins, asm, []>,
841 SIMCInstr <opName#"_e32", SISubtarget.SI>;
842 // No VI instruction. This class is for SI only.
845 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
846 VOP2Common <outs, ins, "", pattern>,
848 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
852 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
853 string opName, string revOp> {
854 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
855 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
857 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
858 SIMCInstr <opName#"_e32", SISubtarget.SI>;
861 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
862 string opName, string revOp> {
863 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
864 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
866 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
867 SIMCInstr <opName#"_e32", SISubtarget.SI>;
868 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
869 SIMCInstr <opName#"_e32", SISubtarget.VI>;
872 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
874 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
875 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
876 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
877 bits<2> omod = !if(HasModifiers, ?, 0);
878 bits<1> clamp = !if(HasModifiers, ?, 0);
879 bits<9> src1 = !if(HasSrc1, ?, 0);
880 bits<9> src2 = !if(HasSrc2, ?, 0);
883 class VOP3DisableModFields <bit HasSrc0Mods,
886 bit HasOutputMods = 0> {
887 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
888 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
889 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
890 bits<2> omod = !if(HasOutputMods, ?, 0);
891 bits<1> clamp = !if(HasOutputMods, ?, 0);
894 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
895 VOP3Common <outs, ins, "", pattern>,
897 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
901 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
902 VOP3Common <outs, ins, asm, []>,
904 SIMCInstr<opName#"_e64", SISubtarget.SI>;
906 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
907 VOP3Common <outs, ins, asm, []>,
909 SIMCInstr <opName#"_e64", SISubtarget.VI>;
911 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
912 VOP3Common <outs, ins, asm, []>,
914 SIMCInstr<opName#"_e64", SISubtarget.SI>;
916 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
917 VOP3Common <outs, ins, asm, []>,
919 SIMCInstr <opName#"_e64", SISubtarget.VI>;
921 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
922 string opName, int NumSrcArgs, bit HasMods = 1> {
924 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
926 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
927 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
928 !if(!eq(NumSrcArgs, 2), 0, 1),
930 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
931 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
932 !if(!eq(NumSrcArgs, 2), 0, 1),
936 // VOP3_m without source modifiers
937 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
938 string opName, int NumSrcArgs, bit HasMods = 1> {
940 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
942 let src0_modifiers = 0,
947 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
948 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
952 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
953 list<dag> pattern, string opName, bit HasMods = 1> {
955 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
957 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
958 VOP3DisableFields<0, 0, HasMods>;
960 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
961 VOP3DisableFields<0, 0, HasMods>;
964 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
965 list<dag> pattern, string opName, bit HasMods = 1> {
967 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
969 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
970 VOP3DisableFields<0, 0, HasMods>;
971 // No VI instruction. This class is for SI only.
974 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
975 list<dag> pattern, string opName, string revOp,
976 bit HasMods = 1, bit UseFullOp = 0> {
978 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
979 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
981 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
982 VOP3DisableFields<1, 0, HasMods>;
984 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
985 VOP3DisableFields<1, 0, HasMods>;
988 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
989 list<dag> pattern, string opName, string revOp,
990 bit HasMods = 1, bit UseFullOp = 0> {
992 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
993 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
995 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
996 VOP3DisableFields<1, 0, HasMods>;
998 // No VI instruction. This class is for SI only.
1001 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1002 // option of implicit vcc use?
1003 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1004 list<dag> pattern, string opName, string revOp,
1005 bit HasMods = 1, bit UseFullOp = 0> {
1006 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1007 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1009 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1010 // can write it into any SGPR. We currently don't use the carry out,
1011 // so for now hardcode it to VCC as well.
1012 let sdst = SIOperand.VCC, Defs = [VCC] in {
1013 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1014 VOP3DisableFields<1, 0, HasMods>;
1016 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1017 VOP3DisableFields<1, 0, HasMods>;
1018 } // End sdst = SIOperand.VCC, Defs = [VCC]
1021 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1022 list<dag> pattern, string opName, string revOp,
1023 bit HasMods = 1, bit UseFullOp = 0> {
1024 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1027 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1028 VOP3DisableFields<1, 1, HasMods>;
1030 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1031 VOP3DisableFields<1, 1, HasMods>;
1034 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1035 list<dag> pattern, string opName,
1036 bit HasMods, bit defExec> {
1038 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1040 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1041 VOP3DisableFields<1, 0, HasMods> {
1042 let Defs = !if(defExec, [EXEC], []);
1045 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1046 VOP3DisableFields<1, 0, HasMods> {
1047 let Defs = !if(defExec, [EXEC], []);
1051 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1052 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1053 string asm, list<dag> pattern = []> {
1054 let isPseudo = 1 in {
1055 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1056 SIMCInstr<opName, SISubtarget.NONE>;
1059 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1060 SIMCInstr <opName, SISubtarget.SI>;
1062 def _vi : VOP3Common <outs, ins, asm, []>,
1064 VOP3DisableFields <1, 0, 0>,
1065 SIMCInstr <opName, SISubtarget.VI>;
1068 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1069 dag ins32, string asm32, list<dag> pat32,
1070 dag ins64, string asm64, list<dag> pat64,
1073 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1075 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1078 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1079 SDPatternOperator node = null_frag> : VOP1_Helper <
1081 P.Ins32, P.Asm32, [],
1084 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1085 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1086 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1090 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1091 SDPatternOperator node = null_frag> {
1093 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1095 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1097 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1098 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1099 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1100 opName, P.HasModifiers>;
1103 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1104 dag ins32, string asm32, list<dag> pat32,
1105 dag ins64, string asm64, list<dag> pat64,
1106 string revOp, bit HasMods> {
1107 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1109 defm _e64 : VOP3_2_m <op,
1110 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1114 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1115 SDPatternOperator node = null_frag,
1116 string revOp = opName> : VOP2_Helper <
1118 P.Ins32, P.Asm32, [],
1122 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1123 i1:$clamp, i32:$omod)),
1124 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1125 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1126 revOp, P.HasModifiers
1129 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1130 SDPatternOperator node = null_frag,
1131 string revOp = opName> {
1132 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1134 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1137 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1138 i1:$clamp, i32:$omod)),
1139 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1140 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1141 opName, revOp, P.HasModifiers>;
1144 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1145 dag ins32, string asm32, list<dag> pat32,
1146 dag ins64, string asm64, list<dag> pat64,
1147 string revOp, bit HasMods> {
1149 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1151 defm _e64 : VOP3b_2_m <op,
1152 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1156 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1157 SDPatternOperator node = null_frag,
1158 string revOp = opName> : VOP2b_Helper <
1160 P.Ins32, P.Asm32, [],
1164 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1165 i1:$clamp, i32:$omod)),
1166 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1167 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1168 revOp, P.HasModifiers
1171 // A VOP2 instruction that is VOP3-only on VI.
1172 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1173 dag ins32, string asm32, list<dag> pat32,
1174 dag ins64, string asm64, list<dag> pat64,
1175 string revOp, bit HasMods> {
1176 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1178 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1182 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1183 SDPatternOperator node = null_frag,
1184 string revOp = opName>
1187 P.Ins32, P.Asm32, [],
1191 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1192 i1:$clamp, i32:$omod)),
1193 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1194 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1195 revOp, P.HasModifiers
1198 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1199 VOPCCommon <ins, "", pattern>,
1201 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1205 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1206 string opName, bit DefExec> {
1207 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1209 def _si : VOPC<op.SI, ins, asm, []>,
1210 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1211 let Defs = !if(DefExec, [EXEC], []);
1214 def _vi : VOPC<op.VI, ins, asm, []>,
1215 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1216 let Defs = !if(DefExec, [EXEC], []);
1220 multiclass VOPC_Helper <vopc op, string opName,
1221 dag ins32, string asm32, list<dag> pat32,
1222 dag out64, dag ins64, string asm64, list<dag> pat64,
1223 bit HasMods, bit DefExec> {
1224 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1226 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1227 opName, HasMods, DefExec>;
1230 // Special case for class instructions which only have modifiers on
1231 // the 1st source operand.
1232 multiclass VOPC_Class_Helper <vopc op, string opName,
1233 dag ins32, string asm32, list<dag> pat32,
1234 dag out64, dag ins64, string asm64, list<dag> pat64,
1235 bit HasMods, bit DefExec> {
1236 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1238 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1239 opName, HasMods, DefExec>,
1240 VOP3DisableModFields<1, 0, 0>;
1243 multiclass VOPCInst <vopc op, string opName,
1244 VOPProfile P, PatLeaf cond = COND_NULL,
1245 bit DefExec = 0> : VOPC_Helper <
1247 P.Ins32, P.Asm32, [],
1248 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1251 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1252 i1:$clamp, i32:$omod)),
1253 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1255 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1256 P.HasModifiers, DefExec
1259 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1260 bit DefExec = 0> : VOPC_Class_Helper <
1262 P.Ins32, P.Asm32, [],
1263 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1266 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1267 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1268 P.HasModifiers, DefExec
1272 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1273 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1275 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1276 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1278 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1279 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1281 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1282 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1285 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1286 PatLeaf cond = COND_NULL>
1287 : VOPCInst <op, opName, P, cond, 1>;
1289 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1290 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1292 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1293 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1295 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1296 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1298 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1299 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1301 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1302 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1303 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1306 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1307 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1309 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1310 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1312 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1313 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1315 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1316 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1318 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1319 SDPatternOperator node = null_frag> : VOP3_Helper <
1320 op, opName, P.Outs, P.Ins64, P.Asm64,
1321 !if(!eq(P.NumSrcArgs, 3),
1324 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1325 i1:$clamp, i32:$omod)),
1326 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1327 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1328 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1330 !if(!eq(P.NumSrcArgs, 2),
1333 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1334 i1:$clamp, i32:$omod)),
1335 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1336 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1337 /* P.NumSrcArgs == 1 */,
1340 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1341 i1:$clamp, i32:$omod))))],
1342 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1343 P.NumSrcArgs, P.HasModifiers
1346 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1347 // only VOP instruction that implicitly reads VCC.
1348 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1350 SDPatternOperator node = null_frag> : VOP3_Helper <
1353 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1354 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1355 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1358 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1360 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1361 i1:$clamp, i32:$omod)),
1362 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1363 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1368 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1369 string opName, list<dag> pattern> :
1371 op, (outs vrc:$vdst, SReg_64:$sdst),
1372 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1373 InputModsNoDefault:$src1_modifiers, arc:$src1,
1374 InputModsNoDefault:$src2_modifiers, arc:$src2,
1375 ClampMod:$clamp, omod:$omod),
1376 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1377 opName, opName, 1, 1
1380 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1381 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1383 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1384 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1387 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1388 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1389 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1390 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1391 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1392 i32:$src1_modifiers, P.Src1VT:$src1,
1393 i32:$src2_modifiers, P.Src2VT:$src2,
1397 //===----------------------------------------------------------------------===//
1398 // Interpolation opcodes
1399 //===----------------------------------------------------------------------===//
1401 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1402 VINTRPCommon <outs, ins, "", pattern>,
1403 SIMCInstr<opName, SISubtarget.NONE> {
1407 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1409 VINTRPCommon <outs, ins, asm, []>,
1411 SIMCInstr<opName, SISubtarget.SI>;
1413 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1415 VINTRPCommon <outs, ins, asm, []>,
1417 SIMCInstr<opName, SISubtarget.VI>;
1419 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1420 string disableEncoding = "", string constraints = "",
1421 list<dag> pattern = []> {
1422 let DisableEncoding = disableEncoding,
1423 Constraints = constraints in {
1424 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1426 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1428 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1432 //===----------------------------------------------------------------------===//
1433 // Vector I/O classes
1434 //===----------------------------------------------------------------------===//
1436 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1437 DS <outs, ins, "", pattern>,
1438 SIMCInstr <opName, SISubtarget.NONE> {
1442 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1443 DS <outs, ins, asm, []>,
1445 SIMCInstr <opName, SISubtarget.SI>;
1447 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1448 DS <outs, ins, asm, []>,
1450 SIMCInstr <opName, SISubtarget.VI>;
1452 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1453 DS <outs, ins, asm, []>,
1455 SIMCInstr <opName, SISubtarget.SI> {
1457 // Single load interpret the 2 i8imm operands as a single i16 offset.
1459 let offset0 = offset{7-0};
1460 let offset1 = offset{15-8};
1463 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1464 DS <outs, ins, asm, []>,
1466 SIMCInstr <opName, SISubtarget.VI> {
1468 // Single load interpret the 2 i8imm operands as a single i16 offset.
1470 let offset0 = offset{7-0};
1471 let offset1 = offset{15-8};
1474 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1476 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1477 def "" : DS_Pseudo <opName, outs, ins, pat>;
1479 let data0 = 0, data1 = 0 in {
1480 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1481 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1486 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1490 (outs regClass:$vdst),
1491 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1492 asm#" $vdst, $addr"#"$offset"#" [M0]",
1495 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1497 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1498 def "" : DS_Pseudo <opName, outs, ins, pat>;
1500 let data0 = 0, data1 = 0 in {
1501 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1502 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1507 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1511 (outs regClass:$vdst),
1512 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1514 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1517 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1518 string asm, list<dag> pat> {
1519 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1520 def "" : DS_Pseudo <opName, outs, ins, pat>;
1522 let data1 = 0, vdst = 0 in {
1523 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1524 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1529 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1534 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1535 asm#" $addr, $data0"#"$offset"#" [M0]",
1538 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1539 string asm, list<dag> pat> {
1540 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1541 def "" : DS_Pseudo <opName, outs, ins, pat>;
1544 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1545 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1550 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1555 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1556 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1557 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1560 // 1 address, 1 data.
1561 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1562 string asm, list<dag> pat, string noRetOp> {
1563 let mayLoad = 1, mayStore = 1,
1564 hasPostISelHook = 1 // Adjusted to no return version.
1566 def "" : DS_Pseudo <opName, outs, ins, pat>,
1567 AtomicNoRet<noRetOp, 1>;
1570 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1571 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1576 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1577 string noRetOp = ""> : DS_1A1D_RET_m <
1580 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1581 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1583 // 1 address, 2 data.
1584 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1585 string asm, list<dag> pat, string noRetOp> {
1586 let mayLoad = 1, mayStore = 1,
1587 hasPostISelHook = 1 // Adjusted to no return version.
1589 def "" : DS_Pseudo <opName, outs, ins, pat>,
1590 AtomicNoRet<noRetOp, 1>;
1592 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1593 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1597 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1598 string noRetOp = ""> : DS_1A2D_RET_m <
1601 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1602 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1605 // 1 address, 2 data.
1606 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1607 string asm, list<dag> pat, string noRetOp> {
1608 let mayLoad = 1, mayStore = 1 in {
1609 def "" : DS_Pseudo <opName, outs, ins, pat>,
1610 AtomicNoRet<noRetOp, 0>;
1613 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1614 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1619 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1620 string noRetOp = asm> : DS_1A2D_NORET_m <
1623 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1624 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1627 // 1 address, 1 data.
1628 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1629 string asm, list<dag> pat, string noRetOp> {
1630 let mayLoad = 1, mayStore = 1 in {
1631 def "" : DS_Pseudo <opName, outs, ins, pat>,
1632 AtomicNoRet<noRetOp, 0>;
1634 let data1 = 0, vdst = 0 in {
1635 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1636 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1641 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1642 string noRetOp = asm> : DS_1A1D_NORET_m <
1645 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1646 asm#" $addr, $data0"#"$offset"#" [M0]",
1649 //===----------------------------------------------------------------------===//
1651 //===----------------------------------------------------------------------===//
1653 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1654 MTBUF <outs, ins, "", pattern>,
1655 SIMCInstr<opName, SISubtarget.NONE> {
1659 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1661 MTBUF <outs, ins, asm, []>,
1663 SIMCInstr<opName, SISubtarget.SI>;
1665 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1666 MTBUF <outs, ins, asm, []>,
1668 SIMCInstr <opName, SISubtarget.VI>;
1670 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1671 list<dag> pattern> {
1673 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1675 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1677 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1681 let mayStore = 1, mayLoad = 0 in {
1683 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1684 RegisterClass regClass> : MTBUF_m <
1686 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1687 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1688 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1689 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1690 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1693 } // mayStore = 1, mayLoad = 0
1695 let mayLoad = 1, mayStore = 0 in {
1697 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1698 RegisterClass regClass> : MTBUF_m <
1699 op, opName, (outs regClass:$dst),
1700 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1701 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1702 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1703 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1704 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1707 } // mayLoad = 1, mayStore = 0
1709 //===----------------------------------------------------------------------===//
1711 //===----------------------------------------------------------------------===//
1713 class mubuf <bits<7> si, bits<7> vi = si> {
1714 field bits<7> SI = si;
1715 field bits<7> VI = vi;
1718 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1719 bit IsAddr64 = is_addr64;
1720 string OpName = NAME # suffix;
1723 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1724 MUBUF <outs, ins, "", pattern>,
1725 SIMCInstr<opName, SISubtarget.NONE> {
1728 // dummy fields, so that we can use let statements around multiclasses
1738 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1740 MUBUF <outs, ins, asm, []>,
1742 SIMCInstr<opName, SISubtarget.SI> {
1746 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1748 MUBUF <outs, ins, asm, []>,
1750 SIMCInstr<opName, SISubtarget.VI> {
1754 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1755 list<dag> pattern> {
1757 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1758 MUBUFAddr64Table <0>;
1761 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1764 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1767 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1768 dag ins, string asm, list<dag> pattern> {
1770 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1771 MUBUFAddr64Table <1>;
1774 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1777 // There is no VI version. If the pseudo is selected, it should be lowered
1778 // for VI appropriately.
1781 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1782 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1786 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1787 string asm, list<dag> pattern, bit is_return> {
1789 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1790 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1791 AtomicNoRet<NAME#"_OFFSET", is_return>;
1793 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1795 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1798 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1802 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1803 string asm, list<dag> pattern, bit is_return> {
1805 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1806 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1807 AtomicNoRet<NAME#"_ADDR64", is_return>;
1809 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1810 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1813 // There is no VI version. If the pseudo is selected, it should be lowered
1814 // for VI appropriately.
1817 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1818 ValueType vt, SDPatternOperator atomic> {
1820 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1822 // No return variants
1825 defm _ADDR64 : MUBUFAtomicAddr64_m <
1826 op, name#"_addr64", (outs),
1827 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1828 mbuf_offset:$offset, SCSrc_32:$soffset, slc:$slc),
1829 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1832 defm _OFFSET : MUBUFAtomicOffset_m <
1833 op, name#"_offset", (outs),
1834 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1835 SCSrc_32:$soffset, slc:$slc),
1836 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1840 // Variant that return values
1841 let glc = 1, Constraints = "$vdata = $vdata_in",
1842 DisableEncoding = "$vdata_in" in {
1844 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1845 op, name#"_rtn_addr64", (outs rc:$vdata),
1846 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1847 mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
1848 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1850 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1851 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1854 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1855 op, name#"_rtn_offset", (outs rc:$vdata),
1856 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1857 SCSrc_32:$soffset, slc:$slc),
1858 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1860 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1861 i1:$slc), vt:$vdata_in))], 1
1866 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1869 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1870 ValueType load_vt = i32,
1871 SDPatternOperator ld = null_frag> {
1873 let mayLoad = 1, mayStore = 0 in {
1874 let offen = 0, idxen = 0, vaddr = 0 in {
1875 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1876 (ins SReg_128:$srsrc,
1877 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1878 slc:$slc, tfe:$tfe),
1879 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1880 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1881 i32:$soffset, i16:$offset,
1882 i1:$glc, i1:$slc, i1:$tfe)))]>;
1885 let offen = 1, idxen = 0 in {
1886 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1887 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1888 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1890 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1893 let offen = 0, idxen = 1 in {
1894 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1895 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1896 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1897 slc:$slc, tfe:$tfe),
1898 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1901 let offen = 1, idxen = 1 in {
1902 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1903 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1904 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1905 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1908 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1909 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1910 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1911 SCSrc_32:$soffset, mbuf_offset:$offset),
1912 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1913 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1914 i64:$vaddr, i32:$soffset,
1920 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1921 ValueType store_vt, SDPatternOperator st> {
1922 let mayLoad = 0, mayStore = 1 in {
1923 defm : MUBUF_m <op, name, (outs),
1924 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1925 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1927 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1928 "$glc"#"$slc"#"$tfe", []>;
1930 let offen = 0, idxen = 0, vaddr = 0 in {
1931 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1932 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1933 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1934 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1935 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1936 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1937 } // offen = 0, idxen = 0, vaddr = 0
1939 let offen = 1, idxen = 0 in {
1940 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1941 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1942 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1943 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1944 "$glc"#"$slc"#"$tfe", []>;
1945 } // end offen = 1, idxen = 0
1947 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1948 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1949 (ins vdataClass:$vdata, SReg_128:$srsrc,
1950 VReg_64:$vaddr, SCSrc_32:$soffset,
1951 mbuf_offset:$offset),
1952 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1953 [(st store_vt:$vdata,
1954 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1955 i32:$soffset, i16:$offset))]>;
1957 } // End mayLoad = 0, mayStore = 1
1960 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1961 FLAT <op, (outs regClass:$vdst),
1962 (ins VReg_64:$addr),
1963 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
1971 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1972 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1973 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1986 class MIMG_Mask <string op, int channels> {
1988 int Channels = channels;
1991 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1992 RegisterClass dst_rc,
1993 RegisterClass src_rc> : MIMG <
1995 (outs dst_rc:$vdata),
1996 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1997 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1999 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2000 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2005 let hasPostISelHook = 1;
2008 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2009 RegisterClass dst_rc,
2011 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2012 MIMG_Mask<asm#"_V1", channels>;
2013 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2014 MIMG_Mask<asm#"_V2", channels>;
2015 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2016 MIMG_Mask<asm#"_V4", channels>;
2019 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2020 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2021 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2022 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2023 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2026 class MIMG_Sampler_Helper <bits<7> op, string asm,
2027 RegisterClass dst_rc,
2028 RegisterClass src_rc, int wqm> : MIMG <
2030 (outs dst_rc:$vdata),
2031 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2032 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2033 SReg_256:$srsrc, SReg_128:$ssamp),
2034 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2035 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2039 let hasPostISelHook = 1;
2043 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2044 RegisterClass dst_rc,
2045 int channels, int wqm> {
2046 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2047 MIMG_Mask<asm#"_V1", channels>;
2048 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2049 MIMG_Mask<asm#"_V2", channels>;
2050 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2051 MIMG_Mask<asm#"_V4", channels>;
2052 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2053 MIMG_Mask<asm#"_V8", channels>;
2054 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2055 MIMG_Mask<asm#"_V16", channels>;
2058 multiclass MIMG_Sampler <bits<7> op, string asm> {
2059 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2060 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2061 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2062 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2065 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2066 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2067 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2068 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2069 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2072 class MIMG_Gather_Helper <bits<7> op, string asm,
2073 RegisterClass dst_rc,
2074 RegisterClass src_rc, int wqm> : MIMG <
2076 (outs dst_rc:$vdata),
2077 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2078 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2079 SReg_256:$srsrc, SReg_128:$ssamp),
2080 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2081 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2086 // DMASK was repurposed for GATHER4. 4 components are always
2087 // returned and DMASK works like a swizzle - it selects
2088 // the component to fetch. The only useful DMASK values are
2089 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2090 // (red,red,red,red) etc.) The ISA document doesn't mention
2092 // Therefore, disable all code which updates DMASK by setting these two:
2094 let hasPostISelHook = 0;
2098 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2099 RegisterClass dst_rc,
2100 int channels, int wqm> {
2101 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2102 MIMG_Mask<asm#"_V1", channels>;
2103 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2104 MIMG_Mask<asm#"_V2", channels>;
2105 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2106 MIMG_Mask<asm#"_V4", channels>;
2107 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2108 MIMG_Mask<asm#"_V8", channels>;
2109 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2110 MIMG_Mask<asm#"_V16", channels>;
2113 multiclass MIMG_Gather <bits<7> op, string asm> {
2114 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2115 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2116 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2117 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2120 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2121 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2122 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2123 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2124 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2127 //===----------------------------------------------------------------------===//
2128 // Vector instruction mappings
2129 //===----------------------------------------------------------------------===//
2131 // Maps an opcode in e32 form to its e64 equivalent
2132 def getVOPe64 : InstrMapping {
2133 let FilterClass = "VOP";
2134 let RowFields = ["OpName"];
2135 let ColFields = ["Size"];
2137 let ValueCols = [["8"]];
2140 // Maps an opcode in e64 form to its e32 equivalent
2141 def getVOPe32 : InstrMapping {
2142 let FilterClass = "VOP";
2143 let RowFields = ["OpName"];
2144 let ColFields = ["Size"];
2146 let ValueCols = [["4"]];
2149 // Maps an original opcode to its commuted version
2150 def getCommuteRev : InstrMapping {
2151 let FilterClass = "VOP2_REV";
2152 let RowFields = ["RevOp"];
2153 let ColFields = ["IsOrig"];
2155 let ValueCols = [["0"]];
2158 def getMaskedMIMGOp : InstrMapping {
2159 let FilterClass = "MIMG_Mask";
2160 let RowFields = ["Op"];
2161 let ColFields = ["Channels"];
2163 let ValueCols = [["1"], ["2"], ["3"] ];
2166 // Maps an commuted opcode to its original version
2167 def getCommuteOrig : InstrMapping {
2168 let FilterClass = "VOP2_REV";
2169 let RowFields = ["RevOp"];
2170 let ColFields = ["IsOrig"];
2172 let ValueCols = [["1"]];
2175 def getMCOpcodeGen : InstrMapping {
2176 let FilterClass = "SIMCInstr";
2177 let RowFields = ["PseudoInstr"];
2178 let ColFields = ["Subtarget"];
2179 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2180 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2183 def getAddr64Inst : InstrMapping {
2184 let FilterClass = "MUBUFAddr64Table";
2185 let RowFields = ["OpName"];
2186 let ColFields = ["IsAddr64"];
2188 let ValueCols = [["1"]];
2191 // Maps an atomic opcode to its version with a return value.
2192 def getAtomicRetOp : InstrMapping {
2193 let FilterClass = "AtomicNoRet";
2194 let RowFields = ["NoRetOp"];
2195 let ColFields = ["IsRet"];
2197 let ValueCols = [["1"]];
2200 // Maps an atomic opcode to its returnless version.
2201 def getAtomicNoRetOp : InstrMapping {
2202 let FilterClass = "AtomicNoRet";
2203 let RowFields = ["NoRetOp"];
2204 let ColFields = ["IsRet"];
2206 let ValueCols = [["0"]];
2209 include "SIInstructions.td"
2210 include "CIInstructions.td"
2211 include "VIInstructions.td"