1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isVI : Predicate <
12 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
13 AssemblerPredicate<"FeatureGCN3Encoding">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
22 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
23 field bits<8> SI = si;
24 field bits<8> VI = vi;
26 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
30 class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
34 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
38 class vop2 <bits<6> si, bits<6> vi = si> : vop {
39 field bits<6> SI = si;
40 field bits<6> VI = vi;
42 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
48 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
52 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
57 class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
62 class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
67 class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
72 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
73 // in AMDGPUInstrInfo.cpp
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
85 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
86 [SDNPMayLoad, SDNPMemOperand]
89 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
91 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
92 SDTCisVT<1, iAny>, // vdata(VGPR)
93 SDTCisVT<2, i32>, // num_channels(imm)
94 SDTCisVT<3, i32>, // vaddr(VGPR)
95 SDTCisVT<4, i32>, // soffset(SGPR)
96 SDTCisVT<5, i32>, // inst_offset(imm)
97 SDTCisVT<6, i32>, // dfmt(imm)
98 SDTCisVT<7, i32>, // nfmt(imm)
99 SDTCisVT<8, i32>, // offen(imm)
100 SDTCisVT<9, i32>, // idxen(imm)
101 SDTCisVT<10, i32>, // glc(imm)
102 SDTCisVT<11, i32>, // slc(imm)
103 SDTCisVT<12, i32> // tfe(imm)
105 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
108 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
109 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
113 class SDSample<string opcode> : SDNode <opcode,
114 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
115 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
118 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
119 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
120 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
121 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
123 def SIconstdata_ptr : SDNode<
124 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
127 // Transformation function, extract the lower 32bit of a 64bit immediate
128 def LO32 : SDNodeXForm<imm, [{
129 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
133 def LO32f : SDNodeXForm<fpimm, [{
134 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
135 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
138 // Transformation function, extract the upper 32bit of a 64bit immediate
139 def HI32 : SDNodeXForm<imm, [{
140 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
143 def HI32f : SDNodeXForm<fpimm, [{
144 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
145 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
149 def IMM8bitDWORD : PatLeaf <(imm),
150 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
153 def as_dword_i32imm : SDNodeXForm<imm, [{
154 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
157 def as_i1imm : SDNodeXForm<imm, [{
158 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
161 def as_i8imm : SDNodeXForm<imm, [{
162 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
165 def as_i16imm : SDNodeXForm<imm, [{
166 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
169 def as_i32imm: SDNodeXForm<imm, [{
170 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
173 def as_i64imm: SDNodeXForm<imm, [{
174 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
177 // Copied from the AArch64 backend:
178 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
179 return CurDAG->getTargetConstant(
180 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
183 // Copied from the AArch64 backend:
184 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
185 return CurDAG->getTargetConstant(
186 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
189 def IMM8bit : PatLeaf <(imm),
190 [{return isUInt<8>(N->getZExtValue());}]
193 def IMM12bit : PatLeaf <(imm),
194 [{return isUInt<12>(N->getZExtValue());}]
197 def IMM16bit : PatLeaf <(imm),
198 [{return isUInt<16>(N->getZExtValue());}]
201 def IMM20bit : PatLeaf <(imm),
202 [{return isUInt<20>(N->getZExtValue());}]
205 def IMM32bit : PatLeaf <(imm),
206 [{return isUInt<32>(N->getZExtValue());}]
209 def mubuf_vaddr_offset : PatFrag<
210 (ops node:$ptr, node:$offset, node:$imm_offset),
211 (add (add node:$ptr, node:$offset), node:$imm_offset)
214 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
215 return isInlineImmediate(N);
218 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
219 return isInlineImmediate(N);
222 class SGPRImm <dag frag> : PatLeaf<frag, [{
223 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
226 const SIRegisterInfo *SIRI =
227 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
228 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
230 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
241 def FRAMEri32 : Operand<iPTR> {
242 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
245 def SoppBrTarget : AsmOperandClass {
246 let Name = "SoppBrTarget";
247 let ParserMethod = "parseSOppBrTarget";
250 def sopp_brtarget : Operand<OtherVT> {
251 let EncoderMethod = "getSOPPBrEncoding";
252 let OperandType = "OPERAND_PCREL";
253 let ParserMatchClass = SoppBrTarget;
256 include "SIInstrFormats.td"
257 include "VIInstrFormats.td"
259 def MubufOffsetMatchClass : AsmOperandClass {
260 let Name = "MubufOffset";
261 let ParserMethod = "parseMubufOptionalOps";
262 let RenderMethod = "addImmOperands";
265 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
266 let Name = "DSOffset"#parser;
267 let ParserMethod = parser;
268 let RenderMethod = "addImmOperands";
269 let PredicateMethod = "isDSOffset";
272 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
273 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
275 def DSOffset01MatchClass : AsmOperandClass {
276 let Name = "DSOffset1";
277 let ParserMethod = "parseDSOff01OptionalOps";
278 let RenderMethod = "addImmOperands";
279 let PredicateMethod = "isDSOffset01";
282 class GDSBaseMatchClass <string parser> : AsmOperandClass {
283 let Name = "GDS"#parser;
284 let PredicateMethod = "isImm";
285 let ParserMethod = parser;
286 let RenderMethod = "addImmOperands";
289 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
290 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
292 def GLCMatchClass : AsmOperandClass {
294 let PredicateMethod = "isImm";
295 let ParserMethod = "parseMubufOptionalOps";
296 let RenderMethod = "addImmOperands";
299 def SLCMatchClass : AsmOperandClass {
301 let PredicateMethod = "isImm";
302 let ParserMethod = "parseMubufOptionalOps";
303 let RenderMethod = "addImmOperands";
306 def TFEMatchClass : AsmOperandClass {
308 let PredicateMethod = "isImm";
309 let ParserMethod = "parseMubufOptionalOps";
310 let RenderMethod = "addImmOperands";
313 def OModMatchClass : AsmOperandClass {
315 let PredicateMethod = "isImm";
316 let ParserMethod = "parseVOP3OptionalOps";
317 let RenderMethod = "addImmOperands";
320 def ClampMatchClass : AsmOperandClass {
322 let PredicateMethod = "isImm";
323 let ParserMethod = "parseVOP3OptionalOps";
324 let RenderMethod = "addImmOperands";
327 let OperandType = "OPERAND_IMMEDIATE" in {
329 def offen : Operand<i1> {
330 let PrintMethod = "printOffen";
332 def idxen : Operand<i1> {
333 let PrintMethod = "printIdxen";
335 def addr64 : Operand<i1> {
336 let PrintMethod = "printAddr64";
338 def mbuf_offset : Operand<i16> {
339 let PrintMethod = "printMBUFOffset";
340 let ParserMatchClass = MubufOffsetMatchClass;
342 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
343 let PrintMethod = "printDSOffset";
344 let ParserMatchClass = mc;
346 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
347 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
349 def ds_offset0 : Operand<i8> {
350 let PrintMethod = "printDSOffset0";
351 let ParserMatchClass = DSOffset01MatchClass;
353 def ds_offset1 : Operand<i8> {
354 let PrintMethod = "printDSOffset1";
355 let ParserMatchClass = DSOffset01MatchClass;
357 class gds_base <AsmOperandClass mc> : Operand <i1> {
358 let PrintMethod = "printGDS";
359 let ParserMatchClass = mc;
361 def gds : gds_base <GDSMatchClass>;
363 def gds01 : gds_base <GDS01MatchClass>;
365 def glc : Operand <i1> {
366 let PrintMethod = "printGLC";
367 let ParserMatchClass = GLCMatchClass;
369 def slc : Operand <i1> {
370 let PrintMethod = "printSLC";
371 let ParserMatchClass = SLCMatchClass;
373 def tfe : Operand <i1> {
374 let PrintMethod = "printTFE";
375 let ParserMatchClass = TFEMatchClass;
378 def omod : Operand <i32> {
379 let PrintMethod = "printOModSI";
380 let ParserMatchClass = OModMatchClass;
383 def ClampMod : Operand <i1> {
384 let PrintMethod = "printClampSI";
385 let ParserMatchClass = ClampMatchClass;
388 } // End OperandType = "OPERAND_IMMEDIATE"
390 def VOPDstS64 : VOPDstOperand <SReg_64>;
392 //===----------------------------------------------------------------------===//
394 //===----------------------------------------------------------------------===//
396 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
397 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
399 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
400 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
401 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
402 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
403 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
404 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
406 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
407 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
408 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
409 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
411 //===----------------------------------------------------------------------===//
412 // SI assembler operands
413 //===----------------------------------------------------------------------===//
434 //===----------------------------------------------------------------------===//
436 // SI Instruction multiclass helpers.
438 // Instructions with _32 take 32-bit operands.
439 // Instructions with _64 take 64-bit operands.
441 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
442 // encoding is the standard encoding, but instruction that make use of
443 // any of the instruction modifiers must use the 64-bit encoding.
445 // Instructions with _e32 use the 32-bit encoding.
446 // Instructions with _e64 use the 64-bit encoding.
448 //===----------------------------------------------------------------------===//
450 class SIMCInstr <string pseudo, int subtarget> {
451 string PseudoInstr = pseudo;
452 int Subtarget = subtarget;
455 //===----------------------------------------------------------------------===//
457 //===----------------------------------------------------------------------===//
459 class EXPCommon : InstSI<
461 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
462 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
463 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
472 let isPseudo = 1, isCodeGenOnly = 1 in {
473 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
476 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
478 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
481 //===----------------------------------------------------------------------===//
483 //===----------------------------------------------------------------------===//
485 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
486 SOP1 <outs, ins, "", pattern>,
487 SIMCInstr<opName, SISubtarget.NONE> {
489 let isCodeGenOnly = 1;
492 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
493 SOP1 <outs, ins, asm, []>,
495 SIMCInstr<opName, SISubtarget.SI> {
496 let isCodeGenOnly = 0;
497 let AssemblerPredicates = [isSICI];
500 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
501 SOP1 <outs, ins, asm, []>,
503 SIMCInstr<opName, SISubtarget.VI> {
504 let isCodeGenOnly = 0;
505 let AssemblerPredicates = [isVI];
508 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
511 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
513 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
515 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
519 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
520 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
521 opName#" $dst, $src0", pattern
524 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
525 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
526 opName#" $dst, $src0", pattern
529 // no input, 64-bit output.
530 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
531 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
533 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
538 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
544 // 64-bit input, no output
545 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
546 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
548 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
553 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
559 // 64-bit input, 32-bit output.
560 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
561 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
562 opName#" $dst, $src0", pattern
565 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
566 SOP2<outs, ins, "", pattern>,
567 SIMCInstr<opName, SISubtarget.NONE> {
569 let isCodeGenOnly = 1;
572 // Pseudo instructions have no encodings, but adding this field here allows
574 // let sdst = xxx in {
575 // for multiclasses that include both real and pseudo instructions.
576 field bits<7> sdst = 0;
579 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
580 SOP2<outs, ins, asm, []>,
582 SIMCInstr<opName, SISubtarget.SI> {
583 let AssemblerPredicates = [isSICI];
586 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
587 SOP2<outs, ins, asm, []>,
589 SIMCInstr<opName, SISubtarget.VI> {
590 let AssemblerPredicates = [isVI];
593 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
594 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
595 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
597 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
598 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
599 opName#" $dst, $src0, $src1 [$scc]">;
601 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
602 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
603 opName#" $dst, $src0, $src1 [$scc]">;
606 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
609 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
611 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
613 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
617 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
618 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
619 opName#" $dst, $src0, $src1", pattern
622 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
623 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
624 opName#" $dst, $src0, $src1", pattern
627 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
628 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
629 opName#" $dst, $src0, $src1", pattern
632 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
633 string opName, PatLeaf cond> : SOPC <
634 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
635 opName#" $src0, $src1", []>;
637 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
638 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
640 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
641 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
643 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
644 SOPK <outs, ins, "", pattern>,
645 SIMCInstr<opName, SISubtarget.NONE> {
647 let isCodeGenOnly = 1;
650 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
651 SOPK <outs, ins, asm, []>,
653 SIMCInstr<opName, SISubtarget.SI> {
654 let AssemblerPredicates = [isSICI];
655 let isCodeGenOnly = 0;
658 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
659 SOPK <outs, ins, asm, []>,
661 SIMCInstr<opName, SISubtarget.VI> {
662 let AssemblerPredicates = [isVI];
663 let isCodeGenOnly = 0;
666 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
667 string asm = opName#opAsm> {
668 def "" : SOPK_Pseudo <opName, outs, ins, []>;
670 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
672 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
676 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
677 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
680 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
681 opName#" $dst, $src0">;
683 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
684 opName#" $dst, $src0">;
687 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
688 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
689 (ins SReg_32:$src0, u16imm:$src1), pattern>;
691 let DisableEncoding = "$dst" in {
692 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
693 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
695 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
696 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
700 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
701 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
705 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
706 string argAsm, string asm = opName#argAsm> {
708 def "" : SOPK_Pseudo <opName, outs, ins, []>;
710 def _si : SOPK <outs, ins, asm, []>,
712 SIMCInstr<opName, SISubtarget.SI> {
713 let AssemblerPredicates = [isSICI];
714 let isCodeGenOnly = 0;
717 def _vi : SOPK <outs, ins, asm, []>,
719 SIMCInstr<opName, SISubtarget.VI> {
720 let AssemblerPredicates = [isVI];
721 let isCodeGenOnly = 0;
724 //===----------------------------------------------------------------------===//
726 //===----------------------------------------------------------------------===//
728 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
729 SMRD <outs, ins, "", pattern>,
730 SIMCInstr<opName, SISubtarget.NONE> {
732 let isCodeGenOnly = 1;
735 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
737 SMRD <outs, ins, asm, []>,
739 SIMCInstr<opName, SISubtarget.SI> {
740 let AssemblerPredicates = [isSICI];
743 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
745 SMRD <outs, ins, asm, []>,
747 SIMCInstr<opName, SISubtarget.VI> {
748 let AssemblerPredicates = [isVI];
751 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
752 string asm, list<dag> pattern> {
754 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
756 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
758 // glc is only applicable to scalar stores, which are not yet
761 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
765 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
766 RegisterClass dstClass> {
768 op, opName#"_IMM", 1, (outs dstClass:$dst),
769 (ins baseClass:$sbase, u32imm:$offset),
770 opName#" $dst, $sbase, $offset", []
773 defm _SGPR : SMRD_m <
774 op, opName#"_SGPR", 0, (outs dstClass:$dst),
775 (ins baseClass:$sbase, SReg_32:$soff),
776 opName#" $dst, $sbase, $soff", []
780 //===----------------------------------------------------------------------===//
781 // Vector ALU classes
782 //===----------------------------------------------------------------------===//
784 // This must always be right before the operand being input modified.
785 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
786 let PrintMethod = "printOperandAndMods";
789 def InputModsMatchClass : AsmOperandClass {
790 let Name = "RegWithInputMods";
793 def InputModsNoDefault : Operand <i32> {
794 let PrintMethod = "printOperandAndMods";
795 let ParserMatchClass = InputModsMatchClass;
798 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
800 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
801 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
805 // Returns the register class to use for the destination of VOP[123C]
806 // instructions for the given VT.
807 class getVALUDstForVT<ValueType VT> {
808 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
809 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
810 VOPDstOperand<SReg_64>)); // else VT == i1
813 // Returns the register class to use for source 0 of VOP[12C]
814 // instructions for the given VT.
815 class getVOPSrc0ForVT<ValueType VT> {
816 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
819 // Returns the register class to use for source 1 of VOP[12C] for the
821 class getVOPSrc1ForVT<ValueType VT> {
822 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
825 // Returns the register class to use for sources of VOP3 instructions for the
827 class getVOP3SrcForVT<ValueType VT> {
828 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
831 // Returns 1 if the source arguments have modifiers, 0 if they do not.
832 class hasModifiers<ValueType SrcVT> {
833 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
834 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
837 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
838 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
839 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
840 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
844 // Returns the input arguments for VOP3 instructions for the given SrcVT.
845 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
846 RegisterOperand Src2RC, int NumSrcArgs,
850 !if (!eq(NumSrcArgs, 1),
851 !if (!eq(HasModifiers, 1),
852 // VOP1 with modifiers
853 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
854 ClampMod:$clamp, omod:$omod)
856 // VOP1 without modifiers
859 !if (!eq(NumSrcArgs, 2),
860 !if (!eq(HasModifiers, 1),
861 // VOP 2 with modifiers
862 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
863 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
864 ClampMod:$clamp, omod:$omod)
866 // VOP2 without modifiers
867 (ins Src0RC:$src0, Src1RC:$src1)
869 /* NumSrcArgs == 3 */,
870 !if (!eq(HasModifiers, 1),
871 // VOP3 with modifiers
872 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
873 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
874 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
875 ClampMod:$clamp, omod:$omod)
877 // VOP3 without modifiers
878 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
882 // Returns the assembly string for the inputs and outputs of a VOP[12C]
883 // instruction. This does not add the _e32 suffix, so it can be reused
885 class getAsm32 <int NumSrcArgs> {
886 string src1 = ", $src1";
887 string src2 = ", $src2";
888 string ret = "$dst, $src0"#
889 !if(!eq(NumSrcArgs, 1), "", src1)#
890 !if(!eq(NumSrcArgs, 3), src2, "");
893 // Returns the assembly string for the inputs and outputs of a VOP3
895 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
896 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
897 string src1 = !if(!eq(NumSrcArgs, 1), "",
898 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
899 " $src1_modifiers,"));
900 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
902 !if(!eq(HasModifiers, 0),
903 getAsm32<NumSrcArgs>.ret,
904 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
908 class VOPProfile <list<ValueType> _ArgVT> {
910 field list<ValueType> ArgVT = _ArgVT;
912 field ValueType DstVT = ArgVT[0];
913 field ValueType Src0VT = ArgVT[1];
914 field ValueType Src1VT = ArgVT[2];
915 field ValueType Src2VT = ArgVT[3];
916 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
917 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
918 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
919 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
920 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
921 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
923 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
924 field bit HasModifiers = hasModifiers<Src0VT>.ret;
926 field dag Outs = (outs DstRC:$dst);
928 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
929 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
932 field string Asm32 = getAsm32<NumSrcArgs>.ret;
933 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
936 // FIXME: I think these F16 profiles will need to use f16 types in order
937 // for the instruction patterns to work.
938 def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
939 def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
940 def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
942 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
943 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
944 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
945 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
946 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
947 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
948 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
949 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
950 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
952 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
953 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
954 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
955 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
956 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
957 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
958 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
959 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
960 let Src0RC32 = VCSrc_32;
963 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
964 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
965 let Asm64 = "$dst, $src0_modifiers, $src1";
968 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
969 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
970 let Asm64 = "$dst, $src0_modifiers, $src1";
973 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
974 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
975 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
976 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
977 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
978 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
979 let Asm64 = "$dst, $src0, $src1, $src2";
982 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
983 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
984 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
985 field string Asm = "$dst, $src0, $vsrc1, $src2";
987 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
988 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
989 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
992 class VOP <string opName> {
993 string OpName = opName;
996 class VOP2_REV <string revOp, bit isOrig> {
997 string RevOp = revOp;
1001 class AtomicNoRet <string noRetOp, bit isRet> {
1002 string NoRetOp = noRetOp;
1006 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1007 VOP1Common <outs, ins, "", pattern>,
1009 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1010 MnemonicAlias<opName#"_e32", opName> {
1012 let isCodeGenOnly = 1;
1018 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1019 VOP1<op.SI, outs, ins, asm, []>,
1020 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1021 let AssemblerPredicate = SIAssemblerPredicate;
1024 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1025 VOP1<op.VI, outs, ins, asm, []>,
1026 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1027 let AssemblerPredicates = [isVI];
1030 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1032 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1034 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1036 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1039 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1041 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1043 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1046 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1047 VOP2Common <outs, ins, "", pattern>,
1049 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1050 MnemonicAlias<opName#"_e32", opName> {
1052 let isCodeGenOnly = 1;
1055 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1056 VOP2 <op.SI, outs, ins, opName#asm, []>,
1057 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1058 let AssemblerPredicates = [isSICI];
1061 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1062 VOP2 <op.VI, outs, ins, opName#asm, []>,
1063 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1064 let AssemblerPredicates = [isVI];
1067 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1068 string opName, string revOp> {
1069 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1070 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1072 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1075 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1076 string opName, string revOp> {
1077 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1078 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1080 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1082 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1086 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1088 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1089 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1090 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1091 bits<2> omod = !if(HasModifiers, ?, 0);
1092 bits<1> clamp = !if(HasModifiers, ?, 0);
1093 bits<9> src1 = !if(HasSrc1, ?, 0);
1094 bits<9> src2 = !if(HasSrc2, ?, 0);
1097 class VOP3DisableModFields <bit HasSrc0Mods,
1098 bit HasSrc1Mods = 0,
1099 bit HasSrc2Mods = 0,
1100 bit HasOutputMods = 0> {
1101 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1102 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1103 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1104 bits<2> omod = !if(HasOutputMods, ?, 0);
1105 bits<1> clamp = !if(HasOutputMods, ?, 0);
1108 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1109 VOP3Common <outs, ins, "", pattern>,
1111 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1112 MnemonicAlias<opName#"_e64", opName> {
1114 let isCodeGenOnly = 1;
1117 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1118 VOP3Common <outs, ins, asm, []>,
1120 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1121 let AssemblerPredicates = [isSICI];
1124 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1125 VOP3Common <outs, ins, asm, []>,
1127 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1128 let AssemblerPredicates = [isVI];
1131 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1132 VOP3Common <outs, ins, asm, []>,
1134 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1135 let AssemblerPredicates = [isSICI];
1138 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1139 VOP3Common <outs, ins, asm, []>,
1141 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1142 let AssemblerPredicates = [isVI];
1145 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1146 string opName, int NumSrcArgs, bit HasMods = 1> {
1148 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1150 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1151 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1152 !if(!eq(NumSrcArgs, 2), 0, 1),
1154 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1155 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1156 !if(!eq(NumSrcArgs, 2), 0, 1),
1160 // VOP3_m without source modifiers
1161 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1162 string opName, int NumSrcArgs, bit HasMods = 1> {
1164 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1166 let src0_modifiers = 0,
1171 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1172 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1176 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1177 list<dag> pattern, string opName, bit HasMods = 1> {
1179 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1181 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1182 VOP3DisableFields<0, 0, HasMods>;
1184 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1185 VOP3DisableFields<0, 0, HasMods>;
1188 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1189 list<dag> pattern, string opName, bit HasMods = 1> {
1191 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1193 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1194 VOP3DisableFields<0, 0, HasMods>;
1195 // No VI instruction. This class is for SI only.
1198 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1199 list<dag> pattern, string opName, string revOp,
1200 bit HasMods = 1, bit UseFullOp = 0> {
1202 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1203 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1205 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1206 VOP3DisableFields<1, 0, HasMods>;
1208 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1209 VOP3DisableFields<1, 0, HasMods>;
1212 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1213 list<dag> pattern, string opName, string revOp,
1214 bit HasMods = 1, bit UseFullOp = 0> {
1216 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1217 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1219 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1220 VOP3DisableFields<1, 0, HasMods>;
1222 // No VI instruction. This class is for SI only.
1225 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1226 // option of implicit vcc use?
1227 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1228 list<dag> pattern, string opName, string revOp,
1229 bit HasMods = 1, bit UseFullOp = 0> {
1230 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1231 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1233 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1234 // can write it into any SGPR. We currently don't use the carry out,
1235 // so for now hardcode it to VCC as well.
1236 let sdst = SIOperand.VCC, Defs = [VCC] in {
1237 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1238 VOP3DisableFields<1, 0, HasMods>;
1240 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1241 VOP3DisableFields<1, 0, HasMods>;
1242 } // End sdst = SIOperand.VCC, Defs = [VCC]
1245 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1246 list<dag> pattern, string opName, string revOp,
1247 bit HasMods = 1, bit UseFullOp = 0> {
1248 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1251 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1252 VOP3DisableFields<1, 1, HasMods>;
1254 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1255 VOP3DisableFields<1, 1, HasMods>;
1258 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1259 list<dag> pattern, string opName,
1260 bit HasMods, bit defExec, string revOp> {
1262 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1263 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1265 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1266 VOP3DisableFields<1, 0, HasMods> {
1267 let Defs = !if(defExec, [EXEC], []);
1270 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1271 VOP3DisableFields<1, 0, HasMods> {
1272 let Defs = !if(defExec, [EXEC], []);
1276 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1277 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1278 string asm, list<dag> pattern = []> {
1279 let isPseudo = 1, isCodeGenOnly = 1 in {
1280 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1281 SIMCInstr<opName, SISubtarget.NONE>;
1284 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1285 SIMCInstr <opName, SISubtarget.SI> {
1286 let AssemblerPredicates = [isSICI];
1289 def _vi : VOP3Common <outs, ins, asm, []>,
1291 VOP3DisableFields <1, 0, 0>,
1292 SIMCInstr <opName, SISubtarget.VI> {
1293 let AssemblerPredicates = [isVI];
1297 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1298 dag ins32, string asm32, list<dag> pat32,
1299 dag ins64, string asm64, list<dag> pat64,
1302 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1304 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1307 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1308 SDPatternOperator node = null_frag> : VOP1_Helper <
1310 P.Ins32, P.Asm32, [],
1313 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1314 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1315 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1319 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1320 SDPatternOperator node = null_frag> {
1322 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1324 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1326 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1327 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1328 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1329 opName, P.HasModifiers>;
1332 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1333 dag ins32, string asm32, list<dag> pat32,
1334 dag ins64, string asm64, list<dag> pat64,
1335 string revOp, bit HasMods> {
1336 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1338 defm _e64 : VOP3_2_m <op,
1339 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1343 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1344 SDPatternOperator node = null_frag,
1345 string revOp = opName> : VOP2_Helper <
1347 P.Ins32, P.Asm32, [],
1351 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1352 i1:$clamp, i32:$omod)),
1353 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1354 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1355 revOp, P.HasModifiers
1358 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1359 SDPatternOperator node = null_frag,
1360 string revOp = opName> {
1361 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1363 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1366 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1367 i1:$clamp, i32:$omod)),
1368 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1369 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1370 opName, revOp, P.HasModifiers>;
1373 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1374 dag ins32, string asm32, list<dag> pat32,
1375 dag ins64, string asm64, list<dag> pat64,
1376 string revOp, bit HasMods> {
1378 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1380 defm _e64 : VOP3b_2_m <op,
1381 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1385 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1386 SDPatternOperator node = null_frag,
1387 string revOp = opName> : VOP2b_Helper <
1389 P.Ins32, P.Asm32, [],
1393 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1394 i1:$clamp, i32:$omod)),
1395 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1396 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1397 revOp, P.HasModifiers
1400 // A VOP2 instruction that is VOP3-only on VI.
1401 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1402 dag ins32, string asm32, list<dag> pat32,
1403 dag ins64, string asm64, list<dag> pat64,
1404 string revOp, bit HasMods> {
1405 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1407 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1411 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1412 SDPatternOperator node = null_frag,
1413 string revOp = opName>
1416 P.Ins32, P.Asm32, [],
1420 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1421 i1:$clamp, i32:$omod)),
1422 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1423 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1424 revOp, P.HasModifiers
1427 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1429 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1431 let isCodeGenOnly = 0 in {
1432 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1433 !strconcat(opName, VOP_MADK.Asm), []>,
1434 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1437 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1438 !strconcat(opName, VOP_MADK.Asm), []>,
1439 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1441 } // End isCodeGenOnly = 0
1444 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1445 VOPCCommon <ins, "", pattern>,
1447 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1448 MnemonicAlias<opName#"_e32", opName> {
1450 let isCodeGenOnly = 1;
1453 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1454 string opName, bit DefExec, string revOpName = ""> {
1455 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1457 def _si : VOPC<op.SI, ins, asm, []>,
1458 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1459 let Defs = !if(DefExec, [EXEC], []);
1460 let hasSideEffects = DefExec;
1463 def _vi : VOPC<op.VI, ins, asm, []>,
1464 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1465 let Defs = !if(DefExec, [EXEC], []);
1466 let hasSideEffects = DefExec;
1470 multiclass VOPC_Helper <vopc op, string opName,
1471 dag ins32, string asm32, list<dag> pat32,
1472 dag out64, dag ins64, string asm64, list<dag> pat64,
1473 bit HasMods, bit DefExec, string revOp> {
1474 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1476 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1477 opName, HasMods, DefExec, revOp>;
1480 // Special case for class instructions which only have modifiers on
1481 // the 1st source operand.
1482 multiclass VOPC_Class_Helper <vopc op, string opName,
1483 dag ins32, string asm32, list<dag> pat32,
1484 dag out64, dag ins64, string asm64, list<dag> pat64,
1485 bit HasMods, bit DefExec, string revOp> {
1486 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1488 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1489 opName, HasMods, DefExec, revOp>,
1490 VOP3DisableModFields<1, 0, 0>;
1493 multiclass VOPCInst <vopc op, string opName,
1494 VOPProfile P, PatLeaf cond = COND_NULL,
1495 string revOp = opName,
1496 bit DefExec = 0> : VOPC_Helper <
1498 P.Ins32, P.Asm32, [],
1499 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1502 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1503 i1:$clamp, i32:$omod)),
1504 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1506 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1507 P.HasModifiers, DefExec, revOp
1510 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1511 bit DefExec = 0> : VOPC_Class_Helper <
1513 P.Ins32, P.Asm32, [],
1514 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1517 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1518 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1519 P.HasModifiers, DefExec, opName
1523 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1524 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1526 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1527 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1529 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1530 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1532 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1533 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1536 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1537 PatLeaf cond = COND_NULL,
1539 : VOPCInst <op, opName, P, cond, revOp, 1>;
1541 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1542 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1544 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1545 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1547 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1548 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1550 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1551 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1553 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1554 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1555 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1558 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1559 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1561 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1562 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1564 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1565 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1567 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1568 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1570 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1571 SDPatternOperator node = null_frag> : VOP3_Helper <
1572 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1573 !if(!eq(P.NumSrcArgs, 3),
1576 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1577 i1:$clamp, i32:$omod)),
1578 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1579 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1580 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1582 !if(!eq(P.NumSrcArgs, 2),
1585 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1586 i1:$clamp, i32:$omod)),
1587 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1588 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1589 /* P.NumSrcArgs == 1 */,
1592 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1593 i1:$clamp, i32:$omod))))],
1594 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1595 P.NumSrcArgs, P.HasModifiers
1598 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1599 // only VOP instruction that implicitly reads VCC.
1600 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1602 SDPatternOperator node = null_frag> : VOP3_Helper <
1604 (outs P.DstRC.RegClass:$dst),
1605 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1606 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1607 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1610 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1612 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1613 i1:$clamp, i32:$omod)),
1614 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1615 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1620 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1621 string opName, list<dag> pattern> :
1623 op, (outs vrc:$vdst, SReg_64:$sdst),
1624 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1625 InputModsNoDefault:$src1_modifiers, arc:$src1,
1626 InputModsNoDefault:$src2_modifiers, arc:$src2,
1627 ClampMod:$clamp, omod:$omod),
1628 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1629 opName, opName, 1, 1
1632 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1633 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1635 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1636 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1639 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1640 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1641 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1642 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1643 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1644 i32:$src1_modifiers, P.Src1VT:$src1,
1645 i32:$src2_modifiers, P.Src2VT:$src2,
1649 //===----------------------------------------------------------------------===//
1650 // Interpolation opcodes
1651 //===----------------------------------------------------------------------===//
1653 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1654 VINTRPCommon <outs, ins, "", pattern>,
1655 SIMCInstr<opName, SISubtarget.NONE> {
1657 let isCodeGenOnly = 1;
1660 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1662 VINTRPCommon <outs, ins, asm, []>,
1664 SIMCInstr<opName, SISubtarget.SI>;
1666 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1668 VINTRPCommon <outs, ins, asm, []>,
1670 SIMCInstr<opName, SISubtarget.VI>;
1672 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1673 string disableEncoding = "", string constraints = "",
1674 list<dag> pattern = []> {
1675 let DisableEncoding = disableEncoding,
1676 Constraints = constraints in {
1677 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1679 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1681 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1685 //===----------------------------------------------------------------------===//
1686 // Vector I/O classes
1687 //===----------------------------------------------------------------------===//
1689 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1690 DS <outs, ins, "", pattern>,
1691 SIMCInstr <opName, SISubtarget.NONE> {
1693 let isCodeGenOnly = 1;
1696 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1697 DS <outs, ins, asm, []>,
1699 SIMCInstr <opName, SISubtarget.SI> {
1700 let isCodeGenOnly = 0;
1703 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1704 DS <outs, ins, asm, []>,
1706 SIMCInstr <opName, SISubtarget.VI>;
1708 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1709 DS_Real_si <op,opName, outs, ins, asm> {
1711 // Single load interpret the 2 i8imm operands as a single i16 offset.
1713 let offset0 = offset{7-0};
1714 let offset1 = offset{15-8};
1715 let isCodeGenOnly = 0;
1718 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1719 DS_Real_vi <op, opName, outs, ins, asm> {
1721 // Single load interpret the 2 i8imm operands as a single i16 offset.
1723 let offset0 = offset{7-0};
1724 let offset1 = offset{15-8};
1727 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1728 dag outs = (outs rc:$vdst),
1729 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1730 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1732 def "" : DS_Pseudo <opName, outs, ins, []>;
1734 let data0 = 0, data1 = 0 in {
1735 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1736 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1740 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1741 dag outs = (outs rc:$vdst),
1742 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1743 gds01:$gds, M0Reg:$m0),
1744 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1746 def "" : DS_Pseudo <opName, outs, ins, []>;
1748 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1749 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1750 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1754 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1756 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1758 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1760 def "" : DS_Pseudo <opName, outs, ins, []>,
1761 AtomicNoRet<opName, 0>;
1763 let data1 = 0, vdst = 0 in {
1764 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1765 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1769 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1771 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1772 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds, M0Reg:$m0),
1773 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1775 def "" : DS_Pseudo <opName, outs, ins, []>;
1777 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1778 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1779 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1783 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1784 string noRetOp = "",
1785 dag outs = (outs rc:$vdst),
1786 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1788 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1790 def "" : DS_Pseudo <opName, outs, ins, []>,
1791 AtomicNoRet<noRetOp, 1>;
1794 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1795 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1799 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1800 string noRetOp = "", dag ins,
1801 dag outs = (outs rc:$vdst),
1802 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1804 def "" : DS_Pseudo <opName, outs, ins, []>,
1805 AtomicNoRet<noRetOp, 1>;
1807 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1808 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1811 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1812 string noRetOp = "", RegisterClass src = rc> :
1813 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1814 (ins VGPR_32:$addr, src:$data0, src:$data1,
1815 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1818 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1819 string noRetOp = opName,
1821 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1822 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1823 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1825 def "" : DS_Pseudo <opName, outs, ins, []>,
1826 AtomicNoRet<noRetOp, 0>;
1829 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1830 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1834 multiclass DS_0A_RET <bits<8> op, string opName,
1835 dag outs = (outs VGPR_32:$vdst),
1836 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1837 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1839 let mayLoad = 1, mayStore = 1 in {
1840 def "" : DS_Pseudo <opName, outs, ins, []>;
1842 let addr = 0, data0 = 0, data1 = 0 in {
1843 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1844 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1845 } // end addr = 0, data0 = 0, data1 = 0
1846 } // end mayLoad = 1, mayStore = 1
1849 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1850 dag outs = (outs VGPR_32:$vdst),
1851 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset, M0Reg:$m0),
1852 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1854 def "" : DS_Pseudo <opName, outs, ins, []>;
1856 let data0 = 0, data1 = 0, gds = 1 in {
1857 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1858 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1859 } // end data0 = 0, data1 = 0, gds = 1
1862 multiclass DS_1A_GDS <bits<8> op, string opName,
1864 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1865 string asm = opName#" $addr gds"> {
1867 def "" : DS_Pseudo <opName, outs, ins, []>;
1869 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1870 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1871 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1872 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1875 multiclass DS_1A <bits<8> op, string opName,
1877 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1878 string asm = opName#" $addr"#"$offset"#"$gds"> {
1880 let mayLoad = 1, mayStore = 1 in {
1881 def "" : DS_Pseudo <opName, outs, ins, []>;
1883 let vdst = 0, data0 = 0, data1 = 0 in {
1884 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1885 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1886 } // let vdst = 0, data0 = 0, data1 = 0
1887 } // end mayLoad = 1, mayStore = 1
1890 //===----------------------------------------------------------------------===//
1892 //===----------------------------------------------------------------------===//
1894 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1895 MTBUF <outs, ins, "", pattern>,
1896 SIMCInstr<opName, SISubtarget.NONE> {
1898 let isCodeGenOnly = 1;
1901 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1903 MTBUF <outs, ins, asm, []>,
1905 SIMCInstr<opName, SISubtarget.SI>;
1907 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1908 MTBUF <outs, ins, asm, []>,
1910 SIMCInstr <opName, SISubtarget.VI>;
1912 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1913 list<dag> pattern> {
1915 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1917 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1919 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1923 let mayStore = 1, mayLoad = 0 in {
1925 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1926 RegisterClass regClass> : MTBUF_m <
1928 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1929 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1930 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1931 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1932 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1935 } // mayStore = 1, mayLoad = 0
1937 let mayLoad = 1, mayStore = 0 in {
1939 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1940 RegisterClass regClass> : MTBUF_m <
1941 op, opName, (outs regClass:$dst),
1942 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1943 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1944 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1945 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1946 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1949 } // mayLoad = 1, mayStore = 0
1951 //===----------------------------------------------------------------------===//
1953 //===----------------------------------------------------------------------===//
1955 class mubuf <bits<7> si, bits<7> vi = si> {
1956 field bits<7> SI = si;
1957 field bits<7> VI = vi;
1960 let isCodeGenOnly = 0 in {
1962 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1963 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1967 } // End let isCodeGenOnly = 0
1969 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1970 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
1974 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1975 bit IsAddr64 = is_addr64;
1976 string OpName = NAME # suffix;
1979 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1980 MUBUF <outs, ins, "", pattern>,
1981 SIMCInstr<opName, SISubtarget.NONE> {
1983 let isCodeGenOnly = 1;
1985 // dummy fields, so that we can use let statements around multiclasses
1995 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1997 MUBUF <outs, ins, asm, []>,
1999 SIMCInstr<opName, SISubtarget.SI> {
2003 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2005 MUBUF <outs, ins, asm, []>,
2007 SIMCInstr<opName, SISubtarget.VI> {
2011 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2012 list<dag> pattern> {
2014 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2015 MUBUFAddr64Table <0>;
2017 let addr64 = 0, isCodeGenOnly = 0 in {
2018 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2021 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2024 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2025 dag ins, string asm, list<dag> pattern> {
2027 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2028 MUBUFAddr64Table <1>;
2030 let addr64 = 1, isCodeGenOnly = 0 in {
2031 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2034 // There is no VI version. If the pseudo is selected, it should be lowered
2035 // for VI appropriately.
2038 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2039 string asm, list<dag> pattern, bit is_return> {
2041 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2042 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2043 AtomicNoRet<NAME#"_OFFSET", is_return>;
2045 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2047 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2050 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2054 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2055 string asm, list<dag> pattern, bit is_return> {
2057 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2058 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2059 AtomicNoRet<NAME#"_ADDR64", is_return>;
2061 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2062 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2065 // There is no VI version. If the pseudo is selected, it should be lowered
2066 // for VI appropriately.
2069 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2070 ValueType vt, SDPatternOperator atomic> {
2072 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2074 // No return variants
2077 defm _ADDR64 : MUBUFAtomicAddr64_m <
2078 op, name#"_addr64", (outs),
2079 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2080 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2081 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2084 defm _OFFSET : MUBUFAtomicOffset_m <
2085 op, name#"_offset", (outs),
2086 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2088 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2092 // Variant that return values
2093 let glc = 1, Constraints = "$vdata = $vdata_in",
2094 DisableEncoding = "$vdata_in" in {
2096 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2097 op, name#"_rtn_addr64", (outs rc:$vdata),
2098 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2099 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2100 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2102 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2103 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2106 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2107 op, name#"_rtn_offset", (outs rc:$vdata),
2108 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2109 mbuf_offset:$offset, slc:$slc),
2110 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2112 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2113 i1:$slc), vt:$vdata_in))], 1
2118 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2121 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2122 ValueType load_vt = i32,
2123 SDPatternOperator ld = null_frag> {
2125 let mayLoad = 1, mayStore = 0 in {
2126 let offen = 0, idxen = 0, vaddr = 0 in {
2127 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2128 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2129 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2130 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2131 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2132 i32:$soffset, i16:$offset,
2133 i1:$glc, i1:$slc, i1:$tfe)))]>;
2136 let offen = 1, idxen = 0 in {
2137 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2138 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2139 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2141 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2144 let offen = 0, idxen = 1 in {
2145 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2146 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2147 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2148 slc:$slc, tfe:$tfe),
2149 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2152 let offen = 1, idxen = 1 in {
2153 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2154 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2155 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2156 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2159 let offen = 0, idxen = 0 in {
2160 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2161 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2162 SCSrc_32:$soffset, mbuf_offset:$offset,
2163 glc:$glc, slc:$slc, tfe:$tfe),
2164 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2165 "$glc"#"$slc"#"$tfe",
2166 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2167 i64:$vaddr, i32:$soffset,
2168 i16:$offset, i1:$glc, i1:$slc,
2174 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2175 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2176 let mayLoad = 0, mayStore = 1 in {
2177 defm : MUBUF_m <op, name, (outs),
2178 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2179 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2181 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2182 "$glc"#"$slc"#"$tfe", []>;
2184 let offen = 0, idxen = 0, vaddr = 0 in {
2185 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2186 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2187 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2188 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2189 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2190 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2191 } // offen = 0, idxen = 0, vaddr = 0
2193 let offen = 1, idxen = 0 in {
2194 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2195 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2196 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2197 slc:$slc, tfe:$tfe),
2198 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2199 "$glc"#"$slc"#"$tfe", []>;
2200 } // end offen = 1, idxen = 0
2202 let offen = 0, idxen = 1 in {
2203 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2204 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2205 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2206 slc:$slc, tfe:$tfe),
2207 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2210 let offen = 1, idxen = 1 in {
2211 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2212 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2213 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2214 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2217 let offen = 0, idxen = 0 in {
2218 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2219 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2221 mbuf_offset:$offset, glc:$glc, slc:$slc,
2223 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2224 "$offset"#"$glc"#"$slc"#"$tfe",
2225 [(st store_vt:$vdata,
2226 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2227 i32:$soffset, i16:$offset,
2228 i1:$glc, i1:$slc, i1:$tfe))]>;
2230 } // End mayLoad = 0, mayStore = 1
2233 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2234 FLAT <op, (outs regClass:$vdst),
2235 (ins VReg_64:$addr),
2236 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2244 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2245 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2246 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2259 class MIMG_Mask <string op, int channels> {
2261 int Channels = channels;
2264 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2265 RegisterClass dst_rc,
2266 RegisterClass src_rc> : MIMG <
2268 (outs dst_rc:$vdata),
2269 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2270 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2272 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2273 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2278 let hasPostISelHook = 1;
2281 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2282 RegisterClass dst_rc,
2284 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2285 MIMG_Mask<asm#"_V1", channels>;
2286 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2287 MIMG_Mask<asm#"_V2", channels>;
2288 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2289 MIMG_Mask<asm#"_V4", channels>;
2292 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2293 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2294 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2295 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2296 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2299 class MIMG_Sampler_Helper <bits<7> op, string asm,
2300 RegisterClass dst_rc,
2301 RegisterClass src_rc, int wqm> : MIMG <
2303 (outs dst_rc:$vdata),
2304 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2305 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2306 SReg_256:$srsrc, SReg_128:$ssamp),
2307 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2308 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2312 let hasPostISelHook = 1;
2316 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2317 RegisterClass dst_rc,
2318 int channels, int wqm> {
2319 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2320 MIMG_Mask<asm#"_V1", channels>;
2321 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2322 MIMG_Mask<asm#"_V2", channels>;
2323 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2324 MIMG_Mask<asm#"_V4", channels>;
2325 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2326 MIMG_Mask<asm#"_V8", channels>;
2327 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2328 MIMG_Mask<asm#"_V16", channels>;
2331 multiclass MIMG_Sampler <bits<7> op, string asm> {
2332 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2333 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2334 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2335 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2338 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2339 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2340 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2341 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2342 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2345 class MIMG_Gather_Helper <bits<7> op, string asm,
2346 RegisterClass dst_rc,
2347 RegisterClass src_rc, int wqm> : MIMG <
2349 (outs dst_rc:$vdata),
2350 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2351 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2352 SReg_256:$srsrc, SReg_128:$ssamp),
2353 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2354 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2359 // DMASK was repurposed for GATHER4. 4 components are always
2360 // returned and DMASK works like a swizzle - it selects
2361 // the component to fetch. The only useful DMASK values are
2362 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2363 // (red,red,red,red) etc.) The ISA document doesn't mention
2365 // Therefore, disable all code which updates DMASK by setting these two:
2367 let hasPostISelHook = 0;
2371 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2372 RegisterClass dst_rc,
2373 int channels, int wqm> {
2374 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2375 MIMG_Mask<asm#"_V1", channels>;
2376 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2377 MIMG_Mask<asm#"_V2", channels>;
2378 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2379 MIMG_Mask<asm#"_V4", channels>;
2380 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2381 MIMG_Mask<asm#"_V8", channels>;
2382 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2383 MIMG_Mask<asm#"_V16", channels>;
2386 multiclass MIMG_Gather <bits<7> op, string asm> {
2387 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2388 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2389 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2390 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2393 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2394 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2395 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2396 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2397 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2400 //===----------------------------------------------------------------------===//
2401 // Vector instruction mappings
2402 //===----------------------------------------------------------------------===//
2404 // Maps an opcode in e32 form to its e64 equivalent
2405 def getVOPe64 : InstrMapping {
2406 let FilterClass = "VOP";
2407 let RowFields = ["OpName"];
2408 let ColFields = ["Size"];
2410 let ValueCols = [["8"]];
2413 // Maps an opcode in e64 form to its e32 equivalent
2414 def getVOPe32 : InstrMapping {
2415 let FilterClass = "VOP";
2416 let RowFields = ["OpName"];
2417 let ColFields = ["Size"];
2419 let ValueCols = [["4"]];
2422 def getMaskedMIMGOp : InstrMapping {
2423 let FilterClass = "MIMG_Mask";
2424 let RowFields = ["Op"];
2425 let ColFields = ["Channels"];
2427 let ValueCols = [["1"], ["2"], ["3"] ];
2430 // Maps an commuted opcode to its original version
2431 def getCommuteOrig : InstrMapping {
2432 let FilterClass = "VOP2_REV";
2433 let RowFields = ["RevOp"];
2434 let ColFields = ["IsOrig"];
2436 let ValueCols = [["1"]];
2439 // Maps an original opcode to its commuted version
2440 def getCommuteRev : InstrMapping {
2441 let FilterClass = "VOP2_REV";
2442 let RowFields = ["RevOp"];
2443 let ColFields = ["IsOrig"];
2445 let ValueCols = [["0"]];
2448 def getCommuteCmpOrig : InstrMapping {
2449 let FilterClass = "VOP2_REV";
2450 let RowFields = ["RevOp"];
2451 let ColFields = ["IsOrig"];
2453 let ValueCols = [["1"]];
2456 // Maps an original opcode to its commuted version
2457 def getCommuteCmpRev : InstrMapping {
2458 let FilterClass = "VOP2_REV";
2459 let RowFields = ["RevOp"];
2460 let ColFields = ["IsOrig"];
2462 let ValueCols = [["0"]];
2466 def getMCOpcodeGen : InstrMapping {
2467 let FilterClass = "SIMCInstr";
2468 let RowFields = ["PseudoInstr"];
2469 let ColFields = ["Subtarget"];
2470 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2471 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2474 def getAddr64Inst : InstrMapping {
2475 let FilterClass = "MUBUFAddr64Table";
2476 let RowFields = ["OpName"];
2477 let ColFields = ["IsAddr64"];
2479 let ValueCols = [["1"]];
2482 // Maps an atomic opcode to its version with a return value.
2483 def getAtomicRetOp : InstrMapping {
2484 let FilterClass = "AtomicNoRet";
2485 let RowFields = ["NoRetOp"];
2486 let ColFields = ["IsRet"];
2488 let ValueCols = [["1"]];
2491 // Maps an atomic opcode to its returnless version.
2492 def getAtomicNoRetOp : InstrMapping {
2493 let FilterClass = "AtomicNoRet";
2494 let RowFields = ["NoRetOp"];
2495 let ColFields = ["IsRet"];
2497 let ValueCols = [["0"]];
2500 include "SIInstructions.td"
2501 include "CIInstructions.td"
2502 include "VIInstructions.td"