1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
386 SOP1 <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
391 SOP1 <outs, ins, asm, []>,
393 SIMCInstr<opName, SISubtarget.VI>;
395 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
398 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
400 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
402 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
406 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
407 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
408 opName#" $dst, $src0", pattern
411 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
412 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
413 opName#" $dst, $src0", pattern
416 // no input, 64-bit output.
417 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
418 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
420 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
425 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
431 // 64-bit input, 32-bit output.
432 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
433 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
434 opName#" $dst, $src0", pattern
437 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
438 SOP2<outs, ins, "", pattern>,
439 SIMCInstr<opName, SISubtarget.NONE> {
444 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
445 SOP2<outs, ins, asm, []>,
447 SIMCInstr<opName, SISubtarget.SI>;
449 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
450 SOP2<outs, ins, asm, []>,
452 SIMCInstr<opName, SISubtarget.VI>;
454 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
455 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
456 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
458 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
459 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
460 opName#" $dst, $src0, $src1 [$scc]">;
462 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
463 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
464 opName#" $dst, $src0, $src1 [$scc]">;
467 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
468 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
469 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
471 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
472 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
474 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
475 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
478 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
479 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
480 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
482 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
483 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
485 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
486 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
489 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
490 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
491 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
493 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
494 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
496 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
497 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
501 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
502 string opName, PatLeaf cond> : SOPC <
503 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
504 opName#" $dst, $src0, $src1", []>;
506 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
507 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
509 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
510 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
512 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
513 SOPK <outs, ins, "", pattern>,
514 SIMCInstr<opName, SISubtarget.NONE> {
518 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
519 SOPK <outs, ins, asm, []>,
521 SIMCInstr<opName, SISubtarget.SI>;
523 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
524 SOPK <outs, ins, asm, []>,
526 SIMCInstr<opName, SISubtarget.VI>;
528 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
529 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
532 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
533 opName#" $dst, $src0">;
535 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
536 opName#" $dst, $src0">;
539 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
540 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
541 (ins SReg_32:$src0, u16imm:$src1), pattern>;
543 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
544 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
546 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
547 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
550 //===----------------------------------------------------------------------===//
552 //===----------------------------------------------------------------------===//
554 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
555 SMRD <outs, ins, "", pattern>,
556 SIMCInstr<opName, SISubtarget.NONE> {
560 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
562 SMRD <outs, ins, asm, []>,
564 SIMCInstr<opName, SISubtarget.SI>;
566 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
568 SMRD <outs, ins, asm, []>,
570 SIMCInstr<opName, SISubtarget.VI>;
572 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
573 string asm, list<dag> pattern> {
575 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
577 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
579 // glc is only applicable to scalar stores, which are not yet
582 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
586 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
587 RegisterClass dstClass> {
589 op, opName#"_IMM", 1, (outs dstClass:$dst),
590 (ins baseClass:$sbase, u32imm:$offset),
591 opName#" $dst, $sbase, $offset", []
594 defm _SGPR : SMRD_m <
595 op, opName#"_SGPR", 0, (outs dstClass:$dst),
596 (ins baseClass:$sbase, SReg_32:$soff),
597 opName#" $dst, $sbase, $soff", []
601 //===----------------------------------------------------------------------===//
602 // Vector ALU classes
603 //===----------------------------------------------------------------------===//
605 // This must always be right before the operand being input modified.
606 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
607 let PrintMethod = "printOperandAndMods";
609 def InputModsNoDefault : Operand <i32> {
610 let PrintMethod = "printOperandAndMods";
613 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
615 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
616 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
620 // Returns the register class to use for the destination of VOP[123C]
621 // instructions for the given VT.
622 class getVALUDstForVT<ValueType VT> {
623 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
624 !if(!eq(VT.Size, 64), VReg_64,
625 SReg_64)); // else VT == i1
628 // Returns the register class to use for source 0 of VOP[12C]
629 // instructions for the given VT.
630 class getVOPSrc0ForVT<ValueType VT> {
631 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
634 // Returns the register class to use for source 1 of VOP[12C] for the
636 class getVOPSrc1ForVT<ValueType VT> {
637 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
640 // Returns the register class to use for sources of VOP3 instructions for the
642 class getVOP3SrcForVT<ValueType VT> {
643 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
646 // Returns 1 if the source arguments have modifiers, 0 if they do not.
647 class hasModifiers<ValueType SrcVT> {
648 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
649 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
652 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
653 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
654 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
655 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
659 // Returns the input arguments for VOP3 instructions for the given SrcVT.
660 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
661 RegisterOperand Src2RC, int NumSrcArgs,
665 !if (!eq(NumSrcArgs, 1),
666 !if (!eq(HasModifiers, 1),
667 // VOP1 with modifiers
668 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
669 ClampMod:$clamp, omod:$omod)
671 // VOP1 without modifiers
674 !if (!eq(NumSrcArgs, 2),
675 !if (!eq(HasModifiers, 1),
676 // VOP 2 with modifiers
677 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
678 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
679 ClampMod:$clamp, omod:$omod)
681 // VOP2 without modifiers
682 (ins Src0RC:$src0, Src1RC:$src1)
684 /* NumSrcArgs == 3 */,
685 !if (!eq(HasModifiers, 1),
686 // VOP3 with modifiers
687 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
688 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
689 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
690 ClampMod:$clamp, omod:$omod)
692 // VOP3 without modifiers
693 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
697 // Returns the assembly string for the inputs and outputs of a VOP[12C]
698 // instruction. This does not add the _e32 suffix, so it can be reused
700 class getAsm32 <int NumSrcArgs> {
701 string src1 = ", $src1";
702 string src2 = ", $src2";
703 string ret = " $dst, $src0"#
704 !if(!eq(NumSrcArgs, 1), "", src1)#
705 !if(!eq(NumSrcArgs, 3), src2, "");
708 // Returns the assembly string for the inputs and outputs of a VOP3
710 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
711 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
712 string src1 = !if(!eq(NumSrcArgs, 1), "",
713 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
714 " $src1_modifiers,"));
715 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
717 !if(!eq(HasModifiers, 0),
718 getAsm32<NumSrcArgs>.ret,
719 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
723 class VOPProfile <list<ValueType> _ArgVT> {
725 field list<ValueType> ArgVT = _ArgVT;
727 field ValueType DstVT = ArgVT[0];
728 field ValueType Src0VT = ArgVT[1];
729 field ValueType Src1VT = ArgVT[2];
730 field ValueType Src2VT = ArgVT[3];
731 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
732 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
733 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
734 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
735 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
736 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
738 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
739 field bit HasModifiers = hasModifiers<Src0VT>.ret;
741 field dag Outs = (outs DstRC:$dst);
743 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
744 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
747 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
748 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
751 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
752 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
753 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
754 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
755 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
756 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
757 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
758 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
759 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
761 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
762 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
763 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
764 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
765 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
766 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
767 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
768 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
769 let Src0RC32 = VCSrc_32;
772 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
773 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
774 let Asm64 = " $dst, $src0_modifiers, $src1";
777 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
778 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
779 let Asm64 = " $dst, $src0_modifiers, $src1";
782 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
783 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
784 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
786 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
787 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
788 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
789 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
792 class VOP <string opName> {
793 string OpName = opName;
796 class VOP2_REV <string revOp, bit isOrig> {
797 string RevOp = revOp;
801 class AtomicNoRet <string noRetOp, bit isRet> {
802 string NoRetOp = noRetOp;
806 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
807 VOP1Common <outs, ins, "", pattern>,
809 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
813 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
815 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
817 def _si : VOP1<op.SI, outs, ins, asm, []>,
818 SIMCInstr <opName#"_e32", SISubtarget.SI>;
819 def _vi : VOP1<op.VI, outs, ins, asm, []>,
820 SIMCInstr <opName#"_e32", SISubtarget.VI>;
823 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
825 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
827 def _si : VOP1<op.SI, outs, ins, asm, []>,
828 SIMCInstr <opName#"_e32", SISubtarget.SI>;
829 // No VI instruction. This class is for SI only.
832 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
833 VOP2Common <outs, ins, "", pattern>,
835 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
839 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
840 string opName, string revOp> {
841 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
842 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
844 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
845 SIMCInstr <opName#"_e32", SISubtarget.SI>;
848 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
849 string opName, string revOp> {
850 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
851 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
853 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
854 SIMCInstr <opName#"_e32", SISubtarget.SI>;
855 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
856 SIMCInstr <opName#"_e32", SISubtarget.VI>;
859 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
861 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
862 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
863 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
864 bits<2> omod = !if(HasModifiers, ?, 0);
865 bits<1> clamp = !if(HasModifiers, ?, 0);
866 bits<9> src1 = !if(HasSrc1, ?, 0);
867 bits<9> src2 = !if(HasSrc2, ?, 0);
870 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
871 VOP3Common <outs, ins, "", pattern>,
873 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
877 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
878 VOP3Common <outs, ins, asm, []>,
880 SIMCInstr<opName#"_e64", SISubtarget.SI>;
882 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
883 VOP3Common <outs, ins, asm, []>,
885 SIMCInstr <opName#"_e64", SISubtarget.VI>;
887 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
888 VOP3Common <outs, ins, asm, []>,
890 SIMCInstr<opName#"_e64", SISubtarget.SI>;
892 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
893 VOP3Common <outs, ins, asm, []>,
895 SIMCInstr <opName#"_e64", SISubtarget.VI>;
897 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
898 string opName, int NumSrcArgs, bit HasMods = 1> {
900 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
902 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
903 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
904 !if(!eq(NumSrcArgs, 2), 0, 1),
906 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
907 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
908 !if(!eq(NumSrcArgs, 2), 0, 1),
912 // VOP3_m without source modifiers
913 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
914 string opName, int NumSrcArgs, bit HasMods = 1> {
916 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
918 let src0_modifiers = 0,
920 src2_modifiers = 0 in {
921 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
922 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
926 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
927 list<dag> pattern, string opName, bit HasMods = 1> {
929 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
931 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
932 VOP3DisableFields<0, 0, HasMods>;
934 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
935 VOP3DisableFields<0, 0, HasMods>;
938 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
939 list<dag> pattern, string opName, bit HasMods = 1> {
941 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
943 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
944 VOP3DisableFields<0, 0, HasMods>;
945 // No VI instruction. This class is for SI only.
948 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
949 list<dag> pattern, string opName, string revOp,
950 bit HasMods = 1, bit UseFullOp = 0> {
952 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
953 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
955 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
956 VOP3DisableFields<1, 0, HasMods>;
958 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
959 VOP3DisableFields<1, 0, HasMods>;
962 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
963 list<dag> pattern, string opName, string revOp,
964 bit HasMods = 1, bit UseFullOp = 0> {
966 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
967 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
969 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
970 VOP3DisableFields<1, 0, HasMods>;
972 // No VI instruction. This class is for SI only.
975 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
976 // option of implicit vcc use?
977 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
978 list<dag> pattern, string opName, string revOp,
979 bit HasMods = 1, bit UseFullOp = 0> {
980 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
981 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
983 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
984 // can write it into any SGPR. We currently don't use the carry out,
985 // so for now hardcode it to VCC as well.
986 let sdst = SIOperand.VCC, Defs = [VCC] in {
987 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
988 VOP3DisableFields<1, 0, HasMods>;
990 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
991 VOP3DisableFields<1, 0, HasMods>;
992 } // End sdst = SIOperand.VCC, Defs = [VCC]
995 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
996 list<dag> pattern, string opName, string revOp,
997 bit HasMods = 1, bit UseFullOp = 0> {
998 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1001 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1002 VOP3DisableFields<1, 1, HasMods>;
1004 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1005 VOP3DisableFields<1, 1, HasMods>;
1008 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1009 list<dag> pattern, string opName,
1010 bit HasMods, bit defExec> {
1012 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1014 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1015 VOP3DisableFields<1, 0, HasMods> {
1016 let Defs = !if(defExec, [EXEC], []);
1019 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1020 VOP3DisableFields<1, 0, HasMods> {
1021 let Defs = !if(defExec, [EXEC], []);
1025 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1026 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1027 string asm, list<dag> pattern = []> {
1028 let isPseudo = 1 in {
1029 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1030 SIMCInstr<opName, SISubtarget.NONE>;
1033 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1034 SIMCInstr <opName, SISubtarget.SI>;
1036 def _vi : VOP3Common <outs, ins, asm, []>,
1038 VOP3DisableFields <1, 0, 0>,
1039 SIMCInstr <opName, SISubtarget.VI>;
1042 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1043 dag ins32, string asm32, list<dag> pat32,
1044 dag ins64, string asm64, list<dag> pat64,
1047 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1049 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1052 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1053 SDPatternOperator node = null_frag> : VOP1_Helper <
1055 P.Ins32, P.Asm32, [],
1058 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1059 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1060 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1064 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1065 SDPatternOperator node = null_frag> {
1067 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1069 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1071 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1072 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1073 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1074 opName, P.HasModifiers>;
1077 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1078 dag ins32, string asm32, list<dag> pat32,
1079 dag ins64, string asm64, list<dag> pat64,
1080 string revOp, bit HasMods> {
1081 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1083 defm _e64 : VOP3_2_m <op,
1084 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1088 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1089 SDPatternOperator node = null_frag,
1090 string revOp = opName> : VOP2_Helper <
1092 P.Ins32, P.Asm32, [],
1096 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1097 i1:$clamp, i32:$omod)),
1098 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1099 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1100 revOp, P.HasModifiers
1103 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1104 SDPatternOperator node = null_frag,
1105 string revOp = opName> {
1106 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1108 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1111 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1112 i1:$clamp, i32:$omod)),
1113 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1114 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1115 opName, revOp, P.HasModifiers>;
1118 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1119 dag ins32, string asm32, list<dag> pat32,
1120 dag ins64, string asm64, list<dag> pat64,
1121 string revOp, bit HasMods> {
1123 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1125 defm _e64 : VOP3b_2_m <op,
1126 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1130 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1131 SDPatternOperator node = null_frag,
1132 string revOp = opName> : VOP2b_Helper <
1134 P.Ins32, P.Asm32, [],
1138 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1139 i1:$clamp, i32:$omod)),
1140 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1141 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1142 revOp, P.HasModifiers
1145 // A VOP2 instruction that is VOP3-only on VI.
1146 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1147 dag ins32, string asm32, list<dag> pat32,
1148 dag ins64, string asm64, list<dag> pat64,
1149 string revOp, bit HasMods> {
1150 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1152 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1156 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1157 SDPatternOperator node = null_frag,
1158 string revOp = opName>
1161 P.Ins32, P.Asm32, [],
1165 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1166 i1:$clamp, i32:$omod)),
1167 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1168 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1169 revOp, P.HasModifiers
1172 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1173 VOPCCommon <ins, "", pattern>,
1175 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1179 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1180 string opName, bit DefExec> {
1181 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1183 def _si : VOPC<op.SI, ins, asm, []>,
1184 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1185 let Defs = !if(DefExec, [EXEC], []);
1188 def _vi : VOPC<op.VI, ins, asm, []>,
1189 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1190 let Defs = !if(DefExec, [EXEC], []);
1194 multiclass VOPC_Helper <vopc op, string opName,
1195 dag ins32, string asm32, list<dag> pat32,
1196 dag out64, dag ins64, string asm64, list<dag> pat64,
1197 bit HasMods, bit DefExec> {
1198 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1200 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1201 opName, HasMods, DefExec>;
1204 multiclass VOPCInst <vopc op, string opName,
1205 VOPProfile P, PatLeaf cond = COND_NULL,
1206 bit DefExec = 0> : VOPC_Helper <
1208 P.Ins32, P.Asm32, [],
1209 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1212 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1213 i1:$clamp, i32:$omod)),
1214 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1216 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1217 P.HasModifiers, DefExec
1220 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1221 bit DefExec = 0> : VOPC_Helper <
1223 P.Ins32, P.Asm32, [],
1224 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1227 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1228 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1229 P.HasModifiers, DefExec
1233 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1234 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1236 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1237 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1239 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1240 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1242 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1243 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1246 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1247 PatLeaf cond = COND_NULL>
1248 : VOPCInst <op, opName, P, cond, 1>;
1250 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1251 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1253 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1254 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1256 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1257 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1259 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1260 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1262 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1263 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1264 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1267 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1268 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1270 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1271 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1273 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1274 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1276 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1277 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1279 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1280 SDPatternOperator node = null_frag> : VOP3_Helper <
1281 op, opName, P.Outs, P.Ins64, P.Asm64,
1282 !if(!eq(P.NumSrcArgs, 3),
1285 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1286 i1:$clamp, i32:$omod)),
1287 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1288 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1289 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1291 !if(!eq(P.NumSrcArgs, 2),
1294 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1295 i1:$clamp, i32:$omod)),
1296 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1297 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1298 /* P.NumSrcArgs == 1 */,
1301 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1302 i1:$clamp, i32:$omod))))],
1303 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1304 P.NumSrcArgs, P.HasModifiers
1307 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1308 // only VOP instruction that implicitly reads VCC.
1309 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1311 SDPatternOperator node = null_frag> : VOP3_Helper <
1314 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1315 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1316 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1319 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1321 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1322 i1:$clamp, i32:$omod)),
1323 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1324 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1329 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1330 string opName, list<dag> pattern> :
1332 op, (outs vrc:$vdst, SReg_64:$sdst),
1333 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1334 InputModsNoDefault:$src1_modifiers, arc:$src1,
1335 InputModsNoDefault:$src2_modifiers, arc:$src2,
1336 ClampMod:$clamp, omod:$omod),
1337 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1338 opName, opName, 1, 1
1341 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1342 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1344 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1345 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1348 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1349 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1350 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1351 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1352 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1353 i32:$src1_modifiers, P.Src1VT:$src1,
1354 i32:$src2_modifiers, P.Src2VT:$src2,
1358 //===----------------------------------------------------------------------===//
1359 // Interpolation opcodes
1360 //===----------------------------------------------------------------------===//
1362 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1363 VINTRPCommon <outs, ins, "", pattern>,
1364 SIMCInstr<opName, SISubtarget.NONE> {
1368 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1370 VINTRPCommon <outs, ins, asm, []>,
1372 SIMCInstr<opName, SISubtarget.SI>;
1374 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1376 VINTRPCommon <outs, ins, asm, []>,
1378 SIMCInstr<opName, SISubtarget.VI>;
1380 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1381 string disableEncoding = "", string constraints = "",
1382 list<dag> pattern = []> {
1383 let DisableEncoding = disableEncoding,
1384 Constraints = constraints in {
1385 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1387 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1389 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1393 //===----------------------------------------------------------------------===//
1394 // Vector I/O classes
1395 //===----------------------------------------------------------------------===//
1397 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1398 DS <outs, ins, "", pattern>,
1399 SIMCInstr <opName, SISubtarget.NONE> {
1403 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1404 DS <outs, ins, asm, []>,
1406 SIMCInstr <opName, SISubtarget.SI>;
1408 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1409 DS <outs, ins, asm, []>,
1411 SIMCInstr <opName, SISubtarget.VI>;
1413 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1414 DS <outs, ins, asm, []>,
1416 SIMCInstr <opName, SISubtarget.SI> {
1418 // Single load interpret the 2 i8imm operands as a single i16 offset.
1420 let offset0 = offset{7-0};
1421 let offset1 = offset{15-8};
1424 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1425 DS <outs, ins, asm, []>,
1427 SIMCInstr <opName, SISubtarget.VI> {
1429 // Single load interpret the 2 i8imm operands as a single i16 offset.
1431 let offset0 = offset{7-0};
1432 let offset1 = offset{15-8};
1435 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1437 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1438 def "" : DS_Pseudo <opName, outs, ins, pat>;
1440 let data0 = 0, data1 = 0 in {
1441 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1442 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1447 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1451 (outs regClass:$vdst),
1452 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1453 asm#" $vdst, $addr"#"$offset"#" [M0]",
1456 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1458 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1459 def "" : DS_Pseudo <opName, outs, ins, pat>;
1461 let data0 = 0, data1 = 0 in {
1462 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1463 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1468 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1472 (outs regClass:$vdst),
1473 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1475 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1478 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1479 string asm, list<dag> pat> {
1480 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1481 def "" : DS_Pseudo <opName, outs, ins, pat>;
1483 let data1 = 0, vdst = 0 in {
1484 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1485 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1490 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1495 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1496 asm#" $addr, $data0"#"$offset"#" [M0]",
1499 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1500 string asm, list<dag> pat> {
1501 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1502 def "" : DS_Pseudo <opName, outs, ins, pat>;
1505 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1506 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1511 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1516 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1517 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1518 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1521 // 1 address, 1 data.
1522 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1523 string asm, list<dag> pat, string noRetOp> {
1524 let mayLoad = 1, mayStore = 1,
1525 hasPostISelHook = 1 // Adjusted to no return version.
1527 def "" : DS_Pseudo <opName, outs, ins, pat>,
1528 AtomicNoRet<noRetOp, 1>;
1531 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1532 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1537 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1538 string noRetOp = ""> : DS_1A1D_RET_m <
1541 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1542 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1544 // 1 address, 2 data.
1545 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1546 string asm, list<dag> pat, string noRetOp> {
1547 let mayLoad = 1, mayStore = 1,
1548 hasPostISelHook = 1 // Adjusted to no return version.
1550 def "" : DS_Pseudo <opName, outs, ins, pat>,
1551 AtomicNoRet<noRetOp, 1>;
1553 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1554 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1558 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1559 string noRetOp = ""> : DS_1A2D_RET_m <
1562 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1563 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1566 // 1 address, 2 data.
1567 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1568 string asm, list<dag> pat, string noRetOp> {
1569 let mayLoad = 1, mayStore = 1 in {
1570 def "" : DS_Pseudo <opName, outs, ins, pat>,
1571 AtomicNoRet<noRetOp, 0>;
1574 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1575 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1580 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1581 string noRetOp = asm> : DS_1A2D_NORET_m <
1584 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1585 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1588 // 1 address, 1 data.
1589 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1590 string asm, list<dag> pat, string noRetOp> {
1591 let mayLoad = 1, mayStore = 1 in {
1592 def "" : DS_Pseudo <opName, outs, ins, pat>,
1593 AtomicNoRet<noRetOp, 0>;
1595 let data1 = 0, vdst = 0 in {
1596 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1597 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1602 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1603 string noRetOp = asm> : DS_1A1D_NORET_m <
1606 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1607 asm#" $addr, $data0"#"$offset"#" [M0]",
1610 //===----------------------------------------------------------------------===//
1612 //===----------------------------------------------------------------------===//
1614 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1615 MTBUF <outs, ins, "", pattern>,
1616 SIMCInstr<opName, SISubtarget.NONE> {
1620 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1622 MTBUF <outs, ins, asm, []>,
1624 SIMCInstr<opName, SISubtarget.SI>;
1626 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1627 MTBUF <outs, ins, asm, []>,
1629 SIMCInstr <opName, SISubtarget.VI>;
1631 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1632 list<dag> pattern> {
1634 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1636 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1638 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1642 let mayStore = 1, mayLoad = 0 in {
1644 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1645 RegisterClass regClass> : MTBUF_m <
1647 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1648 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1649 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1650 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1651 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1654 } // mayStore = 1, mayLoad = 0
1656 let mayLoad = 1, mayStore = 0 in {
1658 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1659 RegisterClass regClass> : MTBUF_m <
1660 op, opName, (outs regClass:$dst),
1661 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1662 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1663 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1664 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1665 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1668 } // mayLoad = 1, mayStore = 0
1670 //===----------------------------------------------------------------------===//
1672 //===----------------------------------------------------------------------===//
1674 class mubuf <bits<7> si, bits<7> vi = si> {
1675 field bits<7> SI = si;
1676 field bits<7> VI = vi;
1679 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1680 bit IsAddr64 = is_addr64;
1681 string OpName = NAME # suffix;
1684 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1685 MUBUF <outs, ins, "", pattern>,
1686 SIMCInstr<opName, SISubtarget.NONE> {
1689 // dummy fields, so that we can use let statements around multiclasses
1699 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1701 MUBUF <outs, ins, asm, []>,
1703 SIMCInstr<opName, SISubtarget.SI> {
1707 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1709 MUBUF <outs, ins, asm, []>,
1711 SIMCInstr<opName, SISubtarget.VI> {
1715 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1716 list<dag> pattern> {
1718 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1719 MUBUFAddr64Table <0>;
1722 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1725 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1728 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1729 dag ins, string asm, list<dag> pattern> {
1731 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1732 MUBUFAddr64Table <1>;
1735 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1738 // There is no VI version. If the pseudo is selected, it should be lowered
1739 // for VI appropriately.
1742 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1743 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1747 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1748 string asm, list<dag> pattern, bit is_return> {
1750 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1751 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1752 AtomicNoRet<NAME#"_OFFSET", is_return>;
1754 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1756 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1759 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1763 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1764 string asm, list<dag> pattern, bit is_return> {
1766 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1767 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1768 AtomicNoRet<NAME#"_ADDR64", is_return>;
1770 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1771 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1774 // There is no VI version. If the pseudo is selected, it should be lowered
1775 // for VI appropriately.
1778 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1779 ValueType vt, SDPatternOperator atomic> {
1781 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1783 // No return variants
1786 defm _ADDR64 : MUBUFAtomicAddr64_m <
1787 op, name#"_addr64", (outs),
1788 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1789 mbuf_offset:$offset, SCSrc_32:$soffset, slc:$slc),
1790 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1793 defm _OFFSET : MUBUFAtomicOffset_m <
1794 op, name#"_offset", (outs),
1795 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1796 SCSrc_32:$soffset, slc:$slc),
1797 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1801 // Variant that return values
1802 let glc = 1, Constraints = "$vdata = $vdata_in",
1803 DisableEncoding = "$vdata_in" in {
1805 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1806 op, name#"_rtn_addr64", (outs rc:$vdata),
1807 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1808 mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
1809 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1811 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1812 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1815 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1816 op, name#"_rtn_offset", (outs rc:$vdata),
1817 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1818 SCSrc_32:$soffset, slc:$slc),
1819 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1821 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1822 i1:$slc), vt:$vdata_in))], 1
1827 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1830 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1831 ValueType load_vt = i32,
1832 SDPatternOperator ld = null_frag> {
1834 let mayLoad = 1, mayStore = 0 in {
1835 let offen = 0, idxen = 0, vaddr = 0 in {
1836 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1837 (ins SReg_128:$srsrc,
1838 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1839 slc:$slc, tfe:$tfe),
1840 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1841 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1842 i32:$soffset, i16:$offset,
1843 i1:$glc, i1:$slc, i1:$tfe)))]>;
1846 let offen = 1, idxen = 0 in {
1847 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1848 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1849 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1851 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1854 let offen = 0, idxen = 1 in {
1855 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1856 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1857 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1858 slc:$slc, tfe:$tfe),
1859 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1862 let offen = 1, idxen = 1 in {
1863 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1864 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1865 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1866 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1869 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1870 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1871 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1872 SCSrc_32:$soffset, mbuf_offset:$offset),
1873 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1874 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1875 i64:$vaddr, i32:$soffset,
1881 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1882 ValueType store_vt, SDPatternOperator st> {
1883 let mayLoad = 0, mayStore = 1 in {
1884 defm : MUBUF_m <op, name, (outs),
1885 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1886 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1888 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1889 "$glc"#"$slc"#"$tfe", []>;
1891 let offen = 0, idxen = 0, vaddr = 0 in {
1892 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1893 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1894 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1895 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1896 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1897 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1898 } // offen = 0, idxen = 0, vaddr = 0
1900 let offen = 1, idxen = 0 in {
1901 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1902 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1903 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1904 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1905 "$glc"#"$slc"#"$tfe", []>;
1906 } // end offen = 1, idxen = 0
1908 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1909 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1910 (ins vdataClass:$vdata, SReg_128:$srsrc,
1911 VReg_64:$vaddr, SCSrc_32:$soffset,
1912 mbuf_offset:$offset),
1913 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1914 [(st store_vt:$vdata,
1915 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1916 i32:$soffset, i16:$offset))]>;
1918 } // End mayLoad = 0, mayStore = 1
1921 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1922 FLAT <op, (outs regClass:$vdst),
1923 (ins VReg_64:$addr),
1924 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
1932 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1933 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1934 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1947 class MIMG_Mask <string op, int channels> {
1949 int Channels = channels;
1952 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1953 RegisterClass dst_rc,
1954 RegisterClass src_rc> : MIMG <
1956 (outs dst_rc:$vdata),
1957 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1958 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1960 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1961 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1966 let hasPostISelHook = 1;
1969 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1970 RegisterClass dst_rc,
1972 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1973 MIMG_Mask<asm#"_V1", channels>;
1974 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1975 MIMG_Mask<asm#"_V2", channels>;
1976 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1977 MIMG_Mask<asm#"_V4", channels>;
1980 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1981 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1982 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1983 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1984 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1987 class MIMG_Sampler_Helper <bits<7> op, string asm,
1988 RegisterClass dst_rc,
1989 RegisterClass src_rc, int wqm> : MIMG <
1991 (outs dst_rc:$vdata),
1992 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1993 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1994 SReg_256:$srsrc, SReg_128:$ssamp),
1995 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1996 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2000 let hasPostISelHook = 1;
2004 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2005 RegisterClass dst_rc,
2006 int channels, int wqm> {
2007 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2008 MIMG_Mask<asm#"_V1", channels>;
2009 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2010 MIMG_Mask<asm#"_V2", channels>;
2011 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2012 MIMG_Mask<asm#"_V4", channels>;
2013 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2014 MIMG_Mask<asm#"_V8", channels>;
2015 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2016 MIMG_Mask<asm#"_V16", channels>;
2019 multiclass MIMG_Sampler <bits<7> op, string asm> {
2020 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2021 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2022 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2023 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2026 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2027 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2028 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2029 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2030 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2033 class MIMG_Gather_Helper <bits<7> op, string asm,
2034 RegisterClass dst_rc,
2035 RegisterClass src_rc, int wqm> : MIMG <
2037 (outs dst_rc:$vdata),
2038 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2039 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2040 SReg_256:$srsrc, SReg_128:$ssamp),
2041 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2042 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2047 // DMASK was repurposed for GATHER4. 4 components are always
2048 // returned and DMASK works like a swizzle - it selects
2049 // the component to fetch. The only useful DMASK values are
2050 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2051 // (red,red,red,red) etc.) The ISA document doesn't mention
2053 // Therefore, disable all code which updates DMASK by setting these two:
2055 let hasPostISelHook = 0;
2059 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2060 RegisterClass dst_rc,
2061 int channels, int wqm> {
2062 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2063 MIMG_Mask<asm#"_V1", channels>;
2064 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2065 MIMG_Mask<asm#"_V2", channels>;
2066 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2067 MIMG_Mask<asm#"_V4", channels>;
2068 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2069 MIMG_Mask<asm#"_V8", channels>;
2070 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2071 MIMG_Mask<asm#"_V16", channels>;
2074 multiclass MIMG_Gather <bits<7> op, string asm> {
2075 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2076 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2077 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2078 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2081 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2082 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2083 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2084 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2085 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2088 //===----------------------------------------------------------------------===//
2089 // Vector instruction mappings
2090 //===----------------------------------------------------------------------===//
2092 // Maps an opcode in e32 form to its e64 equivalent
2093 def getVOPe64 : InstrMapping {
2094 let FilterClass = "VOP";
2095 let RowFields = ["OpName"];
2096 let ColFields = ["Size"];
2098 let ValueCols = [["8"]];
2101 // Maps an opcode in e64 form to its e32 equivalent
2102 def getVOPe32 : InstrMapping {
2103 let FilterClass = "VOP";
2104 let RowFields = ["OpName"];
2105 let ColFields = ["Size"];
2107 let ValueCols = [["4"]];
2110 // Maps an original opcode to its commuted version
2111 def getCommuteRev : InstrMapping {
2112 let FilterClass = "VOP2_REV";
2113 let RowFields = ["RevOp"];
2114 let ColFields = ["IsOrig"];
2116 let ValueCols = [["0"]];
2119 def getMaskedMIMGOp : InstrMapping {
2120 let FilterClass = "MIMG_Mask";
2121 let RowFields = ["Op"];
2122 let ColFields = ["Channels"];
2124 let ValueCols = [["1"], ["2"], ["3"] ];
2127 // Maps an commuted opcode to its original version
2128 def getCommuteOrig : InstrMapping {
2129 let FilterClass = "VOP2_REV";
2130 let RowFields = ["RevOp"];
2131 let ColFields = ["IsOrig"];
2133 let ValueCols = [["1"]];
2136 def getMCOpcodeGen : InstrMapping {
2137 let FilterClass = "SIMCInstr";
2138 let RowFields = ["PseudoInstr"];
2139 let ColFields = ["Subtarget"];
2140 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2141 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2144 def getAddr64Inst : InstrMapping {
2145 let FilterClass = "MUBUFAddr64Table";
2146 let RowFields = ["OpName"];
2147 let ColFields = ["IsAddr64"];
2149 let ValueCols = [["1"]];
2152 // Maps an atomic opcode to its version with a return value.
2153 def getAtomicRetOp : InstrMapping {
2154 let FilterClass = "AtomicNoRet";
2155 let RowFields = ["NoRetOp"];
2156 let ColFields = ["IsRet"];
2158 let ValueCols = [["1"]];
2161 // Maps an atomic opcode to its returnless version.
2162 def getAtomicNoRetOp : InstrMapping {
2163 let FilterClass = "AtomicNoRet";
2164 let RowFields = ["NoRetOp"];
2165 let ColFields = ["IsRet"];
2167 let ValueCols = [["0"]];
2170 include "SIInstructions.td"
2171 include "CIInstructions.td"
2172 include "VIInstructions.td"