1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
44 class sop1 <bits<8> si, bits<8> vi = si> {
45 field bits<8> SI = si;
46 field bits<8> VI = vi;
49 class sop2 <bits<7> si, bits<7> vi = si> {
50 field bits<7> SI = si;
51 field bits<7> VI = vi;
54 class sopk <bits<5> si, bits<5> vi = si> {
55 field bits<5> SI = si;
56 field bits<5> VI = vi;
59 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
60 // in AMDGPUMCInstLower.h
67 //===----------------------------------------------------------------------===//
69 //===----------------------------------------------------------------------===//
71 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
72 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
73 [SDNPMayLoad, SDNPMemOperand]
76 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
78 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
79 SDTCisVT<1, iAny>, // vdata(VGPR)
80 SDTCisVT<2, i32>, // num_channels(imm)
81 SDTCisVT<3, i32>, // vaddr(VGPR)
82 SDTCisVT<4, i32>, // soffset(SGPR)
83 SDTCisVT<5, i32>, // inst_offset(imm)
84 SDTCisVT<6, i32>, // dfmt(imm)
85 SDTCisVT<7, i32>, // nfmt(imm)
86 SDTCisVT<8, i32>, // offen(imm)
87 SDTCisVT<9, i32>, // idxen(imm)
88 SDTCisVT<10, i32>, // glc(imm)
89 SDTCisVT<11, i32>, // slc(imm)
90 SDTCisVT<12, i32> // tfe(imm)
92 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
95 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
100 class SDSample<string opcode> : SDNode <opcode,
101 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
102 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
105 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
106 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
107 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
108 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
110 def SIconstdata_ptr : SDNode<
111 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
114 // Transformation function, extract the lower 32bit of a 64bit immediate
115 def LO32 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
119 def LO32f : SDNodeXForm<fpimm, [{
120 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
121 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
124 // Transformation function, extract the upper 32bit of a 64bit immediate
125 def HI32 : SDNodeXForm<imm, [{
126 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
129 def HI32f : SDNodeXForm<fpimm, [{
130 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
131 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
134 def IMM8bitDWORD : PatLeaf <(imm),
135 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
138 def as_dword_i32imm : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
142 def as_i1imm : SDNodeXForm<imm, [{
143 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
146 def as_i8imm : SDNodeXForm<imm, [{
147 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
150 def as_i16imm : SDNodeXForm<imm, [{
151 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
154 def as_i32imm: SDNodeXForm<imm, [{
155 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
158 def as_i64imm: SDNodeXForm<imm, [{
159 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
162 def IMM8bit : PatLeaf <(imm),
163 [{return isUInt<8>(N->getZExtValue());}]
166 def IMM12bit : PatLeaf <(imm),
167 [{return isUInt<12>(N->getZExtValue());}]
170 def IMM16bit : PatLeaf <(imm),
171 [{return isUInt<16>(N->getZExtValue());}]
174 def IMM32bit : PatLeaf <(imm),
175 [{return isUInt<32>(N->getZExtValue());}]
178 def mubuf_vaddr_offset : PatFrag<
179 (ops node:$ptr, node:$offset, node:$imm_offset),
180 (add (add node:$ptr, node:$offset), node:$imm_offset)
183 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
184 return isInlineImmediate(N);
187 class SGPRImm <dag frag> : PatLeaf<frag, [{
188 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
189 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
192 const SIRegisterInfo *SIRI =
193 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
194 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
196 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
203 //===----------------------------------------------------------------------===//
205 //===----------------------------------------------------------------------===//
207 def FRAMEri32 : Operand<iPTR> {
208 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
211 def sopp_brtarget : Operand<OtherVT> {
212 let EncoderMethod = "getSOPPBrEncoding";
213 let OperandType = "OPERAND_PCREL";
216 include "SIInstrFormats.td"
217 include "VIInstrFormats.td"
219 let OperandType = "OPERAND_IMMEDIATE" in {
221 def offen : Operand<i1> {
222 let PrintMethod = "printOffen";
224 def idxen : Operand<i1> {
225 let PrintMethod = "printIdxen";
227 def addr64 : Operand<i1> {
228 let PrintMethod = "printAddr64";
230 def mbuf_offset : Operand<i16> {
231 let PrintMethod = "printMBUFOffset";
233 def ds_offset : Operand<i16> {
234 let PrintMethod = "printDSOffset";
236 def ds_offset0 : Operand<i8> {
237 let PrintMethod = "printDSOffset0";
239 def ds_offset1 : Operand<i8> {
240 let PrintMethod = "printDSOffset1";
242 def glc : Operand <i1> {
243 let PrintMethod = "printGLC";
245 def slc : Operand <i1> {
246 let PrintMethod = "printSLC";
248 def tfe : Operand <i1> {
249 let PrintMethod = "printTFE";
252 def omod : Operand <i32> {
253 let PrintMethod = "printOModSI";
256 def ClampMod : Operand <i1> {
257 let PrintMethod = "printClampSI";
260 } // End OperandType = "OPERAND_IMMEDIATE"
262 //===----------------------------------------------------------------------===//
264 //===----------------------------------------------------------------------===//
266 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
267 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
269 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
270 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
271 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
272 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
273 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
274 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
276 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
277 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
278 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
280 //===----------------------------------------------------------------------===//
281 // SI assembler operands
282 //===----------------------------------------------------------------------===//
302 //===----------------------------------------------------------------------===//
304 // SI Instruction multiclass helpers.
306 // Instructions with _32 take 32-bit operands.
307 // Instructions with _64 take 64-bit operands.
309 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
310 // encoding is the standard encoding, but instruction that make use of
311 // any of the instruction modifiers must use the 64-bit encoding.
313 // Instructions with _e32 use the 32-bit encoding.
314 // Instructions with _e64 use the 64-bit encoding.
316 //===----------------------------------------------------------------------===//
318 class SIMCInstr <string pseudo, int subtarget> {
319 string PseudoInstr = pseudo;
320 int Subtarget = subtarget;
323 //===----------------------------------------------------------------------===//
325 //===----------------------------------------------------------------------===//
327 class EXPCommon : InstSI<
329 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
330 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
331 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
340 let isPseudo = 1 in {
341 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
344 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
346 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
354 SOP1 <outs, ins, "", pattern>,
355 SIMCInstr<opName, SISubtarget.NONE> {
359 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm,
361 SOP1 <outs, ins, asm, pattern>,
363 SIMCInstr<opName, SISubtarget.SI>;
365 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm,
367 SOP1 <outs, ins, asm, pattern>,
369 SIMCInstr<opName, SISubtarget.VI>;
371 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
372 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
375 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
376 opName#" $dst, $src0", pattern>;
378 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
379 opName#" $dst, $src0", pattern>;
382 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
383 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
386 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
387 opName#" $dst, $src0", pattern>;
389 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
390 opName#" $dst, $src0", pattern>;
393 // no input, 64-bit output.
394 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
395 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
397 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
398 opName#" $dst", pattern> {
402 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
403 opName#" $dst", pattern> {
408 // 64-bit input, 32-bit output.
409 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
410 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
413 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
414 opName#" $dst, $src0", pattern>;
416 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
417 opName#" $dst, $src0", pattern>;
420 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
421 SOP2<outs, ins, "", pattern>,
422 SIMCInstr<opName, SISubtarget.NONE> {
427 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm,
429 SOP2<outs, ins, asm, pattern>,
431 SIMCInstr<opName, SISubtarget.SI>;
433 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm,
435 SOP2<outs, ins, asm, pattern>,
437 SIMCInstr<opName, SISubtarget.VI>;
439 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
440 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
441 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
443 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
444 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
445 opName#" $dst, $src0, $src1 [$scc]", pattern>;
447 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
448 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
449 opName#" $dst, $src0, $src1 [$scc]", pattern>;
452 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
453 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
454 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
456 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
457 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
459 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
460 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
463 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
464 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
465 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
467 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
468 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
470 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
471 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
474 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
475 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
476 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
478 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
479 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
481 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
482 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
486 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
487 string opName, PatLeaf cond> : SOPC <
488 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
489 opName#" $dst, $src0, $src1", []>;
491 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
492 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
494 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
495 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
497 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
498 SOPK <outs, ins, "", pattern>,
499 SIMCInstr<opName, SISubtarget.NONE> {
503 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm,
505 SOPK <outs, ins, asm, pattern>,
507 SIMCInstr<opName, SISubtarget.SI>;
509 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm,
511 SOPK <outs, ins, asm, pattern>,
513 SIMCInstr<opName, SISubtarget.VI>;
515 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
516 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
519 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
520 opName#" $dst, $src0", pattern>;
522 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
523 opName#" $dst, $src0", pattern>;
526 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
527 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
528 (ins SReg_32:$src0, u16imm:$src1), pattern>;
530 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
531 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
533 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
534 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
537 //===----------------------------------------------------------------------===//
539 //===----------------------------------------------------------------------===//
541 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
542 SMRD <outs, ins, "", pattern>,
543 SIMCInstr<opName, SISubtarget.NONE> {
547 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
549 SMRD <outs, ins, asm, []>,
551 SIMCInstr<opName, SISubtarget.SI>;
553 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
555 SMRD <outs, ins, asm, []>,
557 SIMCInstr<opName, SISubtarget.VI>;
559 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
560 string asm, list<dag> pattern> {
562 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
564 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
566 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
569 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
570 RegisterClass dstClass> {
572 op, opName#"_IMM", 1, (outs dstClass:$dst),
573 (ins baseClass:$sbase, u32imm:$offset),
574 opName#" $dst, $sbase, $offset", []
577 defm _SGPR : SMRD_m <
578 op, opName#"_SGPR", 0, (outs dstClass:$dst),
579 (ins baseClass:$sbase, SReg_32:$soff),
580 opName#" $dst, $sbase, $soff", []
584 //===----------------------------------------------------------------------===//
585 // Vector ALU classes
586 //===----------------------------------------------------------------------===//
588 // This must always be right before the operand being input modified.
589 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
590 let PrintMethod = "printOperandAndMods";
592 def InputModsNoDefault : Operand <i32> {
593 let PrintMethod = "printOperandAndMods";
596 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
598 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
599 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
603 // Returns the register class to use for the destination of VOP[123C]
604 // instructions for the given VT.
605 class getVALUDstForVT<ValueType VT> {
606 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
609 // Returns the register class to use for source 0 of VOP[12C]
610 // instructions for the given VT.
611 class getVOPSrc0ForVT<ValueType VT> {
612 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
615 // Returns the register class to use for source 1 of VOP[12C] for the
617 class getVOPSrc1ForVT<ValueType VT> {
618 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
621 // Returns the register classes for the source arguments of a VOP[12C]
622 // instruction for the given SrcVTs.
623 class getInRC32 <list<ValueType> SrcVT> {
624 list<RegisterClass> ret = [
625 getVOPSrc0ForVT<SrcVT[0]>.ret,
626 getVOPSrc1ForVT<SrcVT[1]>.ret
630 // Returns the register class to use for sources of VOP3 instructions for the
632 class getVOP3SrcForVT<ValueType VT> {
633 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
636 // Returns the register classes for the source arguments of a VOP3
637 // instruction for the given SrcVTs.
638 class getInRC64 <list<ValueType> SrcVT> {
639 list<RegisterClass> ret = [
640 getVOP3SrcForVT<SrcVT[0]>.ret,
641 getVOP3SrcForVT<SrcVT[1]>.ret,
642 getVOP3SrcForVT<SrcVT[2]>.ret
646 // Returns 1 if the source arguments have modifiers, 0 if they do not.
647 class hasModifiers<ValueType SrcVT> {
648 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
649 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
652 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
653 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
654 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
655 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
659 // Returns the input arguments for VOP3 instructions for the given SrcVT.
660 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
661 RegisterClass Src2RC, int NumSrcArgs,
665 !if (!eq(NumSrcArgs, 1),
666 !if (!eq(HasModifiers, 1),
667 // VOP1 with modifiers
668 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
669 ClampMod:$clamp, omod:$omod)
671 // VOP1 without modifiers
674 !if (!eq(NumSrcArgs, 2),
675 !if (!eq(HasModifiers, 1),
676 // VOP 2 with modifiers
677 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
678 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
679 ClampMod:$clamp, omod:$omod)
681 // VOP2 without modifiers
682 (ins Src0RC:$src0, Src1RC:$src1)
684 /* NumSrcArgs == 3 */,
685 !if (!eq(HasModifiers, 1),
686 // VOP3 with modifiers
687 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
688 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
689 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
690 ClampMod:$clamp, omod:$omod)
692 // VOP3 without modifiers
693 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
697 // Returns the assembly string for the inputs and outputs of a VOP[12C]
698 // instruction. This does not add the _e32 suffix, so it can be reused
700 class getAsm32 <int NumSrcArgs> {
701 string src1 = ", $src1";
702 string src2 = ", $src2";
703 string ret = " $dst, $src0"#
704 !if(!eq(NumSrcArgs, 1), "", src1)#
705 !if(!eq(NumSrcArgs, 3), src2, "");
708 // Returns the assembly string for the inputs and outputs of a VOP3
710 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
711 string src0 = "$src0_modifiers,";
712 string src1 = !if(!eq(NumSrcArgs, 1), "",
713 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
714 " $src1_modifiers,"));
715 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
717 !if(!eq(HasModifiers, 0),
718 getAsm32<NumSrcArgs>.ret,
719 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
723 class VOPProfile <list<ValueType> _ArgVT> {
725 field list<ValueType> ArgVT = _ArgVT;
727 field ValueType DstVT = ArgVT[0];
728 field ValueType Src0VT = ArgVT[1];
729 field ValueType Src1VT = ArgVT[2];
730 field ValueType Src2VT = ArgVT[3];
731 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
732 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
733 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
734 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
735 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
736 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
738 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
739 field bit HasModifiers = hasModifiers<Src0VT>.ret;
741 field dag Outs = (outs DstRC:$dst);
743 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
744 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
747 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
748 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
751 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
752 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
753 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
754 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
755 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
756 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
757 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
758 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
759 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
761 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
762 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
763 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
764 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
765 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
766 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
767 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
768 let Src0RC32 = VCSrc_32;
770 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
771 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
773 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
774 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
775 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
776 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
779 class VOP <string opName> {
780 string OpName = opName;
783 class VOP2_REV <string revOp, bit isOrig> {
784 string RevOp = revOp;
788 class AtomicNoRet <string noRetOp, bit isRet> {
789 string NoRetOp = noRetOp;
793 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
794 VOP1Common <outs, ins, "", pattern>,
796 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
800 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
802 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
804 def _si : VOP1<op.SI, outs, ins, asm, []>,
805 SIMCInstr <opName#"_e32", SISubtarget.SI>;
806 def _vi : VOP1<op.VI, outs, ins, asm, []>,
807 SIMCInstr <opName#"_e32", SISubtarget.VI>;
810 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
811 VOP2Common <outs, ins, "", pattern>,
813 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
817 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
818 string opName, string revOpSI, string revOpVI> {
819 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
820 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
822 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
823 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
824 SIMCInstr <opName#"_e32", SISubtarget.SI>;
825 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
826 VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
827 SIMCInstr <opName#"_e32", SISubtarget.VI>;
830 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
832 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
833 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
834 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
835 bits<2> omod = !if(HasModifiers, ?, 0);
836 bits<1> clamp = !if(HasModifiers, ?, 0);
837 bits<9> src1 = !if(HasSrc1, ?, 0);
838 bits<9> src2 = !if(HasSrc2, ?, 0);
841 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
842 VOP3Common <outs, ins, "", pattern>,
844 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
848 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
849 VOP3Common <outs, ins, asm, []>,
851 SIMCInstr<opName#"_e64", SISubtarget.SI>;
853 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
854 VOP3Common <outs, ins, asm, []>,
856 SIMCInstr <opName#"_e64", SISubtarget.VI>;
858 // VI only instruction
859 class VOP3_vi <bits<10> op, string opName, dag outs, dag ins, string asm,
860 list<dag> pattern, int NumSrcArgs, bit HasMods = 1> :
861 VOP3Common <outs, ins, asm, pattern>,
864 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
865 !if(!eq(NumSrcArgs, 2), 0, 1),
868 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
869 string opName, int NumSrcArgs, bit HasMods = 1> {
871 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
873 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
874 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
875 !if(!eq(NumSrcArgs, 2), 0, 1),
877 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
878 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
879 !if(!eq(NumSrcArgs, 2), 0, 1),
883 // VOP3_m without source modifiers
884 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
885 string opName, int NumSrcArgs, bit HasMods = 1> {
887 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
889 let src0_modifiers = 0,
891 src2_modifiers = 0 in {
892 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
893 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
897 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
898 list<dag> pattern, string opName, bit HasMods = 1> {
900 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
902 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
903 VOP3DisableFields<0, 0, HasMods>;
905 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
906 VOP3DisableFields<0, 0, HasMods>;
909 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
910 list<dag> pattern, string opName, string revOpSI, string revOpVI,
911 bit HasMods = 1, bit UseFullOp = 0> {
913 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
914 VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>;
916 def _si : VOP3_Real_si <op.SI3,
917 outs, ins, asm, opName>,
918 VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
919 VOP3DisableFields<1, 0, HasMods>;
921 def _vi : VOP3_Real_vi <op.VI3,
922 outs, ins, asm, opName>,
923 VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
924 VOP3DisableFields<1, 0, HasMods>;
927 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
928 list<dag> pattern, string opName, string revOp,
929 bit HasMods = 1, bit UseFullOp = 0> {
930 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
931 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
933 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
934 // can write it into any SGPR. We currently don't use the carry out,
935 // so for now hardcode it to VCC as well.
936 let sdst = SIOperand.VCC, Defs = [VCC] in {
937 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
938 VOP3DisableFields<1, 0, HasMods>,
939 SIMCInstr<opName#"_e64", SISubtarget.SI>,
940 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
942 // TODO: Do we need this VI variant here?
943 /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, pattern>,
944 VOP3DisableFields<1, 0, HasMods>,
945 SIMCInstr<opName#"_e64", SISubtarget.VI>,
946 VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
947 } // End sdst = SIOperand.VCC, Defs = [VCC]
950 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
951 list<dag> pattern, string opName,
952 bit HasMods, bit defExec> {
954 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
956 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
957 VOP3DisableFields<1, 0, HasMods> {
958 let Defs = !if(defExec, [EXEC], []);
961 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
962 VOP3DisableFields<1, 0, HasMods> {
963 let Defs = !if(defExec, [EXEC], []);
967 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
968 dag ins32, string asm32, list<dag> pat32,
969 dag ins64, string asm64, list<dag> pat64,
972 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
974 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
977 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
978 SDPatternOperator node = null_frag> : VOP1_Helper <
980 P.Ins32, P.Asm32, [],
983 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
984 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
985 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
989 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
990 SDPatternOperator node = null_frag> {
992 def _e32 : VOP1 <op.SI, P.Outs, P.Ins32, opName#P.Asm32, []>,
995 def _e64 : VOP3Common <P.Outs, P.Ins64, opName#P.Asm64,
997 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
998 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
999 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])>,
1002 VOP3DisableFields<0, 0, P.HasModifiers>;
1005 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1006 dag ins32, string asm32, list<dag> pat32,
1007 dag ins64, string asm64, list<dag> pat64,
1008 string revOpSI, string revOpVI, bit HasMods> {
1009 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>;
1011 defm _e64 : VOP3_2_m <op,
1012 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods
1016 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1017 SDPatternOperator node = null_frag,
1018 string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper <
1020 P.Ins32, P.Asm32, [],
1024 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1025 i1:$clamp, i32:$omod)),
1026 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1027 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1028 revOpSI, revOpVI, P.HasModifiers
1031 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1032 dag ins32, string asm32, list<dag> pat32,
1033 dag ins64, string asm64, list<dag> pat64,
1034 string revOp, bit HasMods> {
1036 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>;
1038 defm _e64 : VOP3b_2_m <op,
1039 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1043 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1044 SDPatternOperator node = null_frag,
1045 string revOp = opName> : VOP2b_Helper <
1047 P.Ins32, P.Asm32, [],
1051 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1052 i1:$clamp, i32:$omod)),
1053 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1054 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1055 revOp, P.HasModifiers
1058 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1059 VOPCCommon <ins, "", pattern>,
1061 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1065 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1066 string opName, bit DefExec> {
1067 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1069 def _si : VOPC<op.SI, ins, asm, []>,
1070 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1071 let Defs = !if(DefExec, [EXEC], []);
1074 def _vi : VOPC<op.VI, ins, asm, []>,
1075 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1076 let Defs = !if(DefExec, [EXEC], []);
1080 multiclass VOPC_Helper <vopc op, string opName,
1081 dag ins32, string asm32, list<dag> pat32,
1082 dag out64, dag ins64, string asm64, list<dag> pat64,
1083 bit HasMods, bit DefExec> {
1084 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1086 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1087 opName, HasMods, DefExec>;
1090 multiclass VOPCInst <vopc op, string opName,
1091 VOPProfile P, PatLeaf cond = COND_NULL,
1092 bit DefExec = 0> : VOPC_Helper <
1094 P.Ins32, P.Asm32, [],
1095 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1098 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1099 i1:$clamp, i32:$omod)),
1100 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1102 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1103 P.HasModifiers, DefExec
1106 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1107 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1109 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1110 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1112 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1113 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1115 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1116 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1119 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1120 PatLeaf cond = COND_NULL>
1121 : VOPCInst <op, opName, P, cond, 1>;
1123 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1124 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1126 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1127 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1129 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1130 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1132 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1133 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1135 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1136 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1137 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1140 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1141 SDPatternOperator node = null_frag> : VOP3_Helper <
1142 op, opName, P.Outs, P.Ins64, P.Asm64,
1143 !if(!eq(P.NumSrcArgs, 3),
1146 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1147 i1:$clamp, i32:$omod)),
1148 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1149 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1150 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1152 !if(!eq(P.NumSrcArgs, 2),
1155 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1156 i1:$clamp, i32:$omod)),
1157 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1158 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1159 /* P.NumSrcArgs == 1 */,
1162 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1163 i1:$clamp, i32:$omod))))],
1164 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1165 P.NumSrcArgs, P.HasModifiers
1168 class VOP3InstVI <bits<10> op, string opName, VOPProfile P,
1169 SDPatternOperator node = null_frag> : VOP3_vi <
1170 op, opName#"_vi", P.Outs, P.Ins64, opName#P.Asm64,
1171 !if(!eq(P.NumSrcArgs, 3),
1174 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1175 i1:$clamp, i32:$omod)),
1176 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1177 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1178 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1180 !if(!eq(P.NumSrcArgs, 2),
1183 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1184 i1:$clamp, i32:$omod)),
1185 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1186 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1187 /* P.NumSrcArgs == 1 */,
1190 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1191 i1:$clamp, i32:$omod))))],
1192 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1193 P.NumSrcArgs, P.HasModifiers
1196 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterClass arc,
1197 string opName, list<dag> pattern> :
1199 op, (outs vrc:$vdst, SReg_64:$sdst),
1200 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1201 InputModsNoDefault:$src1_modifiers, arc:$src1,
1202 InputModsNoDefault:$src2_modifiers, arc:$src2,
1203 ClampMod:$clamp, omod:$omod),
1204 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1205 opName, opName, 1, 1
1208 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1209 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1211 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1212 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
1215 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1216 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1217 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1218 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1219 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1220 i32:$src1_modifiers, P.Src1VT:$src1,
1221 i32:$src2_modifiers, P.Src2VT:$src2,
1225 //===----------------------------------------------------------------------===//
1226 // Interpolation opcodes
1227 //===----------------------------------------------------------------------===//
1229 class VINTRP_Pseudo <string opName, dag outs, dag ins, string asm,
1230 list<dag> pattern> :
1231 VINTRPCommon <outs, ins, asm, pattern>,
1232 SIMCInstr<opName, SISubtarget.NONE> {
1236 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1237 string asm, list<dag> pattern> :
1238 VINTRPCommon <outs, ins, asm, pattern>,
1240 SIMCInstr<opName, SISubtarget.SI>;
1242 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1243 string asm, list<dag> pattern> :
1244 VINTRPCommon <outs, ins, asm, pattern>,
1246 SIMCInstr<opName, SISubtarget.VI>;
1248 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1249 string disableEncoding = "", string constraints = "",
1250 list<dag> pattern = []> {
1251 let DisableEncoding = disableEncoding,
1252 Constraints = constraints in {
1253 def "" : VINTRP_Pseudo <opName, outs, ins, asm, pattern>;
1255 def _si : VINTRP_Real_si <op, opName, outs, ins, asm, pattern>;
1257 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm, pattern>;
1261 //===----------------------------------------------------------------------===//
1262 // Vector I/O classes
1263 //===----------------------------------------------------------------------===//
1265 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1266 DS <outs, ins, "", pattern>,
1267 SIMCInstr <opName, SISubtarget.NONE> {
1271 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1272 DS <outs, ins, asm, []>,
1274 SIMCInstr <opName, SISubtarget.SI>;
1276 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1277 DS <outs, ins, asm, []>,
1279 SIMCInstr <opName, SISubtarget.VI>;
1281 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1282 DS <outs, ins, asm, []>,
1284 SIMCInstr <opName, SISubtarget.SI> {
1286 // Single load interpret the 2 i8imm operands as a single i16 offset.
1288 let offset0 = offset{7-0};
1289 let offset1 = offset{15-8};
1292 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1293 DS <outs, ins, asm, []>,
1295 SIMCInstr <opName, SISubtarget.VI> {
1297 // Single load interpret the 2 i8imm operands as a single i16 offset.
1299 let offset0 = offset{7-0};
1300 let offset1 = offset{15-8};
1303 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1305 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1306 def "" : DS_Pseudo <opName, outs, ins, pat>;
1308 let data0 = 0, data1 = 0 in {
1309 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1310 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1315 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1319 (outs regClass:$vdst),
1320 (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset, M0Reg:$m0),
1321 asm#" $vdst, $addr"#"$offset"#" [M0]",
1324 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1326 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1327 def "" : DS_Pseudo <opName, outs, ins, pat>;
1329 let data0 = 0, data1 = 0 in {
1330 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1331 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1336 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1340 (outs regClass:$vdst),
1341 (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1343 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1346 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1347 string asm, list<dag> pat> {
1348 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1349 def "" : DS_Pseudo <opName, outs, ins, pat>;
1351 let data1 = 0, vdst = 0 in {
1352 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1353 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1358 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1363 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1364 asm#" $addr, $data0"#"$offset"#" [M0]",
1367 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1368 string asm, list<dag> pat> {
1369 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1370 def "" : DS_Pseudo <opName, outs, ins, pat>;
1373 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1374 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1379 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1384 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
1385 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1386 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1389 class DS_1A_si <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
1390 DS_si <op, outs, ins, asm, pat> {
1393 // Single load interpret the 2 i8imm operands as a single i16 offset.
1394 let offset0 = offset{7-0};
1395 let offset1 = offset{15-8};
1397 let hasSideEffects = 0;
1400 // 1 address, 1 data.
1401 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1404 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1405 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
1406 AtomicNoRet<noRetOp, 1> {
1412 let hasPostISelHook = 1; // Adjusted to no return version.
1415 // 1 address, 2 data.
1416 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1419 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1420 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1422 AtomicNoRet<noRetOp, 1> {
1425 let hasPostISelHook = 1; // Adjusted to no return version.
1428 // 1 address, 2 data.
1429 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1432 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1433 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1435 AtomicNoRet<noRetOp, 0> {
1440 // 1 address, 1 data.
1441 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1444 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1445 asm#" $addr, $data0"#"$offset"#" [M0]",
1447 AtomicNoRet<noRetOp, 0> {
1454 //===----------------------------------------------------------------------===//
1456 //===----------------------------------------------------------------------===//
1458 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1459 MTBUF <outs, ins, "", pattern>,
1460 SIMCInstr<opName, SISubtarget.NONE> {
1464 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1466 MTBUF <outs, ins, asm, []>,
1468 SIMCInstr<opName, SISubtarget.SI>;
1470 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1471 MTBUF <outs, ins, asm, []>,
1473 SIMCInstr <opName, SISubtarget.VI>;
1475 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1476 list<dag> pattern> {
1478 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1480 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1482 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1486 let mayStore = 1, mayLoad = 0 in {
1488 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1489 RegisterClass regClass> : MTBUF_m <
1491 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1492 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1493 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1494 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1495 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1498 } // mayStore = 1, mayLoad = 0
1500 let mayLoad = 1, mayStore = 0 in {
1502 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1503 RegisterClass regClass> : MTBUF_m <
1504 op, opName, (outs regClass:$dst),
1505 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1506 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1507 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1508 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1509 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1512 } // mayLoad = 1, mayStore = 0
1514 //===----------------------------------------------------------------------===//
1516 //===----------------------------------------------------------------------===//
1518 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1519 MUBUF <outs, ins, asm, pattern>, MUBUFe <op>;
1521 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1522 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op>;
1524 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1526 bit IsAddr64 = is_addr64;
1527 string OpName = NAME # suffix;
1530 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1531 : MUBUF_si <op, outs, ins, asm, pattern> {
1541 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1542 : MUBUF_si <op, outs, ins, asm, pattern> {
1552 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1553 ValueType vt, SDPatternOperator atomic> {
1555 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1557 // No return variants
1560 def _ADDR64 : MUBUFAtomicAddr64 <
1562 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1563 mbuf_offset:$offset, slc:$slc),
1564 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1565 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1567 def _OFFSET : MUBUFAtomicOffset <
1569 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1570 SSrc_32:$soffset, slc:$slc),
1571 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1572 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1575 // Variant that return values
1576 let glc = 1, Constraints = "$vdata = $vdata_in",
1577 DisableEncoding = "$vdata_in" in {
1579 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1580 op, (outs rc:$vdata),
1581 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1582 mbuf_offset:$offset, slc:$slc),
1583 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1585 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1586 i1:$slc), vt:$vdata_in))]
1587 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1589 def _RTN_OFFSET : MUBUFAtomicOffset <
1590 op, (outs rc:$vdata),
1591 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1592 SSrc_32:$soffset, slc:$slc),
1593 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1595 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1596 i1:$slc), vt:$vdata_in))]
1597 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1601 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1604 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1605 ValueType load_vt = i32,
1606 SDPatternOperator ld = null_frag> {
1608 let lds = 0, mayLoad = 1 in {
1612 let offen = 0, idxen = 0, vaddr = 0 in {
1613 def _OFFSET : MUBUF_si <op, (outs regClass:$vdata),
1614 (ins SReg_128:$srsrc,
1615 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1616 slc:$slc, tfe:$tfe),
1617 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1618 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1619 i32:$soffset, i16:$offset,
1620 i1:$glc, i1:$slc, i1:$tfe)))]>,
1621 MUBUFAddr64Table<0>;
1624 let offen = 1, idxen = 0 in {
1625 def _OFFEN : MUBUF_si <op, (outs regClass:$vdata),
1626 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1627 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1629 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1632 let offen = 0, idxen = 1 in {
1633 def _IDXEN : MUBUF_si <op, (outs regClass:$vdata),
1634 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1635 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1636 slc:$slc, tfe:$tfe),
1637 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1640 let offen = 1, idxen = 1 in {
1641 def _BOTHEN : MUBUF_si <op, (outs regClass:$vdata),
1642 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1643 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1644 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1648 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1649 def _ADDR64 : MUBUF_si <op, (outs regClass:$vdata),
1650 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1651 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1652 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1653 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1658 multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
1659 ValueType load_vt = i32,
1660 SDPatternOperator ld = null_frag> {
1662 let lds = 0, mayLoad = 1 in {
1663 let offen = 0, idxen = 0, vaddr = 0 in {
1664 def _OFFSET : MUBUF_vi <op, (outs regClass:$vdata),
1665 (ins SReg_128:$srsrc,
1666 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1667 slc:$slc, tfe:$tfe),
1668 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1669 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1670 i32:$soffset, i16:$offset,
1671 i1:$glc, i1:$slc, i1:$tfe)))]>,
1672 MUBUFAddr64Table<0>;
1675 let offen = 1, idxen = 0 in {
1676 def _OFFEN : MUBUF_vi <op, (outs regClass:$vdata),
1677 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1678 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1680 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1683 let offen = 0, idxen = 1 in {
1684 def _IDXEN : MUBUF_vi <op, (outs regClass:$vdata),
1685 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1686 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1687 slc:$slc, tfe:$tfe),
1688 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1691 let offen = 1, idxen = 1 in {
1692 def _BOTHEN : MUBUF_vi <op, (outs regClass:$vdata),
1693 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1694 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1695 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1700 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1701 ValueType store_vt, SDPatternOperator st> {
1703 let addr64 = 0, lds = 0 in {
1707 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1708 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1710 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1711 "$glc"#"$slc"#"$tfe",
1715 let offen = 0, idxen = 0, vaddr = 0 in {
1716 def _OFFSET : MUBUF_si <
1718 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1719 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1720 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1721 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1722 i16:$offset, i1:$glc, i1:$slc,
1724 >, MUBUFAddr64Table<0>;
1725 } // offen = 0, idxen = 0, vaddr = 0
1727 let offen = 1, idxen = 0 in {
1728 def _OFFEN : MUBUF_si <
1730 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1731 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1732 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1733 "$glc"#"$slc"#"$tfe",
1736 } // end offen = 1, idxen = 0
1738 } // End addr64 = 0, lds = 0
1740 def _ADDR64 : MUBUF_si <
1742 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1743 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1744 [(st store_vt:$vdata,
1745 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1759 let soffset = 128; // ZERO
1763 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1764 FLAT <op, (outs regClass:$data),
1765 (ins VReg_64:$addr),
1766 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1773 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1774 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1775 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1787 class MIMG_Mask <string op, int channels> {
1789 int Channels = channels;
1792 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1793 RegisterClass dst_rc,
1794 RegisterClass src_rc> : MIMG <
1796 (outs dst_rc:$vdata),
1797 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1798 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1800 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1801 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1806 let hasPostISelHook = 1;
1809 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1810 RegisterClass dst_rc,
1812 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1813 MIMG_Mask<asm#"_V1", channels>;
1814 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1815 MIMG_Mask<asm#"_V2", channels>;
1816 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1817 MIMG_Mask<asm#"_V4", channels>;
1820 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1821 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1822 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1823 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1824 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1827 class MIMG_Sampler_Helper <bits<7> op, string asm,
1828 RegisterClass dst_rc,
1829 RegisterClass src_rc> : MIMG <
1831 (outs dst_rc:$vdata),
1832 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1833 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1834 SReg_256:$srsrc, SReg_128:$ssamp),
1835 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1836 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1840 let hasPostISelHook = 1;
1843 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1844 RegisterClass dst_rc,
1846 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1847 MIMG_Mask<asm#"_V1", channels>;
1848 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1849 MIMG_Mask<asm#"_V2", channels>;
1850 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1851 MIMG_Mask<asm#"_V4", channels>;
1852 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1853 MIMG_Mask<asm#"_V8", channels>;
1854 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1855 MIMG_Mask<asm#"_V16", channels>;
1858 multiclass MIMG_Sampler <bits<7> op, string asm> {
1859 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1860 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1861 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1862 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1865 class MIMG_Gather_Helper <bits<7> op, string asm,
1866 RegisterClass dst_rc,
1867 RegisterClass src_rc> : MIMG <
1869 (outs dst_rc:$vdata),
1870 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1871 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1872 SReg_256:$srsrc, SReg_128:$ssamp),
1873 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1874 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1879 // DMASK was repurposed for GATHER4. 4 components are always
1880 // returned and DMASK works like a swizzle - it selects
1881 // the component to fetch. The only useful DMASK values are
1882 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1883 // (red,red,red,red) etc.) The ISA document doesn't mention
1885 // Therefore, disable all code which updates DMASK by setting these two:
1887 let hasPostISelHook = 0;
1890 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1891 RegisterClass dst_rc,
1893 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1894 MIMG_Mask<asm#"_V1", channels>;
1895 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1896 MIMG_Mask<asm#"_V2", channels>;
1897 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1898 MIMG_Mask<asm#"_V4", channels>;
1899 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1900 MIMG_Mask<asm#"_V8", channels>;
1901 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1902 MIMG_Mask<asm#"_V16", channels>;
1905 multiclass MIMG_Gather <bits<7> op, string asm> {
1906 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1907 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1908 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1909 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1912 //===----------------------------------------------------------------------===//
1913 // Vector instruction mappings
1914 //===----------------------------------------------------------------------===//
1916 // Maps an opcode in e32 form to its e64 equivalent
1917 def getVOPe64 : InstrMapping {
1918 let FilterClass = "VOP";
1919 let RowFields = ["OpName"];
1920 let ColFields = ["Size"];
1922 let ValueCols = [["8"]];
1925 // Maps an opcode in e64 form to its e32 equivalent
1926 def getVOPe32 : InstrMapping {
1927 let FilterClass = "VOP";
1928 let RowFields = ["OpName"];
1929 let ColFields = ["Size"];
1931 let ValueCols = [["4"]];
1934 // Maps an original opcode to its commuted version
1935 def getCommuteRev : InstrMapping {
1936 let FilterClass = "VOP2_REV";
1937 let RowFields = ["RevOp"];
1938 let ColFields = ["IsOrig"];
1940 let ValueCols = [["0"]];
1943 def getMaskedMIMGOp : InstrMapping {
1944 let FilterClass = "MIMG_Mask";
1945 let RowFields = ["Op"];
1946 let ColFields = ["Channels"];
1948 let ValueCols = [["1"], ["2"], ["3"] ];
1951 // Maps an commuted opcode to its original version
1952 def getCommuteOrig : InstrMapping {
1953 let FilterClass = "VOP2_REV";
1954 let RowFields = ["RevOp"];
1955 let ColFields = ["IsOrig"];
1957 let ValueCols = [["1"]];
1960 def getMCOpcodeGen : InstrMapping {
1961 let FilterClass = "SIMCInstr";
1962 let RowFields = ["PseudoInstr"];
1963 let ColFields = ["Subtarget"];
1964 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1965 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
1968 def getAddr64Inst : InstrMapping {
1969 let FilterClass = "MUBUFAddr64Table";
1970 let RowFields = ["OpName"];
1971 let ColFields = ["IsAddr64"];
1973 let ValueCols = [["1"]];
1976 // Maps an atomic opcode to its version with a return value.
1977 def getAtomicRetOp : InstrMapping {
1978 let FilterClass = "AtomicNoRet";
1979 let RowFields = ["NoRetOp"];
1980 let ColFields = ["IsRet"];
1982 let ValueCols = [["1"]];
1985 // Maps an atomic opcode to its returnless version.
1986 def getAtomicNoRetOp : InstrMapping {
1987 let FilterClass = "AtomicNoRet";
1988 let RowFields = ["NoRetOp"];
1989 let ColFields = ["IsRet"];
1991 let ValueCols = [["0"]];
1994 include "SIInstructions.td"
1995 include "CIInstructions.td"
1996 include "VIInstructions.td"