1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
44 class sop1 <bits<8> si, bits<8> vi = si> {
45 field bits<8> SI = si;
46 field bits<8> VI = vi;
49 class sop2 <bits<7> si, bits<7> vi = si> {
50 field bits<7> SI = si;
51 field bits<7> VI = vi;
54 class sopk <bits<5> si, bits<5> vi = si> {
55 field bits<5> SI = si;
56 field bits<5> VI = vi;
59 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
60 // in AMDGPUMCInstLower.h
67 //===----------------------------------------------------------------------===//
69 //===----------------------------------------------------------------------===//
71 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
72 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
73 [SDNPMayLoad, SDNPMemOperand]
76 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
78 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
79 SDTCisVT<1, iAny>, // vdata(VGPR)
80 SDTCisVT<2, i32>, // num_channels(imm)
81 SDTCisVT<3, i32>, // vaddr(VGPR)
82 SDTCisVT<4, i32>, // soffset(SGPR)
83 SDTCisVT<5, i32>, // inst_offset(imm)
84 SDTCisVT<6, i32>, // dfmt(imm)
85 SDTCisVT<7, i32>, // nfmt(imm)
86 SDTCisVT<8, i32>, // offen(imm)
87 SDTCisVT<9, i32>, // idxen(imm)
88 SDTCisVT<10, i32>, // glc(imm)
89 SDTCisVT<11, i32>, // slc(imm)
90 SDTCisVT<12, i32> // tfe(imm)
92 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
95 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
100 class SDSample<string opcode> : SDNode <opcode,
101 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
102 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
105 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
106 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
107 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
108 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
110 def SIconstdata_ptr : SDNode<
111 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
114 // Transformation function, extract the lower 32bit of a 64bit immediate
115 def LO32 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
119 def LO32f : SDNodeXForm<fpimm, [{
120 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
121 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
124 // Transformation function, extract the upper 32bit of a 64bit immediate
125 def HI32 : SDNodeXForm<imm, [{
126 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
129 def HI32f : SDNodeXForm<fpimm, [{
130 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
131 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
134 def IMM8bitDWORD : PatLeaf <(imm),
135 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
138 def as_dword_i32imm : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
142 def as_i1imm : SDNodeXForm<imm, [{
143 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
146 def as_i8imm : SDNodeXForm<imm, [{
147 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
150 def as_i16imm : SDNodeXForm<imm, [{
151 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
154 def as_i32imm: SDNodeXForm<imm, [{
155 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
158 def as_i64imm: SDNodeXForm<imm, [{
159 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
162 def IMM8bit : PatLeaf <(imm),
163 [{return isUInt<8>(N->getZExtValue());}]
166 def IMM12bit : PatLeaf <(imm),
167 [{return isUInt<12>(N->getZExtValue());}]
170 def IMM16bit : PatLeaf <(imm),
171 [{return isUInt<16>(N->getZExtValue());}]
174 def IMM20bit : PatLeaf <(imm),
175 [{return isUInt<20>(N->getZExtValue());}]
178 def IMM32bit : PatLeaf <(imm),
179 [{return isUInt<32>(N->getZExtValue());}]
182 def mubuf_vaddr_offset : PatFrag<
183 (ops node:$ptr, node:$offset, node:$imm_offset),
184 (add (add node:$ptr, node:$offset), node:$imm_offset)
187 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
188 return isInlineImmediate(N);
191 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
192 return isInlineImmediate(N);
195 class SGPRImm <dag frag> : PatLeaf<frag, [{
196 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
197 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
200 const SIRegisterInfo *SIRI =
201 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
202 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
204 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
211 //===----------------------------------------------------------------------===//
213 //===----------------------------------------------------------------------===//
215 def FRAMEri32 : Operand<iPTR> {
216 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
219 def sopp_brtarget : Operand<OtherVT> {
220 let EncoderMethod = "getSOPPBrEncoding";
221 let OperandType = "OPERAND_PCREL";
224 include "SIInstrFormats.td"
225 include "VIInstrFormats.td"
227 let OperandType = "OPERAND_IMMEDIATE" in {
229 def offen : Operand<i1> {
230 let PrintMethod = "printOffen";
232 def idxen : Operand<i1> {
233 let PrintMethod = "printIdxen";
235 def addr64 : Operand<i1> {
236 let PrintMethod = "printAddr64";
238 def mbuf_offset : Operand<i16> {
239 let PrintMethod = "printMBUFOffset";
241 def ds_offset : Operand<i16> {
242 let PrintMethod = "printDSOffset";
244 def ds_offset0 : Operand<i8> {
245 let PrintMethod = "printDSOffset0";
247 def ds_offset1 : Operand<i8> {
248 let PrintMethod = "printDSOffset1";
250 def glc : Operand <i1> {
251 let PrintMethod = "printGLC";
253 def slc : Operand <i1> {
254 let PrintMethod = "printSLC";
256 def tfe : Operand <i1> {
257 let PrintMethod = "printTFE";
260 def omod : Operand <i32> {
261 let PrintMethod = "printOModSI";
264 def ClampMod : Operand <i1> {
265 let PrintMethod = "printClampSI";
268 } // End OperandType = "OPERAND_IMMEDIATE"
270 //===----------------------------------------------------------------------===//
272 //===----------------------------------------------------------------------===//
274 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
275 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
277 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
278 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
279 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
280 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
281 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
282 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
284 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
285 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
286 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
288 //===----------------------------------------------------------------------===//
289 // SI assembler operands
290 //===----------------------------------------------------------------------===//
310 //===----------------------------------------------------------------------===//
312 // SI Instruction multiclass helpers.
314 // Instructions with _32 take 32-bit operands.
315 // Instructions with _64 take 64-bit operands.
317 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
318 // encoding is the standard encoding, but instruction that make use of
319 // any of the instruction modifiers must use the 64-bit encoding.
321 // Instructions with _e32 use the 32-bit encoding.
322 // Instructions with _e64 use the 64-bit encoding.
324 //===----------------------------------------------------------------------===//
326 class SIMCInstr <string pseudo, int subtarget> {
327 string PseudoInstr = pseudo;
328 int Subtarget = subtarget;
331 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
335 class EXPCommon : InstSI<
337 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
338 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
339 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
348 let isPseudo = 1 in {
349 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
352 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
354 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
357 //===----------------------------------------------------------------------===//
359 //===----------------------------------------------------------------------===//
361 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
362 SOP1 <outs, ins, "", pattern>,
363 SIMCInstr<opName, SISubtarget.NONE> {
367 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm,
369 SOP1 <outs, ins, asm, pattern>,
371 SIMCInstr<opName, SISubtarget.SI>;
373 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm,
375 SOP1 <outs, ins, asm, pattern>,
377 SIMCInstr<opName, SISubtarget.VI>;
379 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
380 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
383 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
384 opName#" $dst, $src0", pattern>;
386 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
387 opName#" $dst, $src0", pattern>;
390 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
391 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
394 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
395 opName#" $dst, $src0", pattern>;
397 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
398 opName#" $dst, $src0", pattern>;
401 // no input, 64-bit output.
402 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
403 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
405 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
406 opName#" $dst", pattern> {
410 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
411 opName#" $dst", pattern> {
416 // 64-bit input, 32-bit output.
417 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
418 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
421 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
422 opName#" $dst, $src0", pattern>;
424 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
425 opName#" $dst, $src0", pattern>;
428 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
429 SOP2<outs, ins, "", pattern>,
430 SIMCInstr<opName, SISubtarget.NONE> {
435 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm,
437 SOP2<outs, ins, asm, pattern>,
439 SIMCInstr<opName, SISubtarget.SI>;
441 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm,
443 SOP2<outs, ins, asm, pattern>,
445 SIMCInstr<opName, SISubtarget.VI>;
447 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
448 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
449 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
451 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
452 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
453 opName#" $dst, $src0, $src1 [$scc]", pattern>;
455 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
456 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
457 opName#" $dst, $src0, $src1 [$scc]", pattern>;
460 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
461 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
462 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
464 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
465 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
467 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
468 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
471 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
472 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
473 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
475 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
476 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
478 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
479 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
482 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
483 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
484 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
486 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
487 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
489 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
490 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
494 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
495 string opName, PatLeaf cond> : SOPC <
496 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
497 opName#" $dst, $src0, $src1", []>;
499 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
500 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
502 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
503 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
505 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
506 SOPK <outs, ins, "", pattern>,
507 SIMCInstr<opName, SISubtarget.NONE> {
511 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm,
513 SOPK <outs, ins, asm, pattern>,
515 SIMCInstr<opName, SISubtarget.SI>;
517 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm,
519 SOPK <outs, ins, asm, pattern>,
521 SIMCInstr<opName, SISubtarget.VI>;
523 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
524 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
527 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
528 opName#" $dst, $src0", pattern>;
530 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
531 opName#" $dst, $src0", pattern>;
534 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
535 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
536 (ins SReg_32:$src0, u16imm:$src1), pattern>;
538 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
539 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
541 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
542 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
545 //===----------------------------------------------------------------------===//
547 //===----------------------------------------------------------------------===//
549 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
550 SMRD <outs, ins, "", pattern>,
551 SIMCInstr<opName, SISubtarget.NONE> {
555 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
557 SMRD <outs, ins, asm, []>,
559 SIMCInstr<opName, SISubtarget.SI>;
561 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
563 SMRD <outs, ins, asm, []>,
565 SIMCInstr<opName, SISubtarget.VI>;
567 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
568 string asm, list<dag> pattern> {
570 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
572 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
574 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
577 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
578 RegisterClass dstClass> {
580 op, opName#"_IMM", 1, (outs dstClass:$dst),
581 (ins baseClass:$sbase, u32imm:$offset),
582 opName#" $dst, $sbase, $offset", []
585 defm _SGPR : SMRD_m <
586 op, opName#"_SGPR", 0, (outs dstClass:$dst),
587 (ins baseClass:$sbase, SReg_32:$soff),
588 opName#" $dst, $sbase, $soff", []
592 //===----------------------------------------------------------------------===//
593 // Vector ALU classes
594 //===----------------------------------------------------------------------===//
596 // This must always be right before the operand being input modified.
597 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
598 let PrintMethod = "printOperandAndMods";
600 def InputModsNoDefault : Operand <i32> {
601 let PrintMethod = "printOperandAndMods";
604 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
606 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
607 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
611 // Returns the register class to use for the destination of VOP[123C]
612 // instructions for the given VT.
613 class getVALUDstForVT<ValueType VT> {
614 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
617 // Returns the register class to use for source 0 of VOP[12C]
618 // instructions for the given VT.
619 class getVOPSrc0ForVT<ValueType VT> {
620 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
623 // Returns the register class to use for source 1 of VOP[12C] for the
625 class getVOPSrc1ForVT<ValueType VT> {
626 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
629 // Returns the register classes for the source arguments of a VOP[12C]
630 // instruction for the given SrcVTs.
631 class getInRC32 <list<ValueType> SrcVT> {
632 list<RegisterClass> ret = [
633 getVOPSrc0ForVT<SrcVT[0]>.ret,
634 getVOPSrc1ForVT<SrcVT[1]>.ret
638 // Returns the register class to use for sources of VOP3 instructions for the
640 class getVOP3SrcForVT<ValueType VT> {
641 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
644 // Returns the register classes for the source arguments of a VOP3
645 // instruction for the given SrcVTs.
646 class getInRC64 <list<ValueType> SrcVT> {
647 list<RegisterClass> ret = [
648 getVOP3SrcForVT<SrcVT[0]>.ret,
649 getVOP3SrcForVT<SrcVT[1]>.ret,
650 getVOP3SrcForVT<SrcVT[2]>.ret
654 // Returns 1 if the source arguments have modifiers, 0 if they do not.
655 class hasModifiers<ValueType SrcVT> {
656 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
657 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
660 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
661 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
662 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
663 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
667 // Returns the input arguments for VOP3 instructions for the given SrcVT.
668 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
669 RegisterClass Src2RC, int NumSrcArgs,
673 !if (!eq(NumSrcArgs, 1),
674 !if (!eq(HasModifiers, 1),
675 // VOP1 with modifiers
676 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
677 ClampMod:$clamp, omod:$omod)
679 // VOP1 without modifiers
682 !if (!eq(NumSrcArgs, 2),
683 !if (!eq(HasModifiers, 1),
684 // VOP 2 with modifiers
685 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
686 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
687 ClampMod:$clamp, omod:$omod)
689 // VOP2 without modifiers
690 (ins Src0RC:$src0, Src1RC:$src1)
692 /* NumSrcArgs == 3 */,
693 !if (!eq(HasModifiers, 1),
694 // VOP3 with modifiers
695 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
696 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
697 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
698 ClampMod:$clamp, omod:$omod)
700 // VOP3 without modifiers
701 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
705 // Returns the assembly string for the inputs and outputs of a VOP[12C]
706 // instruction. This does not add the _e32 suffix, so it can be reused
708 class getAsm32 <int NumSrcArgs> {
709 string src1 = ", $src1";
710 string src2 = ", $src2";
711 string ret = " $dst, $src0"#
712 !if(!eq(NumSrcArgs, 1), "", src1)#
713 !if(!eq(NumSrcArgs, 3), src2, "");
716 // Returns the assembly string for the inputs and outputs of a VOP3
718 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
719 string src0 = "$src0_modifiers,";
720 string src1 = !if(!eq(NumSrcArgs, 1), "",
721 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
722 " $src1_modifiers,"));
723 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
725 !if(!eq(HasModifiers, 0),
726 getAsm32<NumSrcArgs>.ret,
727 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
731 class VOPProfile <list<ValueType> _ArgVT> {
733 field list<ValueType> ArgVT = _ArgVT;
735 field ValueType DstVT = ArgVT[0];
736 field ValueType Src0VT = ArgVT[1];
737 field ValueType Src1VT = ArgVT[2];
738 field ValueType Src2VT = ArgVT[3];
739 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
740 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
741 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
742 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
743 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
744 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
746 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
747 field bit HasModifiers = hasModifiers<Src0VT>.ret;
749 field dag Outs = (outs DstRC:$dst);
751 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
752 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
755 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
756 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
759 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
760 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
761 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
762 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
763 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
764 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
765 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
766 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
767 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
769 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
770 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
771 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
772 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
773 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
774 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
775 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
776 let Src0RC32 = VCSrc_32;
778 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
779 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
781 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
782 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
783 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
784 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
787 class VOP <string opName> {
788 string OpName = opName;
791 class VOP2_REV <string revOp, bit isOrig> {
792 string RevOp = revOp;
796 class AtomicNoRet <string noRetOp, bit isRet> {
797 string NoRetOp = noRetOp;
801 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
802 VOP1Common <outs, ins, "", pattern>,
804 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
808 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
810 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
812 def _si : VOP1<op.SI, outs, ins, asm, []>,
813 SIMCInstr <opName#"_e32", SISubtarget.SI>;
814 def _vi : VOP1<op.VI, outs, ins, asm, []>,
815 SIMCInstr <opName#"_e32", SISubtarget.VI>;
818 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
819 VOP2Common <outs, ins, "", pattern>,
821 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
825 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
826 string opName, string revOpSI, string revOpVI> {
827 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
828 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
830 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
831 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
832 SIMCInstr <opName#"_e32", SISubtarget.SI>;
833 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
834 VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
835 SIMCInstr <opName#"_e32", SISubtarget.VI>;
838 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
840 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
841 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
842 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
843 bits<2> omod = !if(HasModifiers, ?, 0);
844 bits<1> clamp = !if(HasModifiers, ?, 0);
845 bits<9> src1 = !if(HasSrc1, ?, 0);
846 bits<9> src2 = !if(HasSrc2, ?, 0);
849 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
850 VOP3Common <outs, ins, "", pattern>,
852 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
856 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
857 VOP3Common <outs, ins, asm, []>,
859 SIMCInstr<opName#"_e64", SISubtarget.SI>;
861 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
862 VOP3Common <outs, ins, asm, []>,
864 SIMCInstr <opName#"_e64", SISubtarget.VI>;
866 // VI only instruction
867 class VOP3_vi <bits<10> op, string opName, dag outs, dag ins, string asm,
868 list<dag> pattern, int NumSrcArgs, bit HasMods = 1> :
869 VOP3Common <outs, ins, asm, pattern>,
872 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
873 !if(!eq(NumSrcArgs, 2), 0, 1),
876 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
877 string opName, int NumSrcArgs, bit HasMods = 1> {
879 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
881 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
882 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
883 !if(!eq(NumSrcArgs, 2), 0, 1),
885 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
886 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
887 !if(!eq(NumSrcArgs, 2), 0, 1),
891 // VOP3_m without source modifiers
892 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
893 string opName, int NumSrcArgs, bit HasMods = 1> {
895 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
897 let src0_modifiers = 0,
899 src2_modifiers = 0 in {
900 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
901 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
905 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
906 list<dag> pattern, string opName, bit HasMods = 1> {
908 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
910 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
911 VOP3DisableFields<0, 0, HasMods>;
913 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
914 VOP3DisableFields<0, 0, HasMods>;
917 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
918 list<dag> pattern, string opName, string revOpSI, string revOpVI,
919 bit HasMods = 1, bit UseFullOp = 0> {
921 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
922 VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>;
924 def _si : VOP3_Real_si <op.SI3,
925 outs, ins, asm, opName>,
926 VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
927 VOP3DisableFields<1, 0, HasMods>;
929 def _vi : VOP3_Real_vi <op.VI3,
930 outs, ins, asm, opName>,
931 VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
932 VOP3DisableFields<1, 0, HasMods>;
935 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
936 list<dag> pattern, string opName, string revOp,
937 bit HasMods = 1, bit UseFullOp = 0> {
938 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
939 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
941 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
942 // can write it into any SGPR. We currently don't use the carry out,
943 // so for now hardcode it to VCC as well.
944 let sdst = SIOperand.VCC, Defs = [VCC] in {
945 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
946 VOP3DisableFields<1, 0, HasMods>,
947 SIMCInstr<opName#"_e64", SISubtarget.SI>,
948 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
950 // TODO: Do we need this VI variant here?
951 /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, pattern>,
952 VOP3DisableFields<1, 0, HasMods>,
953 SIMCInstr<opName#"_e64", SISubtarget.VI>,
954 VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
955 } // End sdst = SIOperand.VCC, Defs = [VCC]
958 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
959 list<dag> pattern, string opName,
960 bit HasMods, bit defExec> {
962 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
964 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
965 VOP3DisableFields<1, 0, HasMods> {
966 let Defs = !if(defExec, [EXEC], []);
969 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
970 VOP3DisableFields<1, 0, HasMods> {
971 let Defs = !if(defExec, [EXEC], []);
975 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
976 dag ins32, string asm32, list<dag> pat32,
977 dag ins64, string asm64, list<dag> pat64,
980 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
982 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
985 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
986 SDPatternOperator node = null_frag> : VOP1_Helper <
988 P.Ins32, P.Asm32, [],
991 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
992 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
993 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
997 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
998 SDPatternOperator node = null_frag> {
1000 def _e32 : VOP1 <op.SI, P.Outs, P.Ins32, opName#P.Asm32, []>,
1003 def _e64 : VOP3Common <P.Outs, P.Ins64, opName#P.Asm64,
1005 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1006 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1007 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])>,
1010 VOP3DisableFields<0, 0, P.HasModifiers>;
1013 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1014 dag ins32, string asm32, list<dag> pat32,
1015 dag ins64, string asm64, list<dag> pat64,
1016 string revOpSI, string revOpVI, bit HasMods> {
1017 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>;
1019 defm _e64 : VOP3_2_m <op,
1020 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods
1024 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1025 SDPatternOperator node = null_frag,
1026 string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper <
1028 P.Ins32, P.Asm32, [],
1032 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1033 i1:$clamp, i32:$omod)),
1034 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1035 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1036 revOpSI, revOpVI, P.HasModifiers
1039 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1040 dag ins32, string asm32, list<dag> pat32,
1041 dag ins64, string asm64, list<dag> pat64,
1042 string revOp, bit HasMods> {
1044 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>;
1046 defm _e64 : VOP3b_2_m <op,
1047 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1051 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1052 SDPatternOperator node = null_frag,
1053 string revOp = opName> : VOP2b_Helper <
1055 P.Ins32, P.Asm32, [],
1059 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1060 i1:$clamp, i32:$omod)),
1061 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1062 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1063 revOp, P.HasModifiers
1066 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1067 VOPCCommon <ins, "", pattern>,
1069 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1073 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1074 string opName, bit DefExec> {
1075 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1077 def _si : VOPC<op.SI, ins, asm, []>,
1078 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1079 let Defs = !if(DefExec, [EXEC], []);
1082 def _vi : VOPC<op.VI, ins, asm, []>,
1083 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1084 let Defs = !if(DefExec, [EXEC], []);
1088 multiclass VOPC_Helper <vopc op, string opName,
1089 dag ins32, string asm32, list<dag> pat32,
1090 dag out64, dag ins64, string asm64, list<dag> pat64,
1091 bit HasMods, bit DefExec> {
1092 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1094 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1095 opName, HasMods, DefExec>;
1098 multiclass VOPCInst <vopc op, string opName,
1099 VOPProfile P, PatLeaf cond = COND_NULL,
1100 bit DefExec = 0> : VOPC_Helper <
1102 P.Ins32, P.Asm32, [],
1103 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1106 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1107 i1:$clamp, i32:$omod)),
1108 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1110 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1111 P.HasModifiers, DefExec
1114 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1115 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1117 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1118 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1120 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1121 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1123 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1124 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1127 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1128 PatLeaf cond = COND_NULL>
1129 : VOPCInst <op, opName, P, cond, 1>;
1131 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1132 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1134 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1135 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1137 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1138 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1140 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1141 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1143 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1144 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1145 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1148 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1149 SDPatternOperator node = null_frag> : VOP3_Helper <
1150 op, opName, P.Outs, P.Ins64, P.Asm64,
1151 !if(!eq(P.NumSrcArgs, 3),
1154 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1155 i1:$clamp, i32:$omod)),
1156 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1157 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1158 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1160 !if(!eq(P.NumSrcArgs, 2),
1163 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1164 i1:$clamp, i32:$omod)),
1165 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1166 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1167 /* P.NumSrcArgs == 1 */,
1170 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1171 i1:$clamp, i32:$omod))))],
1172 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1173 P.NumSrcArgs, P.HasModifiers
1176 class VOP3InstVI <bits<10> op, string opName, VOPProfile P,
1177 SDPatternOperator node = null_frag> : VOP3_vi <
1178 op, opName#"_vi", P.Outs, P.Ins64, opName#P.Asm64,
1179 !if(!eq(P.NumSrcArgs, 3),
1182 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1183 i1:$clamp, i32:$omod)),
1184 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1185 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1186 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1188 !if(!eq(P.NumSrcArgs, 2),
1191 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1192 i1:$clamp, i32:$omod)),
1193 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1194 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1195 /* P.NumSrcArgs == 1 */,
1198 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1199 i1:$clamp, i32:$omod))))],
1200 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1201 P.NumSrcArgs, P.HasModifiers
1204 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterClass arc,
1205 string opName, list<dag> pattern> :
1207 op, (outs vrc:$vdst, SReg_64:$sdst),
1208 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1209 InputModsNoDefault:$src1_modifiers, arc:$src1,
1210 InputModsNoDefault:$src2_modifiers, arc:$src2,
1211 ClampMod:$clamp, omod:$omod),
1212 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1213 opName, opName, 1, 1
1216 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1217 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1219 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1220 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
1223 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1224 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1225 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1226 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1227 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1228 i32:$src1_modifiers, P.Src1VT:$src1,
1229 i32:$src2_modifiers, P.Src2VT:$src2,
1233 //===----------------------------------------------------------------------===//
1234 // Interpolation opcodes
1235 //===----------------------------------------------------------------------===//
1237 class VINTRP_Pseudo <string opName, dag outs, dag ins, string asm,
1238 list<dag> pattern> :
1239 VINTRPCommon <outs, ins, asm, pattern>,
1240 SIMCInstr<opName, SISubtarget.NONE> {
1244 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1245 string asm, list<dag> pattern> :
1246 VINTRPCommon <outs, ins, asm, pattern>,
1248 SIMCInstr<opName, SISubtarget.SI>;
1250 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1251 string asm, list<dag> pattern> :
1252 VINTRPCommon <outs, ins, asm, pattern>,
1254 SIMCInstr<opName, SISubtarget.VI>;
1256 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1257 string disableEncoding = "", string constraints = "",
1258 list<dag> pattern = []> {
1259 let DisableEncoding = disableEncoding,
1260 Constraints = constraints in {
1261 def "" : VINTRP_Pseudo <opName, outs, ins, asm, pattern>;
1263 def _si : VINTRP_Real_si <op, opName, outs, ins, asm, pattern>;
1265 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm, pattern>;
1269 //===----------------------------------------------------------------------===//
1270 // Vector I/O classes
1271 //===----------------------------------------------------------------------===//
1273 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1274 DS <outs, ins, "", pattern>,
1275 SIMCInstr <opName, SISubtarget.NONE> {
1279 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1280 DS <outs, ins, asm, []>,
1282 SIMCInstr <opName, SISubtarget.SI>;
1284 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1285 DS <outs, ins, asm, []>,
1287 SIMCInstr <opName, SISubtarget.VI>;
1289 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1290 DS <outs, ins, asm, []>,
1292 SIMCInstr <opName, SISubtarget.SI> {
1294 // Single load interpret the 2 i8imm operands as a single i16 offset.
1296 let offset0 = offset{7-0};
1297 let offset1 = offset{15-8};
1300 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1301 DS <outs, ins, asm, []>,
1303 SIMCInstr <opName, SISubtarget.VI> {
1305 // Single load interpret the 2 i8imm operands as a single i16 offset.
1307 let offset0 = offset{7-0};
1308 let offset1 = offset{15-8};
1311 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1313 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1314 def "" : DS_Pseudo <opName, outs, ins, pat>;
1316 let data0 = 0, data1 = 0 in {
1317 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1318 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1323 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1327 (outs regClass:$vdst),
1328 (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset, M0Reg:$m0),
1329 asm#" $vdst, $addr"#"$offset"#" [M0]",
1332 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1334 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1335 def "" : DS_Pseudo <opName, outs, ins, pat>;
1337 let data0 = 0, data1 = 0 in {
1338 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1339 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1344 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1348 (outs regClass:$vdst),
1349 (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1351 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1354 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1355 string asm, list<dag> pat> {
1356 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1357 def "" : DS_Pseudo <opName, outs, ins, pat>;
1359 let data1 = 0, vdst = 0 in {
1360 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1361 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1366 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1371 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1372 asm#" $addr, $data0"#"$offset"#" [M0]",
1375 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1376 string asm, list<dag> pat> {
1377 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1378 def "" : DS_Pseudo <opName, outs, ins, pat>;
1381 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1382 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1387 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1392 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
1393 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1394 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1397 class DS_1A_si <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
1398 DS_si <op, outs, ins, asm, pat> {
1401 // Single load interpret the 2 i8imm operands as a single i16 offset.
1402 let offset0 = offset{7-0};
1403 let offset1 = offset{15-8};
1405 let hasSideEffects = 0;
1408 // 1 address, 1 data.
1409 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1412 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1413 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
1414 AtomicNoRet<noRetOp, 1> {
1420 let hasPostISelHook = 1; // Adjusted to no return version.
1423 // 1 address, 2 data.
1424 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1427 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1428 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1430 AtomicNoRet<noRetOp, 1> {
1433 let hasPostISelHook = 1; // Adjusted to no return version.
1436 // 1 address, 2 data.
1437 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1440 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1441 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1443 AtomicNoRet<noRetOp, 0> {
1448 // 1 address, 1 data.
1449 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1452 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1453 asm#" $addr, $data0"#"$offset"#" [M0]",
1455 AtomicNoRet<noRetOp, 0> {
1462 //===----------------------------------------------------------------------===//
1464 //===----------------------------------------------------------------------===//
1466 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1467 MTBUF <outs, ins, "", pattern>,
1468 SIMCInstr<opName, SISubtarget.NONE> {
1472 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1474 MTBUF <outs, ins, asm, []>,
1476 SIMCInstr<opName, SISubtarget.SI>;
1478 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1479 MTBUF <outs, ins, asm, []>,
1481 SIMCInstr <opName, SISubtarget.VI>;
1483 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1484 list<dag> pattern> {
1486 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1488 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1490 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1494 let mayStore = 1, mayLoad = 0 in {
1496 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1497 RegisterClass regClass> : MTBUF_m <
1499 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1500 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1501 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1502 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1503 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1506 } // mayStore = 1, mayLoad = 0
1508 let mayLoad = 1, mayStore = 0 in {
1510 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1511 RegisterClass regClass> : MTBUF_m <
1512 op, opName, (outs regClass:$dst),
1513 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1514 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1515 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1516 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1517 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1520 } // mayLoad = 1, mayStore = 0
1522 //===----------------------------------------------------------------------===//
1524 //===----------------------------------------------------------------------===//
1526 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1527 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1531 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1532 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
1536 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1538 bit IsAddr64 = is_addr64;
1539 string OpName = NAME # suffix;
1542 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1543 : MUBUF_si <op, outs, ins, asm, pattern> {
1553 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1554 : MUBUF_si <op, outs, ins, asm, pattern> {
1564 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1565 ValueType vt, SDPatternOperator atomic> {
1567 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1569 // No return variants
1572 def _ADDR64 : MUBUFAtomicAddr64 <
1574 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1575 mbuf_offset:$offset, slc:$slc),
1576 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1577 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1579 def _OFFSET : MUBUFAtomicOffset <
1581 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1582 SCSrc_32:$soffset, slc:$slc),
1583 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1584 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1587 // Variant that return values
1588 let glc = 1, Constraints = "$vdata = $vdata_in",
1589 DisableEncoding = "$vdata_in" in {
1591 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1592 op, (outs rc:$vdata),
1593 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1594 mbuf_offset:$offset, slc:$slc),
1595 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1597 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1598 i1:$slc), vt:$vdata_in))]
1599 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1601 def _RTN_OFFSET : MUBUFAtomicOffset <
1602 op, (outs rc:$vdata),
1603 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1604 SCSrc_32:$soffset, slc:$slc),
1605 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1607 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1608 i1:$slc), vt:$vdata_in))]
1609 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1613 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1616 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1617 ValueType load_vt = i32,
1618 SDPatternOperator ld = null_frag> {
1620 let mayLoad = 1, mayStore = 0 in {
1624 let offen = 0, idxen = 0, vaddr = 0 in {
1625 def _OFFSET : MUBUF_si <op, (outs regClass:$vdata),
1626 (ins SReg_128:$srsrc,
1627 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1628 slc:$slc, tfe:$tfe),
1629 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1630 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1631 i32:$soffset, i16:$offset,
1632 i1:$glc, i1:$slc, i1:$tfe)))]>,
1633 MUBUFAddr64Table<0>;
1636 let offen = 1, idxen = 0 in {
1637 def _OFFEN : MUBUF_si <op, (outs regClass:$vdata),
1638 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1639 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1641 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1644 let offen = 0, idxen = 1 in {
1645 def _IDXEN : MUBUF_si <op, (outs regClass:$vdata),
1646 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1647 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1648 slc:$slc, tfe:$tfe),
1649 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1652 let offen = 1, idxen = 1 in {
1653 def _BOTHEN : MUBUF_si <op, (outs regClass:$vdata),
1654 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1655 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1656 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1660 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1661 def _ADDR64 : MUBUF_si <op, (outs regClass:$vdata),
1662 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1663 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1664 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1665 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1670 multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
1671 ValueType load_vt = i32,
1672 SDPatternOperator ld = null_frag> {
1674 let lds = 0, mayLoad = 1 in {
1675 let offen = 0, idxen = 0, vaddr = 0 in {
1676 def _OFFSET : MUBUF_vi <op, (outs regClass:$vdata),
1677 (ins SReg_128:$srsrc,
1678 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1679 slc:$slc, tfe:$tfe),
1680 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1681 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1682 i32:$soffset, i16:$offset,
1683 i1:$glc, i1:$slc, i1:$tfe)))]>,
1684 MUBUFAddr64Table<0>;
1687 let offen = 1, idxen = 0 in {
1688 def _OFFEN : MUBUF_vi <op, (outs regClass:$vdata),
1689 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1690 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1692 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1695 let offen = 0, idxen = 1 in {
1696 def _IDXEN : MUBUF_vi <op, (outs regClass:$vdata),
1697 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1698 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1699 slc:$slc, tfe:$tfe),
1700 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1703 let offen = 1, idxen = 1 in {
1704 def _BOTHEN : MUBUF_vi <op, (outs regClass:$vdata),
1705 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1706 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1707 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1712 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1713 ValueType store_vt, SDPatternOperator st> {
1719 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SCSrc_32:$soffset,
1720 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1722 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1723 "$glc"#"$slc"#"$tfe",
1727 let offen = 0, idxen = 0, vaddr = 0 in {
1728 def _OFFSET : MUBUF_si <
1730 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1731 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1732 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1733 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1734 i16:$offset, i1:$glc, i1:$slc,
1736 >, MUBUFAddr64Table<0>;
1737 } // offen = 0, idxen = 0, vaddr = 0
1739 let offen = 1, idxen = 0 in {
1740 def _OFFEN : MUBUF_si <
1742 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SCSrc_32:$soffset,
1743 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1744 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1745 "$glc"#"$slc"#"$tfe",
1748 } // end offen = 1, idxen = 0
1752 def _ADDR64 : MUBUF_si <
1754 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1755 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1756 [(st store_vt:$vdata,
1757 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1770 let soffset = 128; // ZERO
1774 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1775 FLAT <op, (outs regClass:$data),
1776 (ins VReg_64:$addr),
1777 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1784 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1785 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1786 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1798 class MIMG_Mask <string op, int channels> {
1800 int Channels = channels;
1803 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1804 RegisterClass dst_rc,
1805 RegisterClass src_rc> : MIMG <
1807 (outs dst_rc:$vdata),
1808 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1809 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1811 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1812 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1817 let hasPostISelHook = 1;
1820 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1821 RegisterClass dst_rc,
1823 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1824 MIMG_Mask<asm#"_V1", channels>;
1825 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1826 MIMG_Mask<asm#"_V2", channels>;
1827 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1828 MIMG_Mask<asm#"_V4", channels>;
1831 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1832 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1833 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1834 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1835 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1838 class MIMG_Sampler_Helper <bits<7> op, string asm,
1839 RegisterClass dst_rc,
1840 RegisterClass src_rc> : MIMG <
1842 (outs dst_rc:$vdata),
1843 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1844 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1845 SReg_256:$srsrc, SReg_128:$ssamp),
1846 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1847 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1851 let hasPostISelHook = 1;
1854 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1855 RegisterClass dst_rc,
1857 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1858 MIMG_Mask<asm#"_V1", channels>;
1859 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1860 MIMG_Mask<asm#"_V2", channels>;
1861 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1862 MIMG_Mask<asm#"_V4", channels>;
1863 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1864 MIMG_Mask<asm#"_V8", channels>;
1865 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1866 MIMG_Mask<asm#"_V16", channels>;
1869 multiclass MIMG_Sampler <bits<7> op, string asm> {
1870 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1871 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1872 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1873 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1876 class MIMG_Gather_Helper <bits<7> op, string asm,
1877 RegisterClass dst_rc,
1878 RegisterClass src_rc> : MIMG <
1880 (outs dst_rc:$vdata),
1881 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1882 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1883 SReg_256:$srsrc, SReg_128:$ssamp),
1884 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1885 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1890 // DMASK was repurposed for GATHER4. 4 components are always
1891 // returned and DMASK works like a swizzle - it selects
1892 // the component to fetch. The only useful DMASK values are
1893 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1894 // (red,red,red,red) etc.) The ISA document doesn't mention
1896 // Therefore, disable all code which updates DMASK by setting these two:
1898 let hasPostISelHook = 0;
1901 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1902 RegisterClass dst_rc,
1904 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1905 MIMG_Mask<asm#"_V1", channels>;
1906 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1907 MIMG_Mask<asm#"_V2", channels>;
1908 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1909 MIMG_Mask<asm#"_V4", channels>;
1910 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1911 MIMG_Mask<asm#"_V8", channels>;
1912 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1913 MIMG_Mask<asm#"_V16", channels>;
1916 multiclass MIMG_Gather <bits<7> op, string asm> {
1917 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1918 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1919 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1920 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1923 //===----------------------------------------------------------------------===//
1924 // Vector instruction mappings
1925 //===----------------------------------------------------------------------===//
1927 // Maps an opcode in e32 form to its e64 equivalent
1928 def getVOPe64 : InstrMapping {
1929 let FilterClass = "VOP";
1930 let RowFields = ["OpName"];
1931 let ColFields = ["Size"];
1933 let ValueCols = [["8"]];
1936 // Maps an opcode in e64 form to its e32 equivalent
1937 def getVOPe32 : InstrMapping {
1938 let FilterClass = "VOP";
1939 let RowFields = ["OpName"];
1940 let ColFields = ["Size"];
1942 let ValueCols = [["4"]];
1945 // Maps an original opcode to its commuted version
1946 def getCommuteRev : InstrMapping {
1947 let FilterClass = "VOP2_REV";
1948 let RowFields = ["RevOp"];
1949 let ColFields = ["IsOrig"];
1951 let ValueCols = [["0"]];
1954 def getMaskedMIMGOp : InstrMapping {
1955 let FilterClass = "MIMG_Mask";
1956 let RowFields = ["Op"];
1957 let ColFields = ["Channels"];
1959 let ValueCols = [["1"], ["2"], ["3"] ];
1962 // Maps an commuted opcode to its original version
1963 def getCommuteOrig : InstrMapping {
1964 let FilterClass = "VOP2_REV";
1965 let RowFields = ["RevOp"];
1966 let ColFields = ["IsOrig"];
1968 let ValueCols = [["1"]];
1971 def getMCOpcodeGen : InstrMapping {
1972 let FilterClass = "SIMCInstr";
1973 let RowFields = ["PseudoInstr"];
1974 let ColFields = ["Subtarget"];
1975 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1976 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
1979 def getAddr64Inst : InstrMapping {
1980 let FilterClass = "MUBUFAddr64Table";
1981 let RowFields = ["OpName"];
1982 let ColFields = ["IsAddr64"];
1984 let ValueCols = [["1"]];
1987 // Maps an atomic opcode to its version with a return value.
1988 def getAtomicRetOp : InstrMapping {
1989 let FilterClass = "AtomicNoRet";
1990 let RowFields = ["NoRetOp"];
1991 let ColFields = ["IsRet"];
1993 let ValueCols = [["1"]];
1996 // Maps an atomic opcode to its returnless version.
1997 def getAtomicNoRetOp : InstrMapping {
1998 let FilterClass = "AtomicNoRet";
1999 let RowFields = ["NoRetOp"];
2000 let ColFields = ["IsRet"];
2002 let ValueCols = [["0"]];
2005 include "SIInstructions.td"
2006 include "CIInstructions.td"
2007 include "VIInstructions.td"