1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
14 class vopc <bits<8> si> : vop {
15 field bits<8> SI = si;
17 field bits<9> SI3 = {0, si{7-0}};
20 class vop1 <bits<8> si> : vop {
21 field bits<8> SI = si;
23 field bits<9> SI3 = {1, 1, si{6-0}};
26 class vop2 <bits<6> si> : vop {
27 field bits<6> SI = si;
29 field bits<9> SI3 = {1, 0, 0, si{5-0}};
32 class vop3 <bits<9> si> : vop {
33 field bits<9> SI3 = si;
36 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
37 // in AMDGPUMCInstLower.h
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
47 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
48 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
49 [SDNPMayLoad, SDNPMemOperand]
52 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
54 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
55 SDTCisVT<1, iAny>, // vdata(VGPR)
56 SDTCisVT<2, i32>, // num_channels(imm)
57 SDTCisVT<3, i32>, // vaddr(VGPR)
58 SDTCisVT<4, i32>, // soffset(SGPR)
59 SDTCisVT<5, i32>, // inst_offset(imm)
60 SDTCisVT<6, i32>, // dfmt(imm)
61 SDTCisVT<7, i32>, // nfmt(imm)
62 SDTCisVT<8, i32>, // offen(imm)
63 SDTCisVT<9, i32>, // idxen(imm)
64 SDTCisVT<10, i32>, // glc(imm)
65 SDTCisVT<11, i32>, // slc(imm)
66 SDTCisVT<12, i32> // tfe(imm)
68 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
71 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
72 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
76 class SDSample<string opcode> : SDNode <opcode,
77 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
78 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
81 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
82 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
83 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
84 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
86 def SIconstdata_ptr : SDNode<
87 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
90 // Transformation function, extract the lower 32bit of a 64bit immediate
91 def LO32 : SDNodeXForm<imm, [{
92 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
95 def LO32f : SDNodeXForm<fpimm, [{
96 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
97 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
100 // Transformation function, extract the upper 32bit of a 64bit immediate
101 def HI32 : SDNodeXForm<imm, [{
102 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
105 def HI32f : SDNodeXForm<fpimm, [{
106 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
107 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
110 def IMM8bitDWORD : PatLeaf <(imm),
111 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
114 def as_dword_i32imm : SDNodeXForm<imm, [{
115 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
118 def as_i1imm : SDNodeXForm<imm, [{
119 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
122 def as_i8imm : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
126 def as_i16imm : SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
130 def as_i32imm: SDNodeXForm<imm, [{
131 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
134 def IMM8bit : PatLeaf <(imm),
135 [{return isUInt<8>(N->getZExtValue());}]
138 def IMM12bit : PatLeaf <(imm),
139 [{return isUInt<12>(N->getZExtValue());}]
142 def IMM16bit : PatLeaf <(imm),
143 [{return isUInt<16>(N->getZExtValue());}]
146 def IMM32bit : PatLeaf <(imm),
147 [{return isUInt<32>(N->getZExtValue());}]
150 def mubuf_vaddr_offset : PatFrag<
151 (ops node:$ptr, node:$offset, node:$imm_offset),
152 (add (add node:$ptr, node:$offset), node:$imm_offset)
155 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
156 return isInlineImmediate(N);
159 class SGPRImm <dag frag> : PatLeaf<frag, [{
160 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
161 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
164 const SIRegisterInfo *SIRI =
165 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
166 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
168 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
175 //===----------------------------------------------------------------------===//
177 //===----------------------------------------------------------------------===//
179 def FRAMEri32 : Operand<iPTR> {
180 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
183 def sopp_brtarget : Operand<OtherVT> {
184 let EncoderMethod = "getSOPPBrEncoding";
185 let OperandType = "OPERAND_PCREL";
188 include "SIInstrFormats.td"
190 let OperandType = "OPERAND_IMMEDIATE" in {
192 def offen : Operand<i1> {
193 let PrintMethod = "printOffen";
195 def idxen : Operand<i1> {
196 let PrintMethod = "printIdxen";
198 def addr64 : Operand<i1> {
199 let PrintMethod = "printAddr64";
201 def mbuf_offset : Operand<i16> {
202 let PrintMethod = "printMBUFOffset";
204 def ds_offset : Operand<i16> {
205 let PrintMethod = "printDSOffset";
207 def ds_offset0 : Operand<i8> {
208 let PrintMethod = "printDSOffset0";
210 def ds_offset1 : Operand<i8> {
211 let PrintMethod = "printDSOffset1";
213 def glc : Operand <i1> {
214 let PrintMethod = "printGLC";
216 def slc : Operand <i1> {
217 let PrintMethod = "printSLC";
219 def tfe : Operand <i1> {
220 let PrintMethod = "printTFE";
223 def omod : Operand <i32> {
224 let PrintMethod = "printOModSI";
227 def ClampMod : Operand <i1> {
228 let PrintMethod = "printClampSI";
231 } // End OperandType = "OPERAND_IMMEDIATE"
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
237 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
238 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
240 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
241 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
242 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
243 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
244 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
245 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
247 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
248 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
249 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
251 //===----------------------------------------------------------------------===//
252 // SI assembler operands
253 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
275 // SI Instruction multiclass helpers.
277 // Instructions with _32 take 32-bit operands.
278 // Instructions with _64 take 64-bit operands.
280 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
281 // encoding is the standard encoding, but instruction that make use of
282 // any of the instruction modifiers must use the 64-bit encoding.
284 // Instructions with _e32 use the 32-bit encoding.
285 // Instructions with _e64 use the 64-bit encoding.
287 //===----------------------------------------------------------------------===//
289 class SIMCInstr <string pseudo, int subtarget> {
290 string PseudoInstr = pseudo;
291 int Subtarget = subtarget;
294 //===----------------------------------------------------------------------===//
296 //===----------------------------------------------------------------------===//
298 class EXPCommon : InstSI<
300 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
301 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
302 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
311 let isPseudo = 1 in {
312 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
315 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
322 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
323 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
324 opName#" $dst, $src0", pattern
327 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
328 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
329 opName#" $dst, $src0", pattern
332 // 64-bit input, 32-bit output.
333 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
334 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
335 opName#" $dst, $src0", pattern
338 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
339 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
340 opName#" $dst, $src0, $src1", pattern
343 class SOP2_SELECT_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
344 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
345 opName#" $dst, $src0, $src1 [$scc]", pattern
348 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
349 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
350 opName#" $dst, $src0, $src1", pattern
353 class SOP2_64_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
354 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
355 opName#" $dst, $src0, $src1", pattern
358 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
359 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
360 opName#" $dst, $src0, $src1", pattern
364 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
365 string opName, PatLeaf cond> : SOPC <
366 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
367 opName#" $dst, $src0, $src1", []>;
369 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
370 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
372 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
373 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
375 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
376 op, (outs SReg_32:$dst), (ins u16imm:$src0),
377 opName#" $dst, $src0", pattern
380 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
381 op, (outs SReg_64:$dst), (ins u16imm:$src0),
382 opName#" $dst, $src0", pattern
385 //===----------------------------------------------------------------------===//
387 //===----------------------------------------------------------------------===//
389 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
390 SMRD <outs, ins, "", pattern>,
391 SIMCInstr<opName, SISubtarget.NONE> {
395 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
397 SMRD <outs, ins, asm, []>,
399 SIMCInstr<opName, SISubtarget.SI>;
401 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
402 string asm, list<dag> pattern> {
404 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
406 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
410 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
411 RegisterClass dstClass> {
413 op, opName#"_IMM", 1, (outs dstClass:$dst),
414 (ins baseClass:$sbase, u32imm:$offset),
415 opName#" $dst, $sbase, $offset", []
418 defm _SGPR : SMRD_m <
419 op, opName#"_SGPR", 0, (outs dstClass:$dst),
420 (ins baseClass:$sbase, SReg_32:$soff),
421 opName#" $dst, $sbase, $soff", []
425 //===----------------------------------------------------------------------===//
426 // Vector ALU classes
427 //===----------------------------------------------------------------------===//
429 // This must always be right before the operand being input modified.
430 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
431 let PrintMethod = "printOperandAndMods";
433 def InputModsNoDefault : Operand <i32> {
434 let PrintMethod = "printOperandAndMods";
437 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
439 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
440 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
444 // Returns the register class to use for the destination of VOP[123C]
445 // instructions for the given VT.
446 class getVALUDstForVT<ValueType VT> {
447 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
450 // Returns the register class to use for source 0 of VOP[12C]
451 // instructions for the given VT.
452 class getVOPSrc0ForVT<ValueType VT> {
453 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
456 // Returns the register class to use for source 1 of VOP[12C] for the
458 class getVOPSrc1ForVT<ValueType VT> {
459 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
462 // Returns the register classes for the source arguments of a VOP[12C]
463 // instruction for the given SrcVTs.
464 class getInRC32 <list<ValueType> SrcVT> {
465 list<RegisterClass> ret = [
466 getVOPSrc0ForVT<SrcVT[0]>.ret,
467 getVOPSrc1ForVT<SrcVT[1]>.ret
471 // Returns the register class to use for sources of VOP3 instructions for the
473 class getVOP3SrcForVT<ValueType VT> {
474 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
477 // Returns the register classes for the source arguments of a VOP3
478 // instruction for the given SrcVTs.
479 class getInRC64 <list<ValueType> SrcVT> {
480 list<RegisterClass> ret = [
481 getVOP3SrcForVT<SrcVT[0]>.ret,
482 getVOP3SrcForVT<SrcVT[1]>.ret,
483 getVOP3SrcForVT<SrcVT[2]>.ret
487 // Returns 1 if the source arguments have modifiers, 0 if they do not.
488 class hasModifiers<ValueType SrcVT> {
489 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
490 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
493 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
494 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
495 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
496 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
500 // Returns the input arguments for VOP3 instructions for the given SrcVT.
501 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
502 RegisterClass Src2RC, int NumSrcArgs,
506 !if (!eq(NumSrcArgs, 1),
507 !if (!eq(HasModifiers, 1),
508 // VOP1 with modifiers
509 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
510 ClampMod:$clamp, omod:$omod)
512 // VOP1 without modifiers
515 !if (!eq(NumSrcArgs, 2),
516 !if (!eq(HasModifiers, 1),
517 // VOP 2 with modifiers
518 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
519 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
520 ClampMod:$clamp, omod:$omod)
522 // VOP2 without modifiers
523 (ins Src0RC:$src0, Src1RC:$src1)
525 /* NumSrcArgs == 3 */,
526 !if (!eq(HasModifiers, 1),
527 // VOP3 with modifiers
528 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
529 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
530 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
531 ClampMod:$clamp, omod:$omod)
533 // VOP3 without modifiers
534 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
538 // Returns the assembly string for the inputs and outputs of a VOP[12C]
539 // instruction. This does not add the _e32 suffix, so it can be reused
541 class getAsm32 <int NumSrcArgs> {
542 string src1 = ", $src1";
543 string src2 = ", $src2";
544 string ret = " $dst, $src0"#
545 !if(!eq(NumSrcArgs, 1), "", src1)#
546 !if(!eq(NumSrcArgs, 3), src2, "");
549 // Returns the assembly string for the inputs and outputs of a VOP3
551 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
552 string src0 = "$src0_modifiers,";
553 string src1 = !if(!eq(NumSrcArgs, 1), "",
554 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
555 " $src1_modifiers,"));
556 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
558 !if(!eq(HasModifiers, 0),
559 getAsm32<NumSrcArgs>.ret,
560 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
564 class VOPProfile <list<ValueType> _ArgVT> {
566 field list<ValueType> ArgVT = _ArgVT;
568 field ValueType DstVT = ArgVT[0];
569 field ValueType Src0VT = ArgVT[1];
570 field ValueType Src1VT = ArgVT[2];
571 field ValueType Src2VT = ArgVT[3];
572 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
573 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
574 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
575 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
576 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
577 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
579 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
580 field bit HasModifiers = hasModifiers<Src0VT>.ret;
582 field dag Outs = (outs DstRC:$dst);
584 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
585 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
588 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
589 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
592 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
593 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
594 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
595 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
596 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
597 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
598 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
599 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
600 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
602 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
603 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
604 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
605 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
606 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
607 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
608 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
609 let Src0RC32 = VCSrc_32;
611 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
612 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
614 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
615 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
616 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
617 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
620 class VOP <string opName> {
621 string OpName = opName;
624 class VOP2_REV <string revOp, bit isOrig> {
625 string RevOp = revOp;
629 class AtomicNoRet <string noRetOp, bit isRet> {
630 string NoRetOp = noRetOp;
634 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
635 VOP1Common <outs, ins, "", pattern>,
636 SIMCInstr<opName, SISubtarget.NONE> {
640 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
642 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
644 def _si : VOP1<op.SI, outs, ins, asm, []>,
645 SIMCInstr <opName, SISubtarget.SI>;
648 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
650 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
651 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
652 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
653 bits<2> omod = !if(HasModifiers, ?, 0);
654 bits<1> clamp = !if(HasModifiers, ?, 0);
655 bits<9> src1 = !if(HasSrc1, ?, 0);
656 bits<9> src2 = !if(HasSrc2, ?, 0);
659 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
660 VOP3Common <outs, ins, "", pattern>,
662 SIMCInstr<opName, SISubtarget.NONE> {
666 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
667 VOP3 <op, outs, ins, asm, []>,
668 SIMCInstr<opName, SISubtarget.SI>;
670 multiclass VOP3_m <vop3 op, dag outs, dag ins, string asm, list<dag> pattern,
671 string opName, int NumSrcArgs, bit HasMods = 1> {
673 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
675 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
676 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
677 !if(!eq(NumSrcArgs, 2), 0, 1),
682 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
683 list<dag> pattern, string opName, bit HasMods = 1> {
685 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
687 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
688 VOP3DisableFields<0, 0, HasMods>;
691 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
692 list<dag> pattern, string opName, string revOp,
693 bit HasMods = 1, bit UseFullOp = 0> {
695 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
696 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
698 def _si : VOP3_Real_si <op.SI3,
699 outs, ins, asm, opName>,
700 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
701 VOP3DisableFields<1, 0, HasMods>;
704 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
705 list<dag> pattern, string opName, string revOp,
706 bit HasMods = 1, bit UseFullOp = 0> {
707 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
708 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
710 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
711 // can write it into any SGPR. We currently don't use the carry out,
712 // so for now hardcode it to VCC as well.
713 let sdst = SIOperand.VCC, Defs = [VCC] in {
714 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
715 VOP3DisableFields<1, 0, HasMods>,
716 SIMCInstr<opName, SISubtarget.SI>,
717 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
718 } // End sdst = SIOperand.VCC, Defs = [VCC]
721 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
722 list<dag> pattern, string opName,
723 bit HasMods, bit defExec> {
725 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
727 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
728 VOP3DisableFields<1, 0, HasMods> {
729 let Defs = !if(defExec, [EXEC], []);
733 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
734 dag ins32, string asm32, list<dag> pat32,
735 dag ins64, string asm64, list<dag> pat64,
738 def _e32 : VOP1 <op.SI, outs, ins32, opName#asm32, pat32>, VOP<opName>;
740 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
743 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
744 SDPatternOperator node = null_frag> : VOP1_Helper <
746 P.Ins32, P.Asm32, [],
749 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
750 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
751 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
755 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
756 list<dag> pattern, string revOp> :
757 VOP2 <op, outs, ins, opName#asm, pattern>,
759 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
761 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
762 dag ins32, string asm32, list<dag> pat32,
763 dag ins64, string asm64, list<dag> pat64,
764 string revOp, bit HasMods> {
765 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
767 defm _e64 : VOP3_2_m <op,
768 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
772 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
773 SDPatternOperator node = null_frag,
774 string revOp = opName> : VOP2_Helper <
776 P.Ins32, P.Asm32, [],
780 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
781 i1:$clamp, i32:$omod)),
782 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
783 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
784 revOp, P.HasModifiers
787 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
788 dag ins32, string asm32, list<dag> pat32,
789 dag ins64, string asm64, list<dag> pat64,
790 string revOp, bit HasMods> {
792 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
794 defm _e64 : VOP3b_2_m <op,
795 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
799 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
800 SDPatternOperator node = null_frag,
801 string revOp = opName> : VOP2b_Helper <
803 P.Ins32, P.Asm32, [],
807 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
808 i1:$clamp, i32:$omod)),
809 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
810 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
811 revOp, P.HasModifiers
814 multiclass VOPC_Helper <vopc op, string opName,
815 dag ins32, string asm32, list<dag> pat32,
816 dag out64, dag ins64, string asm64, list<dag> pat64,
817 bit HasMods, bit DefExec> {
818 def _e32 : VOPC <op.SI, ins32, opName#asm32, pat32>, VOP <opName> {
819 let Defs = !if(DefExec, [EXEC], []);
822 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
826 multiclass VOPCInst <vopc op, string opName,
827 VOPProfile P, PatLeaf cond = COND_NULL,
828 bit DefExec = 0> : VOPC_Helper <
830 P.Ins32, P.Asm32, [],
831 (outs SReg_64:$dst), P.Ins64, P.Asm64,
834 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
835 i1:$clamp, i32:$omod)),
836 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
838 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
839 P.HasModifiers, DefExec
842 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
843 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
845 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
846 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
848 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
849 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
851 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
852 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
855 multiclass VOPCX <vopc op, string opName, VOPProfile P,
856 PatLeaf cond = COND_NULL>
857 : VOPCInst <op, opName, P, cond, 1>;
859 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
860 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
862 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
863 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
865 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
866 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
868 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
869 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
871 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
872 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
873 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
876 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
877 SDPatternOperator node = null_frag> : VOP3_Helper <
878 op, opName, P.Outs, P.Ins64, P.Asm64,
879 !if(!eq(P.NumSrcArgs, 3),
882 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
883 i1:$clamp, i32:$omod)),
884 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
885 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
886 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
888 !if(!eq(P.NumSrcArgs, 2),
891 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
892 i1:$clamp, i32:$omod)),
893 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
894 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
895 /* P.NumSrcArgs == 1 */,
898 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
899 i1:$clamp, i32:$omod))))],
900 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
901 P.NumSrcArgs, P.HasModifiers
904 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterClass arc,
905 string opName, list<dag> pattern> :
907 op, (outs vrc:$vdst, SReg_64:$sdst),
908 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
909 InputModsNoDefault:$src1_modifiers, arc:$src1,
910 InputModsNoDefault:$src2_modifiers, arc:$src2,
911 ClampMod:$clamp, omod:$omod),
912 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
916 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
917 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
919 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
920 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
923 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
924 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
925 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
926 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
927 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
928 i32:$src1_modifiers, P.Src1VT:$src1,
929 i32:$src2_modifiers, P.Src2VT:$src2,
933 //===----------------------------------------------------------------------===//
934 // Vector I/O classes
935 //===----------------------------------------------------------------------===//
937 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
938 DS <op, outs, ins, asm, pat> {
941 // Single load interpret the 2 i8imm operands as a single i16 offset.
942 let offset0 = offset{7-0};
943 let offset1 = offset{15-8};
946 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
948 (outs regClass:$vdst),
949 (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset),
950 asm#" $vdst, $addr"#"$offset"#" [M0]",
958 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
960 (outs regClass:$vdst),
961 (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1),
962 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
970 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
973 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset),
974 asm#" $addr, $data0"#"$offset"#" [M0]",
982 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
985 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
986 ds_offset0:$offset0, ds_offset1:$offset1),
987 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
994 // 1 address, 1 data.
995 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
998 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),
999 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
1000 AtomicNoRet<noRetOp, 1> {
1006 let hasPostISelHook = 1; // Adjusted to no return version.
1009 // 1 address, 2 data.
1010 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
1013 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),
1014 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1016 AtomicNoRet<noRetOp, 1> {
1020 let hasPostISelHook = 1; // Adjusted to no return version.
1023 // 1 address, 2 data.
1024 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1027 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),
1028 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1030 AtomicNoRet<noRetOp, 0> {
1035 // 1 address, 1 data.
1036 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1039 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),
1040 asm#" $addr, $data0"#"$offset"#" [M0]",
1042 AtomicNoRet<noRetOp, 0> {
1049 //===----------------------------------------------------------------------===//
1051 //===----------------------------------------------------------------------===//
1053 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1054 MTBUF <outs, ins, "", pattern>,
1055 SIMCInstr<opName, SISubtarget.NONE> {
1059 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1061 MTBUF <outs, ins, asm, []>,
1063 SIMCInstr<opName, SISubtarget.SI>;
1065 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1066 list<dag> pattern> {
1068 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1070 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1074 let mayStore = 1, mayLoad = 0 in {
1076 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1077 RegisterClass regClass> : MTBUF_m <
1079 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1080 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1081 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1082 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1083 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1086 } // mayStore = 1, mayLoad = 0
1088 let mayLoad = 1, mayStore = 0 in {
1090 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1091 RegisterClass regClass> : MTBUF_m <
1092 op, opName, (outs regClass:$dst),
1093 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1094 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1095 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1096 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1097 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1100 } // mayLoad = 1, mayStore = 0
1102 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1104 bit IsAddr64 = is_addr64;
1105 string OpName = NAME # suffix;
1108 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1109 : MUBUF <op, outs, ins, asm, pattern> {
1119 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1120 : MUBUF <op, outs, ins, asm, pattern> {
1130 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1131 ValueType vt, SDPatternOperator atomic> {
1133 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1135 // No return variants
1138 def _ADDR64 : MUBUFAtomicAddr64 <
1140 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1141 mbuf_offset:$offset, slc:$slc),
1142 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1143 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1145 def _OFFSET : MUBUFAtomicOffset <
1147 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1148 SSrc_32:$soffset, slc:$slc),
1149 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1150 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1153 // Variant that return values
1154 let glc = 1, Constraints = "$vdata = $vdata_in",
1155 DisableEncoding = "$vdata_in" in {
1157 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1158 op, (outs rc:$vdata),
1159 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1160 mbuf_offset:$offset, slc:$slc),
1161 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1163 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1164 i1:$slc), vt:$vdata_in))]
1165 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1167 def _RTN_OFFSET : MUBUFAtomicOffset <
1168 op, (outs rc:$vdata),
1169 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1170 SSrc_32:$soffset, slc:$slc),
1171 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1173 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1174 i1:$slc), vt:$vdata_in))]
1175 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1179 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1182 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1183 ValueType load_vt = i32,
1184 SDPatternOperator ld = null_frag> {
1186 let lds = 0, mayLoad = 1 in {
1190 let offen = 0, idxen = 0, vaddr = 0 in {
1191 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1192 (ins SReg_128:$srsrc,
1193 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1194 slc:$slc, tfe:$tfe),
1195 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1196 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1197 i32:$soffset, i16:$offset,
1198 i1:$glc, i1:$slc, i1:$tfe)))]>,
1199 MUBUFAddr64Table<0>;
1202 let offen = 1, idxen = 0 in {
1203 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1204 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1205 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1207 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1210 let offen = 0, idxen = 1 in {
1211 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1212 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1213 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1214 slc:$slc, tfe:$tfe),
1215 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1218 let offen = 1, idxen = 1 in {
1219 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1220 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1221 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1222 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1226 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1227 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1228 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1229 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1230 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1231 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1236 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1237 ValueType store_vt, SDPatternOperator st> {
1239 let addr64 = 0, lds = 0 in {
1243 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1244 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1246 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1247 "$glc"#"$slc"#"$tfe",
1251 let offen = 0, idxen = 0, vaddr = 0 in {
1252 def _OFFSET : MUBUF <
1254 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1255 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1256 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1257 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1258 i16:$offset, i1:$glc, i1:$slc,
1260 >, MUBUFAddr64Table<0>;
1261 } // offen = 0, idxen = 0, vaddr = 0
1263 let offen = 1, idxen = 0 in {
1264 def _OFFEN : MUBUF <
1266 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1267 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1268 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1269 "$glc"#"$slc"#"$tfe",
1272 } // end offen = 1, idxen = 0
1274 } // End addr64 = 0, lds = 0
1276 def _ADDR64 : MUBUF <
1278 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1279 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1280 [(st store_vt:$vdata,
1281 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1295 let soffset = 128; // ZERO
1299 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1300 FLAT <op, (outs regClass:$data),
1301 (ins VReg_64:$addr),
1302 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1309 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1310 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1311 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1323 class MIMG_Mask <string op, int channels> {
1325 int Channels = channels;
1328 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1329 RegisterClass dst_rc,
1330 RegisterClass src_rc> : MIMG <
1332 (outs dst_rc:$vdata),
1333 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1334 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1336 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1337 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1342 let hasPostISelHook = 1;
1345 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1346 RegisterClass dst_rc,
1348 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1349 MIMG_Mask<asm#"_V1", channels>;
1350 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1351 MIMG_Mask<asm#"_V2", channels>;
1352 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1353 MIMG_Mask<asm#"_V4", channels>;
1356 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1357 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1358 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1359 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1360 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1363 class MIMG_Sampler_Helper <bits<7> op, string asm,
1364 RegisterClass dst_rc,
1365 RegisterClass src_rc> : MIMG <
1367 (outs dst_rc:$vdata),
1368 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1369 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1370 SReg_256:$srsrc, SReg_128:$ssamp),
1371 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1372 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1376 let hasPostISelHook = 1;
1379 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1380 RegisterClass dst_rc,
1382 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1383 MIMG_Mask<asm#"_V1", channels>;
1384 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1385 MIMG_Mask<asm#"_V2", channels>;
1386 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1387 MIMG_Mask<asm#"_V4", channels>;
1388 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1389 MIMG_Mask<asm#"_V8", channels>;
1390 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1391 MIMG_Mask<asm#"_V16", channels>;
1394 multiclass MIMG_Sampler <bits<7> op, string asm> {
1395 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1396 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1397 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1398 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1401 class MIMG_Gather_Helper <bits<7> op, string asm,
1402 RegisterClass dst_rc,
1403 RegisterClass src_rc> : MIMG <
1405 (outs dst_rc:$vdata),
1406 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1407 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1408 SReg_256:$srsrc, SReg_128:$ssamp),
1409 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1410 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1415 // DMASK was repurposed for GATHER4. 4 components are always
1416 // returned and DMASK works like a swizzle - it selects
1417 // the component to fetch. The only useful DMASK values are
1418 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1419 // (red,red,red,red) etc.) The ISA document doesn't mention
1421 // Therefore, disable all code which updates DMASK by setting these two:
1423 let hasPostISelHook = 0;
1426 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1427 RegisterClass dst_rc,
1429 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1430 MIMG_Mask<asm#"_V1", channels>;
1431 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1432 MIMG_Mask<asm#"_V2", channels>;
1433 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1434 MIMG_Mask<asm#"_V4", channels>;
1435 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1436 MIMG_Mask<asm#"_V8", channels>;
1437 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1438 MIMG_Mask<asm#"_V16", channels>;
1441 multiclass MIMG_Gather <bits<7> op, string asm> {
1442 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1443 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1444 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1445 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1448 //===----------------------------------------------------------------------===//
1449 // Vector instruction mappings
1450 //===----------------------------------------------------------------------===//
1452 // Maps an opcode in e32 form to its e64 equivalent
1453 def getVOPe64 : InstrMapping {
1454 let FilterClass = "VOP";
1455 let RowFields = ["OpName"];
1456 let ColFields = ["Size"];
1458 let ValueCols = [["8"]];
1461 // Maps an opcode in e64 form to its e32 equivalent
1462 def getVOPe32 : InstrMapping {
1463 let FilterClass = "VOP";
1464 let RowFields = ["OpName"];
1465 let ColFields = ["Size"];
1467 let ValueCols = [["4"]];
1470 // Maps an original opcode to its commuted version
1471 def getCommuteRev : InstrMapping {
1472 let FilterClass = "VOP2_REV";
1473 let RowFields = ["RevOp"];
1474 let ColFields = ["IsOrig"];
1476 let ValueCols = [["0"]];
1479 def getMaskedMIMGOp : InstrMapping {
1480 let FilterClass = "MIMG_Mask";
1481 let RowFields = ["Op"];
1482 let ColFields = ["Channels"];
1484 let ValueCols = [["1"], ["2"], ["3"] ];
1487 // Maps an commuted opcode to its original version
1488 def getCommuteOrig : InstrMapping {
1489 let FilterClass = "VOP2_REV";
1490 let RowFields = ["RevOp"];
1491 let ColFields = ["IsOrig"];
1493 let ValueCols = [["1"]];
1496 def isDS : InstrMapping {
1497 let FilterClass = "DS";
1498 let RowFields = ["Inst"];
1499 let ColFields = ["Size"];
1501 let ValueCols = [["8"]];
1504 def getMCOpcode : InstrMapping {
1505 let FilterClass = "SIMCInstr";
1506 let RowFields = ["PseudoInstr"];
1507 let ColFields = ["Subtarget"];
1508 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1509 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1512 def getAddr64Inst : InstrMapping {
1513 let FilterClass = "MUBUFAddr64Table";
1514 let RowFields = ["OpName"];
1515 let ColFields = ["IsAddr64"];
1517 let ValueCols = [["1"]];
1520 // Maps an atomic opcode to its version with a return value.
1521 def getAtomicRetOp : InstrMapping {
1522 let FilterClass = "AtomicNoRet";
1523 let RowFields = ["NoRetOp"];
1524 let ColFields = ["IsRet"];
1526 let ValueCols = [["1"]];
1529 // Maps an atomic opcode to its returnless version.
1530 def getAtomicNoRetOp : InstrMapping {
1531 let FilterClass = "AtomicNoRet";
1532 let RowFields = ["NoRetOp"];
1533 let ColFields = ["IsRet"];
1535 let ValueCols = [["0"]];
1538 include "SIInstructions.td"