1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 // SMRD takes a 64bit memory address and can only add an 32bit offset
15 def SIadd64bit32bit : SDNode<"ISD::ADD",
16 SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i32>]>
19 // Transformation function, extract the lower 32bit of a 64bit immediate
20 def LO32 : SDNodeXForm<imm, [{
21 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
24 // Transformation function, extract the upper 32bit of a 64bit immediate
25 def HI32 : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
29 def IMM8bitDWORD : ImmLeaf <
31 return (Imm & ~0x3FC) == 0;
32 }], SDNodeXForm<imm, [{
33 return CurDAG->getTargetConstant(
34 N->getZExtValue() >> 2, MVT::i32);
38 def IMM12bit : ImmLeaf <
40 [{return isUInt<12>(Imm);}]
43 class InlineImm <ValueType vt> : ImmLeaf <vt, [{
44 return -16 <= Imm && Imm <= 64;
48 //===----------------------------------------------------------------------===//
49 // SI assembler operands
50 //===----------------------------------------------------------------------===//
56 class GPR4Align <RegisterClass rc> : Operand <vAny> {
57 let EncoderMethod = "GPR4AlignEncode";
58 let MIOperandInfo = (ops rc:$reg);
61 class GPR2Align <RegisterClass rc> : Operand <iPTR> {
62 let EncoderMethod = "GPR2AlignEncode";
63 let MIOperandInfo = (ops rc:$reg);
66 include "SIInstrFormats.td"
68 //===----------------------------------------------------------------------===//
70 // SI Instruction multiclass helpers.
72 // Instructions with _32 take 32-bit operands.
73 // Instructions with _64 take 64-bit operands.
75 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
76 // encoding is the standard encoding, but instruction that make use of
77 // any of the instruction modifiers must use the 64-bit encoding.
79 // Instructions with _e32 use the 32-bit encoding.
80 // Instructions with _e64 use the 64-bit encoding.
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 //===----------------------------------------------------------------------===//
88 class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
89 : SOP1 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern>;
91 class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
92 : SOP1 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern>;
94 class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
95 : SOP2 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
97 class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
98 : SOP2 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
100 class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
101 : SOPC <op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
103 class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
104 : SOPC <op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
106 class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
107 : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
109 class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
110 : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
112 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
114 op, 1, (outs dstClass:$dst),
115 (ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
120 op, 0, (outs dstClass:$dst),
121 (ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
126 //===----------------------------------------------------------------------===//
127 // Vector ALU classes
128 //===----------------------------------------------------------------------===//
130 class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
131 op, (outs VReg_32:$dst),
132 (ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3,
133 i32imm:$src4, i32imm:$src5, i32imm:$src6),
137 class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
138 op, (outs VReg_64:$dst),
139 (ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2,
140 i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
144 multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
145 string opName, list<dag> pattern> {
148 op, (outs drc:$dst), (ins src:$src0),
149 opName#"_e32 $dst, $src0", pattern
153 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
156 i32imm:$abs, i32imm:$clamp,
157 i32imm:$omod, i32imm:$neg),
158 opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
160 let SRC1 = SIOperand.ZERO;
161 let SRC2 = SIOperand.ZERO;
165 multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern>
166 : VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
168 multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
169 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
171 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
172 string opName, list<dag> pattern> :
174 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
177 multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
179 def _e32 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
181 def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
186 multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
187 def _e32: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
190 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
195 multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
196 string opName, list<dag> pattern> {
198 def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>;
200 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
202 (ins arc:$src0, vrc:$src1,
203 InstFlag:$abs, InstFlag:$clamp,
204 InstFlag:$omod, InstFlag:$neg),
207 let SRC2 = SIOperand.ZERO;
211 multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern>
212 : VOPC_Helper <op, VReg_32, VSrc_32, opName, pattern>;
214 multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern>
215 : VOPC_Helper <op, VReg_64, VSrc_64, opName, pattern>;
217 //===----------------------------------------------------------------------===//
218 // Vector I/O classes
219 //===----------------------------------------------------------------------===//
221 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
224 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
225 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
226 GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
233 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
235 (outs regClass:$dst),
236 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
237 i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
238 i1imm:$tfe, SSrc_32:$soffset),
245 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
247 (outs regClass:$dst),
248 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
249 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
250 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
257 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
259 (outs VReg_128:$vdata),
260 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
261 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
262 GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
269 include "SIInstructions.td"